[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_soc_ErrSteering_8core_UE_CE.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_soc_ErrSteering_8core_UE_CE.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap

#define ENABLE_PCIE_LINK_TRAINING    
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

#define MEM32_RD_ADDR 		mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)

#define DMA_DATA_ADDR   	0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define SOC_ERR_STEERING_REG	0x9001041000
#define	SYNC_ADDR	0x55500000

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Recoverable_Sw_error_trap
.global	 My_Corrected_ECC_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

get_th_id:
	ta	T_RD_THID

	cmp	%o1, 0
	be	main_th_0
	nop

	ba	main_all_other_threads

main_th_0:
	! enable bypass in IOMMU
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
	stx	%g3, [%g2]
	ldx	[%g2], %g3

	clr	%i0
	clr	%o0

initialize_SYNC_ADDR:
	setx	SYNC_ADDR, %g7, %o2
	setx	 0x1111111111111111, %g7, %g2
	stx	 %g2, [%o2]

set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

set_eie:
        setx    SOC_EIE_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

	/************************* LOOP of DMA TRIGER *****************************/
	set	START_TH, %o2
trig_dma_loop:
	nop

errorsteer:
	setx	SOC_ERR_STEERING_REG, %g7, %g1
	stx	%o2, [%g1]
	membar	0x40

#ifdef CE
XmtUsrEvnt_ce:
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ce)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * )
	nop
	nop
#else
XmtUsrEvnt_ue:
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ue)) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * )
	nop
	nop
#endif

wait_set:
        setx    SYNC_ADDR, %g7, %g1
delay_loop_trap_taken:
	ldx	[%g1], %g2
	cmp	%g2, %o2		! Each thread writes its TH_ID to SYNC_ADDR at the end of
					! the Trap Handler; TH0 waits to get that value
					! %o2 has the value of Error_Steering TH_ID , where the trap should go
	bne	%xcc, delay_loop_trap_taken 
	nop

add_some_more_delay:
        nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop

loop_control:
	inc	%o2		! %o2 increases each time: from 0, 1, 2, 3 ....63
				! to send Trap to 64 different threads
	cmp	%o2, END_TH
	bne	%xcc, trig_dma_loop
	nop
        /************************* END of LOOP of DMA TRIGER *****************************/

#ifdef	TH0_TRAP
	set	0x30, %g6
wait_for_thread0_err_th0:
	dec	%g6
	cmp	%g6, %g0
timeout_th0:
	be	%xcc, test_failed
	nop

check_trap_taken_th0:
#ifdef  CE     
        cmp     %i0, 0x1       
#else 
        cmp	%o0, 0x1
#endif
	bne	wait_for_thread0_err_th0
	nop
	nop
#endif


passed_th0:
	ba	test_passed
	nop


/************************  TH B ***********************************/
main_all_other_threads:
	clr	%o0
	clr	%i0

	! timeout for TH1=0x400, TH2=0x800
        sllx	%o1, 10, %i6
wait_for_thread0_err:
	dec	%i6
	cmp	%i6, %g0
timeout:
        be	%xcc, test_failed
	nop

check_trap_taken:
#ifdef	CE
	cmp	%i0, 0x1
#else 	
	cmp	%o0, 0x1
#endif
	bne	wait_for_thread0_err	
	nop
	nop

	
test_passed:
	EXIT_GOOD

	
test_failed:
	EXIT_BAD


/************************************************************************
        RAS
        Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
	inc	%o0

check_desr_tt40:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0xb300000000000000, %g7, %g3
	cmp	%g2, %g3
	bne	%xcc, test_failed
	nop

check_per_tt40:
        setx    SOC_PER_REG, %g7, %g1
        ldx     [%g1], %g2
        setx    0x8000000000000000, %g7, %g3    !valid bit
        set     0x1, %g4
        sllx    %g4, ERR_FIELD, %g5
        or      %g3, %g5, %g3
	cmp	%g2, %g3
	bne	%xcc, test_failed
	nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %g1
        stx     %g0, [%g1]
        nop

sync_addr_0x40:
	setx	SYNC_ADDR, %g7, %g1
	stx	%o1, [%g1]

        retry
        nop


 ************************************************************************/
My_Corrected_ECC_error_trap:
	inc	%i0

check_desr_tt63:
	ldxa  [%g0]0x4c, %g2
	nop
	setx	0x8b00000000000000, %g7, %g3
        cmp     %g2, %g3
        bne     %xcc, test_failed
        nop

check_per_tt63:
        setx    SOC_PER_REG, %g7, %g1
	ldx	[%g1], %g2
	setx	0x8000000000000000, %g7, %g3	!valid bit
	set	0x1, %g4
	sllx	%g4, ERR_FIELD, %g5
	or	%g3, %g5, %g3
	cmp	%g2, %g3
	bne	%xcc, test_failed
        nop

clear_per_tt63:
	setx	SOC_PER_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

sync_addr_0x63:
	setx	SYNC_ADDR, %g7, %g1
	stx	%o1, [%g1]

        retry
	nop

/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
	.xword 0x0001020304050607
	.xword 0x08090a0b0c0d0e0f
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f
	.xword 0x6061626364656667
	.xword 0x68696a6b6c6d6e6f
	.xword 0x7071727374757677
	.xword 0x78797a7b7c7d7e7f
	
	.xword 0x8081828384858687
	.xword 0x88898a8b8c8d8e8f
	.xword 0x9091929394959697
	.xword 0x98999a9b9c9d9e9f
	.xword 0xa0a1a2a3a4a5a6a7
	.xword 0xa8a9aaabacadaeaf
	.xword 0xb0b1b2b3b4b5b6b7
	.xword 0xb8b9babbbcbdbebf
	
	.xword 0xc0c1c2c3c4c5c6c7
	.xword 0xc8c9cacbcccdcecf
	.xword 0xd0d1d2d3d4d5d6d7
	.xword 0xd8d9dadbdcdddedf
	.xword 0xe0e1e2e3e4e5e6e7
	.xword 0xe8e9eaebecedeeef
	.xword 0xf0f1f2f3f4f5f6f7
	.xword 0xf8f9fafbfcfdfeff

	.xword 0x0001020304050607
	.xword 0x08090a0b0c0d0e0f
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f
	.xword 0x6061626364656667
	.xword 0x68696a6b6c6d6e6f
	.xword 0x7071727374757677
	.xword 0x78797a7b7c7d7e7f
	
	.xword 0x8081828384858687
	.xword 0x88898a8b8c8d8e8f
	.xword 0x9091929394959697
	.xword 0x98999a9b9c9d9e9f
	.xword 0xa0a1a2a3a4a5a6a7
	.xword 0xa8a9aaabacadaeaf
	.xword 0xb0b1b2b3b4b5b6b7
	.xword 0xb8b9babbbcbdbebf
	
	.xword 0xc0c1c2c3c4c5c6c7
	.xword 0xc8c9cacbcccdcecf
	.xword 0xd0d1d2d3d4d5d6d7
	.xword 0xd8d9dadbdcdddedf
	.xword 0xe0e1e2e3e4e5e6e7
	.xword 0xe8e9eaebecedeeef
	.xword 0xf0f1f2f3f4f5f6f7
	.xword 0xf8f9fafbfcfdfeff
	
/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_soc_ErrSteering_8core_UE_CE.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "hboot.s"
	46	#include "peu_defines.h"
	47
	48	#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	49
	50	#define DMA_DATA_ADDR 0x0000000123456700
	51	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	52	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	53
	54	#define SOC_ERR_STEERING_REG 0x9001041000
	55	#define SYNC_ADDR 0x55500000
	56
	57	/************************************************************************
	58	Test case code start
	59	************************************************************************/
	60	.text
	61	.global main
	62	.global My_Recoverable_Sw_error_trap
	63	.global My_Corrected_ECC_error_trap
	64
65	main:
66	ta T_CHANGE_HPRIV
67	nop
68
69	get_th_id:
70	ta T_RD_THID
71
72	cmp %o1, 0
73	be main_th_0
74	nop
75
76	ba main_all_other_threads
77
78	main_th_0:
79	! enable bypass in IOMMU
80	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
81	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
82	stx %g3, [%g2]
83	ldx [%g2], %g3
84
85	clr %i0
86	clr %o0
87
88	initialize_SYNC_ADDR:
89	setx SYNC_ADDR, %g7, %o2
90	setx 0x1111111111111111, %g7, %g2
91	stx %g2, [%o2]
92
93	set_ejr:
94	set 0x1, %i1
95	sllx %i1, ERR_FIELD, %i2
96	setx SOC_EJR_REG, %l7, %i3
97	stx %i2, [%i3]
98	membar 0x40
99
100	set_eie:
101	setx SOC_EIE_REG, %l7, %i3
102	stx %i2, [%i3]
103	membar 0x40
104
105	/*********************** LOOP of DMA TRIGER ***************************/
106	set START_TH, %o2
107	trig_dma_loop:
108	nop
109
110	errorsteer:
111	setx SOC_ERR_STEERING_REG, %g7, %g1
112	stx %o2, [%g1]
113	membar 0x40
114
115	#ifdef CE
116	XmtUsrEvnt_ce:
117	nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ce)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, , )
118	nop
119	nop
120	#else
121	XmtUsrEvnt_ue:
122	nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ue)) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, , )
123	nop
124	nop
125	#endif
126
127	wait_set:
128	setx SYNC_ADDR, %g7, %g1
129	delay_loop_trap_taken:
130	ldx [%g1], %g2
131	cmp %g2, %o2 ! Each thread writes its TH_ID to SYNC_ADDR at the end of
132	! the Trap Handler; TH0 waits to get that value
133	! %o2 has the value of Error_Steering TH_ID , where the trap should go
134	bne %xcc, delay_loop_trap_taken
135	nop
136
137	add_some_more_delay:
138	nop; nop; nop; nop
139	nop; nop; nop; nop
140	nop; nop; nop; nop
141	nop; nop; nop; nop
142	nop; nop; nop; nop
143
144	loop_control:
145	inc %o2 ! %o2 increases each time: from 0, 1, 2, 3 ....63
146	! to send Trap to 64 different threads
147	cmp %o2, END_TH
148	bne %xcc, trig_dma_loop
149	nop
150	/*********************** END of LOOP of DMA TRIGER ***************************/
151
152	#ifdef TH0_TRAP
153	set 0x30, %g6
154	wait_for_thread0_err_th0:
155	dec %g6
156	cmp %g6, %g0
157	timeout_th0:
158	be %xcc, test_failed
159	nop
160
161	check_trap_taken_th0:
162	#ifdef CE
163	cmp %i0, 0x1
164	#else
165	cmp %o0, 0x1
166	#endif
167	bne wait_for_thread0_err_th0
168	nop
169	nop
170	#endif
171
172
173	passed_th0:
174	ba test_passed
175	nop
176
177
178	/********************** TH B *********************************/
179	main_all_other_threads:
180	clr %o0
181	clr %i0
182
183	! timeout for TH1=0x400, TH2=0x800
184	sllx %o1, 10, %i6
185	wait_for_thread0_err:
186	dec %i6
187	cmp %i6, %g0
188	timeout:
189	be %xcc, test_failed
190	nop
191
192	check_trap_taken:
193	#ifdef CE
194	cmp %i0, 0x1
195	#else
196	cmp %o0, 0x1
197	#endif
198	bne wait_for_thread0_err
199	nop
200	nop
201
202
203	test_passed:
204	EXIT_GOOD
205
206
207	test_failed:
208	EXIT_BAD
209
210
211	/************************************************************************
212	RAS
213	Trap Handlers
214	************************************************************************/
215	My_Recoverable_Sw_error_trap:
216	inc %o0
217
218	check_desr_tt40:
219	ldxa [%g0]0x4c, %g2
220	nop
221	setx 0xb300000000000000, %g7, %g3
222	cmp %g2, %g3
223	bne %xcc, test_failed
224	nop
225
226	check_per_tt40:
227	setx SOC_PER_REG, %g7, %g1
228	ldx [%g1], %g2
229	setx 0x8000000000000000, %g7, %g3 !valid bit
230	set 0x1, %g4
231	sllx %g4, ERR_FIELD, %g5
232	or %g3, %g5, %g3
233	cmp %g2, %g3
234	bne %xcc, test_failed
235	nop
236
237	clear_per_tt40:
238	setx SOC_PER_REG, %l7, %g1
239	stx %g0, [%g1]
240	nop
241
242	sync_addr_0x40:
243	setx SYNC_ADDR, %g7, %g1
244	stx %o1, [%g1]
245
246	retry
247	nop
248
249
250	************************************************************************/
251	My_Corrected_ECC_error_trap:
252	inc %i0
253
254	check_desr_tt63:
255	ldxa [%g0]0x4c, %g2
256	nop
257	setx 0x8b00000000000000, %g7, %g3
258	cmp %g2, %g3
259	bne %xcc, test_failed
260	nop
261
262	check_per_tt63:
263	setx SOC_PER_REG, %g7, %g1
264	ldx [%g1], %g2
265	setx 0x8000000000000000, %g7, %g3 !valid bit
266	set 0x1, %g4
267	sllx %g4, ERR_FIELD, %g5
268	or %g3, %g5, %g3
269	cmp %g2, %g3
270	bne %xcc, test_failed
271	nop
272
273	clear_per_tt63:
274	setx SOC_PER_REG, %l7, %g1
275	stx %g0, [%g1]
276	nop
277
278	sync_addr_0x63:
279	setx SYNC_ADDR, %g7, %g1
280	stx %o1, [%g1]
281
282	retry
283	nop
284
285	/************************************************************************
286	Test case data start
287	************************************************************************/
288
289	SECTION .DATA DATA_VA=DMA_DATA_ADDR
290	attr_data {
291	Name = .DATA,
292	hypervisor,
293	compressimage
294	}
295
296	.data
297	.xword 0x0001020304050607
298	.xword 0x08090a0b0c0d0e0f
299	.xword 0x1011121314151617
300	.xword 0x18191a1b1c1d1e1f
301	.xword 0x2021222324252627
302	.xword 0x28292a2b2c2d2e2f
303	.xword 0x3031323334353637
304	.xword 0x38393a3b3c3d3e3f
305
306	.xword 0x4041424344454647
307	.xword 0x48494a4b4c4d4e4f
308	.xword 0x5051525354555657
309	.xword 0x58595a5b5c5d5e5f
310	.xword 0x6061626364656667
311	.xword 0x68696a6b6c6d6e6f
312	.xword 0x7071727374757677
313	.xword 0x78797a7b7c7d7e7f
314
315	.xword 0x8081828384858687
316	.xword 0x88898a8b8c8d8e8f
317	.xword 0x9091929394959697
318	.xword 0x98999a9b9c9d9e9f
319	.xword 0xa0a1a2a3a4a5a6a7
320	.xword 0xa8a9aaabacadaeaf
321	.xword 0xb0b1b2b3b4b5b6b7
322	.xword 0xb8b9babbbcbdbebf
323
324	.xword 0xc0c1c2c3c4c5c6c7
325	.xword 0xc8c9cacbcccdcecf
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369	/************************************************************************/