[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / cmp / cmp_master_park_unpark_all_w1s_w1c.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: cmp_master_park_unpark_all_w1s_w1c.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "ncu_defines.h"


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	/* Get thread ID */

        ta      T_RD_THID
	nop
	cmp	%o1, 0
	be	main_t0			! branch if thread 0
	nop

	ba	main_t1_t63		! branch if not thread 0
	nop

/************************************************************************
   Thread 0 Code
 ************************************************************************/

	/* Park all the other threads one by one. */
main_t0:
	setx	ASI_CMP_CORE_RUNNING_W1C, %g1, %g2
	set	0x2, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 1
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 2
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 3
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 4
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 5
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 6
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 7
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 8
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 9
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 10
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 11
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 12
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 13
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 14
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 15
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 16
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 17
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 18
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 19
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 20
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 21
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 22
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 23
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 24
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 25
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 26
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 27
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 28
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 29
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 30
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 31
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 32
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 33
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 34
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 35
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 36
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 37
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 38
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 39
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 40
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 41
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 42
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 43
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 44
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 45
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 46
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 47
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 48
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 49
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 50
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 51
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 52
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 53
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 54
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 55
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 56
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 57
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 58
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 59
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 60
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 61
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 62
	sllx	%g3, 1, %g3
	stxa    %g3, [%g2]ASI_CMP_CORE		! thread 63

	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
t0_0:
        setx    ASI_CMP_CORE_RUNNING_RW, %g1, %g2
        setx    ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
	set	0x100, %g7

t0_loop_1_top:
	cmp	%g7, 0
	beq	local_test_failed		! fail on a timeout
	dec	%g7

	ldxa	[%g3]ASI_CMP_CORE, %g4		! CORE_RUNNING_STATUS
	cmp	%g4, 1
	bne	t0_loop_1_top
	nop

t0_1:
	ldxa	[%g2]ASI_CMP_CORE, %g5		! CORE_RUNNING_RW
	cmp	%g4, %g5
	bne	local_test_failed		! fail on RW != STATUS
	nop

	/* Now unpark all the other threads one by one. */
t0_2:
	setx	ASI_CMP_CORE_RUNNING_W1S, %g1, %g2
	set	2, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 1
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 2
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 3
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 4
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 5
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 6
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 7
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 8
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 9
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 10
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 11
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 12
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 13
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 14
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 15
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 16
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 17
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 18
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 19
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 20
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 21
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 22
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 23
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 24
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 25
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 26
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 27
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 28
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 29
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 30
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 31
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 32
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 33
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 34
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 35
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 36
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 37
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 38
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 39
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 40
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 41
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 42
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 43
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 44
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 45
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 46
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 47
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 48
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 49
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 50
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 51
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 52
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 53
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 54
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 55
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 56
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 57
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 58
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 59
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 60
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 61
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 62
	sllx	%g3, 1, %g3
	stxa	%g3, [%g2]ASI_CMP_CORE		! thread 63

	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
t0_3:
        setx    ASI_CMP_CORE_RUNNING_RW, %g1, %g2
        setx    ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
	set	0x100, %g7
	orn	%g0, %g0, %g6

t0_loop_2_top:
	cmp	%g7, 0
	beq	local_test_failed		! fail on a timeout
	dec	%g7

	ldxa	[%g3]ASI_CMP_CORE, %g4		! CORE_RUNNING_STATUS
	cmp	%g4, %g6
	bne	t0_loop_2_top
	nop

t0_4:
	ldxa	[%g2]ASI_CMP_CORE, %g5		! CORE_RUNNING_RW
	cmp	%g4, %g5
	bne	local_test_failed		! fail on RW != STATUS
	nop

	/* Signal all the other threads that were done */
t0_5:
	setx	user_data_start, %g1, %g2
	set	1, %g3
	stx	%g3, [%g2]

	/* Done */

	ba	test_passed
	nop

/************************************************************************
   Thread 1 to 63 Code
 ************************************************************************/

	/* Wait till thread 0 says were done */
main_t1_t63:
	setx	0x1000, %g1, %g7
	setx	user_data_start, %g1, %g2

t1_t63_wait_loop_top:
	cmp	%g7, 0
	beq	local_test_failed		! fail on a timeout
	dec	%g7

	ldx	[%g2], %g4
	cmp	%g4, 1
	bne	t1_t63_wait_loop_top
	nop

	/* Done */

	ba	test_passed
	nop


test_passed:
	EXIT_GOOD

local_test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/

.align	1024
.data
user_data_start:
	.word	0x0
	.word	0x0
	.word	0x0
	.word	0x0
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: cmp_master_park_unpark_all_w1s_w1c.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#include "hboot.s"
	41	#include "ncu_defines.h"
	42
	43
	44
	45	/************************************************************************
	46	Test case code start
	47	************************************************************************/
	48	.text
	49	.global main
	50
	51	main:
	52	ta T_CHANGE_HPRIV
	53	nop
	54
	55	/* Get thread ID */
	56
	57	ta T_RD_THID
	58	nop
	59	cmp %o1, 0
	60	be main_t0 ! branch if thread 0
	61	nop
	62
	63	ba main_t1_t63 ! branch if not thread 0
	64	nop
65
66	/************************************************************************
67	Thread 0 Code
68	************************************************************************/
69
70	/* Park all the other threads one by one. */
71	main_t0:
72	setx ASI_CMP_CORE_RUNNING_W1C, %g1, %g2
73	set 0x2, %g3
74	stxa %g3, [%g2]ASI_CMP_CORE ! thread 1
75	sllx %g3, 1, %g3
76	stxa %g3, [%g2]ASI_CMP_CORE ! thread 2
77	sllx %g3, 1, %g3
78	stxa %g3, [%g2]ASI_CMP_CORE ! thread 3
79	sllx %g3, 1, %g3
80	stxa %g3, [%g2]ASI_CMP_CORE ! thread 4
81	sllx %g3, 1, %g3
82	stxa %g3, [%g2]ASI_CMP_CORE ! thread 5
83	sllx %g3, 1, %g3
84	stxa %g3, [%g2]ASI_CMP_CORE ! thread 6
85	sllx %g3, 1, %g3
86	stxa %g3, [%g2]ASI_CMP_CORE ! thread 7
87	sllx %g3, 1, %g3
88	stxa %g3, [%g2]ASI_CMP_CORE ! thread 8
89	sllx %g3, 1, %g3
90	stxa %g3, [%g2]ASI_CMP_CORE ! thread 9
91	sllx %g3, 1, %g3
92	stxa %g3, [%g2]ASI_CMP_CORE ! thread 10
93	sllx %g3, 1, %g3
94	stxa %g3, [%g2]ASI_CMP_CORE ! thread 11
95	sllx %g3, 1, %g3
96	stxa %g3, [%g2]ASI_CMP_CORE ! thread 12
97	sllx %g3, 1, %g3
98	stxa %g3, [%g2]ASI_CMP_CORE ! thread 13
99	sllx %g3, 1, %g3
100	stxa %g3, [%g2]ASI_CMP_CORE ! thread 14
101	sllx %g3, 1, %g3
102	stxa %g3, [%g2]ASI_CMP_CORE ! thread 15
103	sllx %g3, 1, %g3
104	stxa %g3, [%g2]ASI_CMP_CORE ! thread 16
105	sllx %g3, 1, %g3
106	stxa %g3, [%g2]ASI_CMP_CORE ! thread 17
107	sllx %g3, 1, %g3
108	stxa %g3, [%g2]ASI_CMP_CORE ! thread 18
109	sllx %g3, 1, %g3
110	stxa %g3, [%g2]ASI_CMP_CORE ! thread 19
111	sllx %g3, 1, %g3
112	stxa %g3, [%g2]ASI_CMP_CORE ! thread 20
113	sllx %g3, 1, %g3
114	stxa %g3, [%g2]ASI_CMP_CORE ! thread 21
115	sllx %g3, 1, %g3
116	stxa %g3, [%g2]ASI_CMP_CORE ! thread 22
117	sllx %g3, 1, %g3
118	stxa %g3, [%g2]ASI_CMP_CORE ! thread 23
119	sllx %g3, 1, %g3
120	stxa %g3, [%g2]ASI_CMP_CORE ! thread 24
121	sllx %g3, 1, %g3
122	stxa %g3, [%g2]ASI_CMP_CORE ! thread 25
123	sllx %g3, 1, %g3
124	stxa %g3, [%g2]ASI_CMP_CORE ! thread 26
125	sllx %g3, 1, %g3
126	stxa %g3, [%g2]ASI_CMP_CORE ! thread 27
127	sllx %g3, 1, %g3
128	stxa %g3, [%g2]ASI_CMP_CORE ! thread 28
129	sllx %g3, 1, %g3
130	stxa %g3, [%g2]ASI_CMP_CORE ! thread 29
131	sllx %g3, 1, %g3
132	stxa %g3, [%g2]ASI_CMP_CORE ! thread 30
133	sllx %g3, 1, %g3
134	stxa %g3, [%g2]ASI_CMP_CORE ! thread 31
135	sllx %g3, 1, %g3
136	stxa %g3, [%g2]ASI_CMP_CORE ! thread 32
137	sllx %g3, 1, %g3
138	stxa %g3, [%g2]ASI_CMP_CORE ! thread 33
139	sllx %g3, 1, %g3
140	stxa %g3, [%g2]ASI_CMP_CORE ! thread 34
141	sllx %g3, 1, %g3
142	stxa %g3, [%g2]ASI_CMP_CORE ! thread 35
143	sllx %g3, 1, %g3
144	stxa %g3, [%g2]ASI_CMP_CORE ! thread 36
145	sllx %g3, 1, %g3
146	stxa %g3, [%g2]ASI_CMP_CORE ! thread 37
147	sllx %g3, 1, %g3
148	stxa %g3, [%g2]ASI_CMP_CORE ! thread 38
149	sllx %g3, 1, %g3
150	stxa %g3, [%g2]ASI_CMP_CORE ! thread 39
151	sllx %g3, 1, %g3
152	stxa %g3, [%g2]ASI_CMP_CORE ! thread 40
153	sllx %g3, 1, %g3
154	stxa %g3, [%g2]ASI_CMP_CORE ! thread 41
155	sllx %g3, 1, %g3
156	stxa %g3, [%g2]ASI_CMP_CORE ! thread 42
157	sllx %g3, 1, %g3
158	stxa %g3, [%g2]ASI_CMP_CORE ! thread 43
159	sllx %g3, 1, %g3
160	stxa %g3, [%g2]ASI_CMP_CORE ! thread 44
161	sllx %g3, 1, %g3
162	stxa %g3, [%g2]ASI_CMP_CORE ! thread 45
163	sllx %g3, 1, %g3
164	stxa %g3, [%g2]ASI_CMP_CORE ! thread 46
165	sllx %g3, 1, %g3
166	stxa %g3, [%g2]ASI_CMP_CORE ! thread 47
167	sllx %g3, 1, %g3
168	stxa %g3, [%g2]ASI_CMP_CORE ! thread 48
169	sllx %g3, 1, %g3
170	stxa %g3, [%g2]ASI_CMP_CORE ! thread 49
171	sllx %g3, 1, %g3
172	stxa %g3, [%g2]ASI_CMP_CORE ! thread 50
173	sllx %g3, 1, %g3
174	stxa %g3, [%g2]ASI_CMP_CORE ! thread 51
175	sllx %g3, 1, %g3
176	stxa %g3, [%g2]ASI_CMP_CORE ! thread 52
177	sllx %g3, 1, %g3
178	stxa %g3, [%g2]ASI_CMP_CORE ! thread 53
179	sllx %g3, 1, %g3
180	stxa %g3, [%g2]ASI_CMP_CORE ! thread 54
181	sllx %g3, 1, %g3
182	stxa %g3, [%g2]ASI_CMP_CORE ! thread 55
183	sllx %g3, 1, %g3
184	stxa %g3, [%g2]ASI_CMP_CORE ! thread 56
185	sllx %g3, 1, %g3
186	stxa %g3, [%g2]ASI_CMP_CORE ! thread 57
187	sllx %g3, 1, %g3
188	stxa %g3, [%g2]ASI_CMP_CORE ! thread 58
189	sllx %g3, 1, %g3
190	stxa %g3, [%g2]ASI_CMP_CORE ! thread 59
191	sllx %g3, 1, %g3
192	stxa %g3, [%g2]ASI_CMP_CORE ! thread 60
193	sllx %g3, 1, %g3
194	stxa %g3, [%g2]ASI_CMP_CORE ! thread 61
195	sllx %g3, 1, %g3
196	stxa %g3, [%g2]ASI_CMP_CORE ! thread 62
197	sllx %g3, 1, %g3
198	stxa %g3, [%g2]ASI_CMP_CORE ! thread 63
199
200	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
201	t0_0:
202	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
203	setx ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
204	set 0x100, %g7
205
206	t0_loop_1_top:
207	cmp %g7, 0
208	beq local_test_failed ! fail on a timeout
209	dec %g7
210
211	ldxa [%g3]ASI_CMP_CORE, %g4 ! CORE_RUNNING_STATUS
212	cmp %g4, 1
213	bne t0_loop_1_top
214	nop
215
216	t0_1:
217	ldxa [%g2]ASI_CMP_CORE, %g5 ! CORE_RUNNING_RW
218	cmp %g4, %g5
219	bne local_test_failed ! fail on RW != STATUS
220	nop
221
222	/* Now unpark all the other threads one by one. */
223	t0_2:
224	setx ASI_CMP_CORE_RUNNING_W1S, %g1, %g2
225	set 2, %g3
226	stxa %g3, [%g2]ASI_CMP_CORE ! thread 1
227	sllx %g3, 1, %g3
228	stxa %g3, [%g2]ASI_CMP_CORE ! thread 2
229	sllx %g3, 1, %g3
230	stxa %g3, [%g2]ASI_CMP_CORE ! thread 3
231	sllx %g3, 1, %g3
232	stxa %g3, [%g2]ASI_CMP_CORE ! thread 4
233	sllx %g3, 1, %g3
234	stxa %g3, [%g2]ASI_CMP_CORE ! thread 5
235	sllx %g3, 1, %g3
236	stxa %g3, [%g2]ASI_CMP_CORE ! thread 6
237	sllx %g3, 1, %g3
238	stxa %g3, [%g2]ASI_CMP_CORE ! thread 7
239	sllx %g3, 1, %g3
240	stxa %g3, [%g2]ASI_CMP_CORE ! thread 8
241	sllx %g3, 1, %g3
242	stxa %g3, [%g2]ASI_CMP_CORE ! thread 9
243	sllx %g3, 1, %g3
244	stxa %g3, [%g2]ASI_CMP_CORE ! thread 10
245	sllx %g3, 1, %g3
246	stxa %g3, [%g2]ASI_CMP_CORE ! thread 11
247	sllx %g3, 1, %g3
248	stxa %g3, [%g2]ASI_CMP_CORE ! thread 12
249	sllx %g3, 1, %g3
250	stxa %g3, [%g2]ASI_CMP_CORE ! thread 13
251	sllx %g3, 1, %g3
252	stxa %g3, [%g2]ASI_CMP_CORE ! thread 14
253	sllx %g3, 1, %g3
254	stxa %g3, [%g2]ASI_CMP_CORE ! thread 15
255	sllx %g3, 1, %g3
256	stxa %g3, [%g2]ASI_CMP_CORE ! thread 16
257	sllx %g3, 1, %g3
258	stxa %g3, [%g2]ASI_CMP_CORE ! thread 17
259	sllx %g3, 1, %g3
260	stxa %g3, [%g2]ASI_CMP_CORE ! thread 18
261	sllx %g3, 1, %g3
262	stxa %g3, [%g2]ASI_CMP_CORE ! thread 19
263	sllx %g3, 1, %g3
264	stxa %g3, [%g2]ASI_CMP_CORE ! thread 20
265	sllx %g3, 1, %g3
266	stxa %g3, [%g2]ASI_CMP_CORE ! thread 21
267	sllx %g3, 1, %g3
268	stxa %g3, [%g2]ASI_CMP_CORE ! thread 22
269	sllx %g3, 1, %g3
270	stxa %g3, [%g2]ASI_CMP_CORE ! thread 23
271	sllx %g3, 1, %g3
272	stxa %g3, [%g2]ASI_CMP_CORE ! thread 24
273	sllx %g3, 1, %g3
274	stxa %g3, [%g2]ASI_CMP_CORE ! thread 25
275	sllx %g3, 1, %g3
276	stxa %g3, [%g2]ASI_CMP_CORE ! thread 26
277	sllx %g3, 1, %g3
278	stxa %g3, [%g2]ASI_CMP_CORE ! thread 27
279	sllx %g3, 1, %g3
280	stxa %g3, [%g2]ASI_CMP_CORE ! thread 28
281	sllx %g3, 1, %g3
282	stxa %g3, [%g2]ASI_CMP_CORE ! thread 29
283	sllx %g3, 1, %g3
284	stxa %g3, [%g2]ASI_CMP_CORE ! thread 30
285	sllx %g3, 1, %g3
286	stxa %g3, [%g2]ASI_CMP_CORE ! thread 31
287	sllx %g3, 1, %g3
288	stxa %g3, [%g2]ASI_CMP_CORE ! thread 32
289	sllx %g3, 1, %g3
290	stxa %g3, [%g2]ASI_CMP_CORE ! thread 33
291	sllx %g3, 1, %g3
292	stxa %g3, [%g2]ASI_CMP_CORE ! thread 34
293	sllx %g3, 1, %g3
294	stxa %g3, [%g2]ASI_CMP_CORE ! thread 35
295	sllx %g3, 1, %g3
296	stxa %g3, [%g2]ASI_CMP_CORE ! thread 36
297	sllx %g3, 1, %g3
298	stxa %g3, [%g2]ASI_CMP_CORE ! thread 37
299	sllx %g3, 1, %g3
300	stxa %g3, [%g2]ASI_CMP_CORE ! thread 38
301	sllx %g3, 1, %g3
302	stxa %g3, [%g2]ASI_CMP_CORE ! thread 39
303	sllx %g3, 1, %g3
304	stxa %g3, [%g2]ASI_CMP_CORE ! thread 40
305	sllx %g3, 1, %g3
306	stxa %g3, [%g2]ASI_CMP_CORE ! thread 41
307	sllx %g3, 1, %g3
308	stxa %g3, [%g2]ASI_CMP_CORE ! thread 42
309	sllx %g3, 1, %g3
310	stxa %g3, [%g2]ASI_CMP_CORE ! thread 43
311	sllx %g3, 1, %g3
312	stxa %g3, [%g2]ASI_CMP_CORE ! thread 44
313	sllx %g3, 1, %g3
314	stxa %g3, [%g2]ASI_CMP_CORE ! thread 45
315	sllx %g3, 1, %g3
316	stxa %g3, [%g2]ASI_CMP_CORE ! thread 46
317	sllx %g3, 1, %g3
318	stxa %g3, [%g2]ASI_CMP_CORE ! thread 47
319	sllx %g3, 1, %g3
320	stxa %g3, [%g2]ASI_CMP_CORE ! thread 48
321	sllx %g3, 1, %g3
322	stxa %g3, [%g2]ASI_CMP_CORE ! thread 49
323	sllx %g3, 1, %g3
324	stxa %g3, [%g2]ASI_CMP_CORE ! thread 50
325	sllx %g3, 1, %g3
326	stxa %g3, [%g2]ASI_CMP_CORE ! thread 51
327	sllx %g3, 1, %g3
328	stxa %g3, [%g2]ASI_CMP_CORE ! thread 52
329	sllx %g3, 1, %g3
330	stxa %g3, [%g2]ASI_CMP_CORE ! thread 53
331	sllx %g3, 1, %g3
332	stxa %g3, [%g2]ASI_CMP_CORE ! thread 54
333	sllx %g3, 1, %g3
334	stxa %g3, [%g2]ASI_CMP_CORE ! thread 55
335	sllx %g3, 1, %g3
336	stxa %g3, [%g2]ASI_CMP_CORE ! thread 56
337	sllx %g3, 1, %g3
338	stxa %g3, [%g2]ASI_CMP_CORE ! thread 57
339	sllx %g3, 1, %g3
340	stxa %g3, [%g2]ASI_CMP_CORE ! thread 58
341	sllx %g3, 1, %g3
342	stxa %g3, [%g2]ASI_CMP_CORE ! thread 59
343	sllx %g3, 1, %g3
344	stxa %g3, [%g2]ASI_CMP_CORE ! thread 60
345	sllx %g3, 1, %g3
346	stxa %g3, [%g2]ASI_CMP_CORE ! thread 61
347	sllx %g3, 1, %g3
348	stxa %g3, [%g2]ASI_CMP_CORE ! thread 62
349	sllx %g3, 1, %g3
350	stxa %g3, [%g2]ASI_CMP_CORE ! thread 63
351
352	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
353	t0_3:
354	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
355	setx ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
356	set 0x100, %g7
357	orn %g0, %g0, %g6
358
359	t0_loop_2_top:
360	cmp %g7, 0
361	beq local_test_failed ! fail on a timeout
362	dec %g7
363
364	ldxa [%g3]ASI_CMP_CORE, %g4 ! CORE_RUNNING_STATUS
365	cmp %g4, %g6
366	bne t0_loop_2_top
367	nop
368
369	t0_4:
370	ldxa [%g2]ASI_CMP_CORE, %g5 ! CORE_RUNNING_RW
371	cmp %g4, %g5
372	bne local_test_failed ! fail on RW != STATUS
373	nop
374
375	/* Signal all the other threads that were done */
376	t0_5:
377	setx user_data_start, %g1, %g2
378	set 1, %g3
379	stx %g3, [%g2]
380
381	/* Done */
382
383	ba test_passed
384	nop
385
386	/************************************************************************
387	Thread 1 to 63 Code
388	************************************************************************/
389
390	/* Wait till thread 0 says were done */
391	main_t1_t63:
392	setx 0x1000, %g1, %g7
393	setx user_data_start, %g1, %g2
394
395	t1_t63_wait_loop_top:
396	cmp %g7, 0
397	beq local_test_failed ! fail on a timeout
398	dec %g7
399
400	ldx [%g2], %g4
401	cmp %g4, 1
402	bne t1_t63_wait_loop_top
403	nop
404
405	/* Done */
406
407	ba test_passed
408	nop
409
410
411	test_passed:
412	EXIT_GOOD
413
414	local_test_failed:
415	EXIT_BAD
416
417
418
419	/************************************************************************
420	Test case data start
421	************************************************************************/
422
423	.align 1024
424	.data
425	user_data_start:
426	.word 0x0
427	.word 0x0
428	.word 0x0
429	.word 0x0