[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / cmp / ncu_ios_nack.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: ncu_ios_nack.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Data_access_error_0x32  My_Precise_data_access_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO


#define FFLP_CONFIG             0x00100
#define FZC_FFLP_BASE_OFFSET    0x020000
#define FZC_FFLP_BASE_ADDRESS   0x380000

#include "hboot.s"
!#include "asi_s.h"

.text
.global	 main
.global  My_Precise_data_access_error_trap


main:
    ta   T_CHANGE_HPRIV

get_th_id:
    ta   %icc, T_RD_THID

//    cmp  %o1,0x0
//    bne  test_pass
    nop


acc_ssi_timeout:
!Write then read data of  INT_VEC_REG of NCU
    setx 0x000000ff00010088,%g7,%g1
    setx ssi_timeout, %g7,%g2

    ldx  [%g2],%g4
    stx  %g4,[%g1]

    ldx [%g1], %g5
    cmp %g4, %g5
    
    bne %xcc, test_fail
    nop

acc_int_vec_in_ncu:
!Write then read data of  INT_VEC_REG of NCU
    setx 0x0000008000000a00,%g7,%g1
    setx int_vec_data,%g7,%g2

    ldx  [%g2],%g4
    stx  %g4,[%g1]

    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_int_vec_in_ncu_nack:
!Write then read data of  INT_VEC_REG of NCU
    setx 0x00000080f0000a00,%g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop

acc_int_vec_in_ncu1:
!Write then read data of  INT_VEC_REG of NCU
    setx 0x0000008000000a00,%g7,%g1
    setx int_vec_data,%g7,%g2

    ldx  [%g2],%g4
    stx  %g4,[%g1]

    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_reset_fee_in_rst:
!Write then read data of  RESET_FEE of RST block
 setx 0x0000008900000820,%g7,%g1
    setx reset_fee,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_reset_fee_in_rst_nack:
!Write then read data of  RESET_FEE of RST block
 setx 0x00000089f0000820,%g7,%g1
    setx 0,%g7,%o1
    ldx  [%g1],%g5
    cmp %g0, %o1    !! check trap active
    be %xcc, test_fail
    nop


acc_reset_fee_in_rst1:
!Write then read data of  RESET_FEE of RST block
 setx 0x0000008900000820,%g7,%g1
    setx reset_fee,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu0:
!Write then read data of  SERDES Test Configuration Bus Register of MCU0 block
 setx 0x00000084000008e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop
acc_serdes_test_cfg_in_mcu0_nack:
!Write then read data of  SERDES Test Configuration Bus Register of MCU0 block
 setx 0x00000084f00008e0,%g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu0_1:
!Write then read data of  SERDES Test Configuration Bus Register of MCU0 block
 setx 0x00000084000008e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu1:
!Write then read data of  SERDES Test Configuration Bus Register of MCU1 block
 setx 0x00000084000018e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu1_nack:
!Write then read data of  SERDES Test Configuration Bus Register of MCU1 block
 setx 0x00000084f00018e0,%g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu1_1:
!Write then read data of  SERDES Test Configuration Bus Register of MCU1 block
 setx 0x00000084000018e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu2:
!Write then read data of  SERDES Test Configuration Bus Register of MCU2 block
 setx 0x00000084000028e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop
acc_serdes_test_cfg_in_mcu2_nack:
!Write then read data of  SERDES Test Configuration Bus Register of MCU2 block
 setx 0x00000084f00028e0,%g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu2_1:
!Write then read data of  SERDES Test Configuration Bus Register of MCU2 block
 setx 0x00000084000028e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu3:
!Write then read data of  SERDES Test Configuration Bus Register of MCU3 block
 setx 0x00000084000038e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop
acc_serdes_test_cfg_in_mcu3_nack:
!Write then read data of  SERDES Test Configuration Bus Register of MCU3 block
 setx 0x00000084f00038e0,%g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop

acc_serdes_test_cfg_in_mcu3_1:
!Write then read data of  SERDES Test Configuration Bus Register of MCU3 block
 setx 0x00000084000038e0,%g7,%g1
    setx mcu_cfg_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_pll_ctl_in_ccu:
!Write then read data of  PLL_CTL Register of CCU block
 setx 0x0000008300000000,%g7,%g1
    setx pll_ctl_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop
acc_pll_ctl_in_ccu_nack:
!Write then read data of  PLL_CTL Register of CCU block
 setx 0x00000083f0000000,%g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop
acc_pll_ctl_in_ccu1:
!Write then read data of  PLL_CTL Register of CCU block
 setx 0x0000008300000000,%g7,%g1
    setx pll_ctl_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_config_in_niu:
!Write then read data of  PLL_CTL Register of NIU block
 setx config,%g7,%g1
    setx config_data,%g7,%g2
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE
    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop
acc_config_in_niu_nack:
!Write then read data of  PLL_CTL Register of NIU block
 setx 0x00000081f0000000,%g7,%g1
    setx 0,%g7,%o1
    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop

acc_config_in_niu1:
!Write then read data of  PLL_CTL Register of NIU block
 setx config,%g7,%g1
    setx config_data,%g7,%g2
    ldx  [%g2],%g4
    stxa  %g4,[%g1]ASI_PRIMARY_LITTLE
    ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_int_en_in_dmu:
!Write then read data of  INT_EN Register of DMUCSR block
 setx 0x8800631008, %g7,%g1
    setx int_en_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

/*
acc_int_en_in_dmu_nack:
!Write then read data of  INT_EN Register of DMUCSR block
 setx 0x88f0631008, %g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop
*/


acc_int_en_in_dmu1:
!Write then read data of  INT_EN Register of DMUCSR block
 setx 0x8800631008, %g7,%g1
    setx int_en_data,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop

acc_debug_port_cfg_in_dbug1:
!Write then read data of  DEBUG_PORT_CONFIG of DBG1 block
 setx 0x8600000000, %g7,%g1
    setx dbg1_cfg,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    nop 	

acc_debug_port_cfg_in_dbug1_nack:
!Write then read data of  DEBUG_PORT_CONFIG of DBG1 block
 setx 0x86f0000000, %g7,%g1
    setx 0,%g7,%o1
    ldx [%g1], %g5
    cmp %g0, %o1    ! check trap active
    be %xcc, test_fail
    nop 	


acc_debug_port_cfg_in_dbug1_1:
!Write then read data of  DEBUG_PORT_CONFIG of DBG1 block
 setx 0x8600000000, %g7,%g1
    setx dbg1_cfg,%g7,%g2
    ldx  [%g2],%g4
    stx  %g4,[%g1]
    ldx [%g1], %g5
    cmp %g4, %g5
    bne %xcc, test_fail
    ba test_pass	
    nop


My_Precise_data_access_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o1
  ! save trap type value
  rdpr  %tt, %o1
  done
  nop


******************************************************
 * Exit code
 *******************************************************/

test_pass:
EXIT_GOOD

test_fail:
EXIT_BAD


.data
.align 0x100
int_vec_data:
    .xword 0x000000000000002a
    .xword 0x000000000000003f
    .xword 0x0000000000000015
    .xword 0x0000000000000001
    .xword 0x0000000000000002
    .xword 0x0000000000000004
    .xword 0x0000000000000008
    .xword 0x0000000000000010
    .xword 0x0000000000000020


.align 0x100
reset_fee:
    .xword 0x000000000000ff00
    .xword 0x000000000000aa00
    .xword 0x0000000000005500
    .xword 0x0000000000000000
    .xword 0x0000000000008800
    .xword 0x0000000000002200

.align 0x100
mcu_cfg_data:
    .xword 0x000000000000ff00
    .xword 0x000000000000aa00
    .xword 0x0000000000005500
    .xword 0x0000000000000000
    .xword 0x0000000000000000
    .xword 0x0000000000000000

.align 0x100
ssi_timeout:
    .xword 0x0000000000ffffff
    .xword 0x0000000000aaaaaa
    .xword 0x0000000000555555
    .xword 0x000000000056789a
    .xword 0x0000000000df0123
    .xword 0x0000000000789abc

.align 0x100
pll_ctl_data:
    .xword 0x0000001fffffffff
    .xword 0x0000001aaaaaaaaa
    .xword 0x0000000555555555
    .xword 0x000000123456789a
    .xword 0x0000000bcedf0123
    .xword 0x0000001456789abc

.align 0x100
int_en_data:
    .xword 0x0000000000000fff
    .xword 0x0000000000000aaa
    .xword 0x0000000000000555
    .xword 0x000000000000089a
    .xword 0x0000000000000123
    .xword 0x0000000000000abc

.align 0x100
config_data:
    .xword 0x0000000000ffffff
    .xword 0x0000000000aaaaaa
    .xword 0x0000000000555555
    .xword 0x000000000056789a
    .xword 0x0000000000df0123
    .xword 0x0000000000789abc


.align 0x100
wdata:
    .xword 0xffffffffffffffff
    .xword 0xaaaaaaaaaaaaaaaa
    .xword 0x0000000000000000
    .xword 0x5555555555555555
    .xword 0x0123456789abcdef

.align 0x100
dbg1_cfg:
    .xword 0x00000000000000ff
    .xword 0x00000000000000aa
    .xword 0x0000000000000000
    .xword 0x0000000000000055

.align 0x100
debug_cnt_en:
    .xword 0x000000000000000f
    .xword 0x0000000000000000
    .xword 0x000000000000000a
    .xword 0x0000000000000005
    .xword 0x0000000000000002
    .xword 0x0000000000000004
.align 0x100
bit_1_data:
    .xword 0x0000000000000001
    .xword 0x0000000000000000
    .xword 0x0000000000000001
    .xword 0x0000000000000000

busy_data:
    .xword 0x0000000000000040
    .xword 0x0000000000000000
    .xword 0x0000000000000040
    .xword 0x0000000000000000

.align 0x100
data_xword:
    .xword 0x000000faaa000000
    .xword 0x000000fcad000000
    .xword 0x000000f555000000
    .xword 0x000000fabc000000

.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: ncu_ios_nack.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Data_access_error_0x32 My_Precise_data_access_error_trap
	39
	40	#define MAIN_PAGE_NUCLEUS_ALSO
	41	#define MAIN_PAGE_HV_ALSO
	42
	43
	44	#define FFLP_CONFIG 0x00100
	45	#define FZC_FFLP_BASE_OFFSET 0x020000
	46	#define FZC_FFLP_BASE_ADDRESS 0x380000
	47
	48	#include "hboot.s"
	49	!#include "asi_s.h"
	50
	51	.text
	52	.global main
	53	.global My_Precise_data_access_error_trap
	54
	55
	56	main:
	57	ta T_CHANGE_HPRIV
	58
	59	get_th_id:
	60	ta %icc, T_RD_THID
	61
	62	// cmp %o1,0x0
	63	// bne test_pass
	64	nop
65
66
67	acc_ssi_timeout:
68	!Write then read data of INT_VEC_REG of NCU
69	setx 0x000000ff00010088,%g7,%g1
70	setx ssi_timeout, %g7,%g2
71
72	ldx [%g2],%g4
73	stx %g4,[%g1]
74
75	ldx [%g1], %g5
76	cmp %g4, %g5
77
78	bne %xcc, test_fail
79	nop
80
81	acc_int_vec_in_ncu:
82	!Write then read data of INT_VEC_REG of NCU
83	setx 0x0000008000000a00,%g7,%g1
84	setx int_vec_data,%g7,%g2
85
86	ldx [%g2],%g4
87	stx %g4,[%g1]
88
89	ldx [%g1], %g5
90	cmp %g4, %g5
91	bne %xcc, test_fail
92	nop
93
94	acc_int_vec_in_ncu_nack:
95	!Write then read data of INT_VEC_REG of NCU
96	setx 0x00000080f0000a00,%g7,%g1
97	setx 0,%g7,%o1
98	ldx [%g1], %g5
99	cmp %g0, %o1 ! check trap active
100	be %xcc, test_fail
101	nop
102
103	acc_int_vec_in_ncu1:
104	!Write then read data of INT_VEC_REG of NCU
105	setx 0x0000008000000a00,%g7,%g1
106	setx int_vec_data,%g7,%g2
107
108	ldx [%g2],%g4
109	stx %g4,[%g1]
110
111	ldx [%g1], %g5
112	cmp %g4, %g5
113	bne %xcc, test_fail
114	nop
115
116	acc_reset_fee_in_rst:
117	!Write then read data of RESET_FEE of RST block
118	setx 0x0000008900000820,%g7,%g1
119	setx reset_fee,%g7,%g2
120	ldx [%g2],%g4
121	stx %g4,[%g1]
122	ldx [%g1], %g5
123	cmp %g4, %g5
124	bne %xcc, test_fail
125	nop
126
127	acc_reset_fee_in_rst_nack:
128	!Write then read data of RESET_FEE of RST block
129	setx 0x00000089f0000820,%g7,%g1
130	setx 0,%g7,%o1
131	ldx [%g1],%g5
132	cmp %g0, %o1 !! check trap active
133	be %xcc, test_fail
134	nop
135
136
137	acc_reset_fee_in_rst1:
138	!Write then read data of RESET_FEE of RST block
139	setx 0x0000008900000820,%g7,%g1
140	setx reset_fee,%g7,%g2
141	ldx [%g2],%g4
142	stx %g4,[%g1]
143	ldx [%g1], %g5
144	cmp %g4, %g5
145	bne %xcc, test_fail
146	nop
147
148	acc_serdes_test_cfg_in_mcu0:
149	!Write then read data of SERDES Test Configuration Bus Register of MCU0 block
150	setx 0x00000084000008e0,%g7,%g1
151	setx mcu_cfg_data,%g7,%g2
152	ldx [%g2],%g4
153	stx %g4,[%g1]
154	ldx [%g1], %g5
155	cmp %g4, %g5
156	bne %xcc, test_fail
157	nop
158	acc_serdes_test_cfg_in_mcu0_nack:
159	!Write then read data of SERDES Test Configuration Bus Register of MCU0 block
160	setx 0x00000084f00008e0,%g7,%g1
161	setx 0,%g7,%o1
162	ldx [%g1], %g5
163	cmp %g0, %o1 ! check trap active
164	be %xcc, test_fail
165	nop
166
167	acc_serdes_test_cfg_in_mcu0_1:
168	!Write then read data of SERDES Test Configuration Bus Register of MCU0 block
169	setx 0x00000084000008e0,%g7,%g1
170	setx mcu_cfg_data,%g7,%g2
171	ldx [%g2],%g4
172	stx %g4,[%g1]
173	ldx [%g1], %g5
174	cmp %g4, %g5
175	bne %xcc, test_fail
176	nop
177
178	acc_serdes_test_cfg_in_mcu1:
179	!Write then read data of SERDES Test Configuration Bus Register of MCU1 block
180	setx 0x00000084000018e0,%g7,%g1
181	setx mcu_cfg_data,%g7,%g2
182	ldx [%g2],%g4
183	stx %g4,[%g1]
184	ldx [%g1], %g5
185	cmp %g4, %g5
186	bne %xcc, test_fail
187	nop
188
189	acc_serdes_test_cfg_in_mcu1_nack:
190	!Write then read data of SERDES Test Configuration Bus Register of MCU1 block
191	setx 0x00000084f00018e0,%g7,%g1
192	setx 0,%g7,%o1
193	ldx [%g1], %g5
194	cmp %g0, %o1 ! check trap active
195	be %xcc, test_fail
196	nop
197
198	acc_serdes_test_cfg_in_mcu1_1:
199	!Write then read data of SERDES Test Configuration Bus Register of MCU1 block
200	setx 0x00000084000018e0,%g7,%g1
201	setx mcu_cfg_data,%g7,%g2
202	ldx [%g2],%g4
203	stx %g4,[%g1]
204	ldx [%g1], %g5
205	cmp %g4, %g5
206	bne %xcc, test_fail
207	nop
208
209	acc_serdes_test_cfg_in_mcu2:
210	!Write then read data of SERDES Test Configuration Bus Register of MCU2 block
211	setx 0x00000084000028e0,%g7,%g1
212	setx mcu_cfg_data,%g7,%g2
213	ldx [%g2],%g4
214	stx %g4,[%g1]
215	ldx [%g1], %g5
216	cmp %g4, %g5
217	bne %xcc, test_fail
218	nop
219	acc_serdes_test_cfg_in_mcu2_nack:
220	!Write then read data of SERDES Test Configuration Bus Register of MCU2 block
221	setx 0x00000084f00028e0,%g7,%g1
222	setx 0,%g7,%o1
223	ldx [%g1], %g5
224	cmp %g0, %o1 ! check trap active
225	be %xcc, test_fail
226	nop
227
228	acc_serdes_test_cfg_in_mcu2_1:
229	!Write then read data of SERDES Test Configuration Bus Register of MCU2 block
230	setx 0x00000084000028e0,%g7,%g1
231	setx mcu_cfg_data,%g7,%g2
232	ldx [%g2],%g4
233	stx %g4,[%g1]
234	ldx [%g1], %g5
235	cmp %g4, %g5
236	bne %xcc, test_fail
237	nop
238
239	acc_serdes_test_cfg_in_mcu3:
240	!Write then read data of SERDES Test Configuration Bus Register of MCU3 block
241	setx 0x00000084000038e0,%g7,%g1
242	setx mcu_cfg_data,%g7,%g2
243	ldx [%g2],%g4
244	stx %g4,[%g1]
245	ldx [%g1], %g5
246	cmp %g4, %g5
247	bne %xcc, test_fail
248	nop
249	acc_serdes_test_cfg_in_mcu3_nack:
250	!Write then read data of SERDES Test Configuration Bus Register of MCU3 block
251	setx 0x00000084f00038e0,%g7,%g1
252	setx 0,%g7,%o1
253	ldx [%g1], %g5
254	cmp %g0, %o1 ! check trap active
255	be %xcc, test_fail
256	nop
257
258	acc_serdes_test_cfg_in_mcu3_1:
259	!Write then read data of SERDES Test Configuration Bus Register of MCU3 block
260	setx 0x00000084000038e0,%g7,%g1
261	setx mcu_cfg_data,%g7,%g2
262	ldx [%g2],%g4
263	stx %g4,[%g1]
264	ldx [%g1], %g5
265	cmp %g4, %g5
266	bne %xcc, test_fail
267	nop
268
269	acc_pll_ctl_in_ccu:
270	!Write then read data of PLL_CTL Register of CCU block
271	setx 0x0000008300000000,%g7,%g1
272	setx pll_ctl_data,%g7,%g2
273	ldx [%g2],%g4
274	stx %g4,[%g1]
275	ldx [%g1], %g5
276	cmp %g4, %g5
277	bne %xcc, test_fail
278	nop
279	acc_pll_ctl_in_ccu_nack:
280	!Write then read data of PLL_CTL Register of CCU block
281	setx 0x00000083f0000000,%g7,%g1
282	setx 0,%g7,%o1
283	ldx [%g1], %g5
284	cmp %g0, %o1 ! check trap active
285	be %xcc, test_fail
286	nop
287	acc_pll_ctl_in_ccu1:
288	!Write then read data of PLL_CTL Register of CCU block
289	setx 0x0000008300000000,%g7,%g1
290	setx pll_ctl_data,%g7,%g2
291	ldx [%g2],%g4
292	stx %g4,[%g1]
293	ldx [%g1], %g5
294	cmp %g4, %g5
295	bne %xcc, test_fail
296	nop
297
298	acc_config_in_niu:
299	!Write then read data of PLL_CTL Register of NIU block
300	setx config,%g7,%g1
301	setx config_data,%g7,%g2
302	ldx [%g2],%g4
303	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
304	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
305	cmp %g4, %g5
306	bne %xcc, test_fail
307	nop
308	acc_config_in_niu_nack:
309	!Write then read data of PLL_CTL Register of NIU block
310	setx 0x00000081f0000000,%g7,%g1
311	setx 0,%g7,%o1
312	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
313	cmp %g0, %o1 ! check trap active
314	be %xcc, test_fail
315	nop
316
317	acc_config_in_niu1:
318	!Write then read data of PLL_CTL Register of NIU block
319	setx config,%g7,%g1
320	setx config_data,%g7,%g2
321	ldx [%g2],%g4
322	stxa %g4,[%g1]ASI_PRIMARY_LITTLE
323	ldxa [%g1]ASI_PRIMARY_LITTLE, %g5
324	cmp %g4, %g5
325	bne %xcc, test_fail
326	nop
327
328	acc_int_en_in_dmu:
329	!Write then read data of INT_EN Register of DMUCSR block
330	setx 0x8800631008, %g7,%g1
331	setx int_en_data,%g7,%g2
332	ldx [%g2],%g4
333	stx %g4,[%g1]
334	ldx [%g1], %g5
335	cmp %g4, %g5
336	bne %xcc, test_fail
337	nop
338
339	/*
340	acc_int_en_in_dmu_nack:
341	!Write then read data of INT_EN Register of DMUCSR block
342	setx 0x88f0631008, %g7,%g1
343	setx 0,%g7,%o1
344	ldx [%g1], %g5
345	cmp %g0, %o1 ! check trap active
346	be %xcc, test_fail
347	nop
348	*/
349
350
351	acc_int_en_in_dmu1:
352	!Write then read data of INT_EN Register of DMUCSR block
353	setx 0x8800631008, %g7,%g1
354	setx int_en_data,%g7,%g2
355	ldx [%g2],%g4
356	stx %g4,[%g1]
357	ldx [%g1], %g5
358	cmp %g4, %g5
359	bne %xcc, test_fail
360	nop
361
362	acc_debug_port_cfg_in_dbug1:
363	!Write then read data of DEBUG_PORT_CONFIG of DBG1 block
364	setx 0x8600000000, %g7,%g1
365	setx dbg1_cfg,%g7,%g2
366	ldx [%g2],%g4
367	stx %g4,[%g1]
368	ldx [%g1], %g5
369	cmp %g4, %g5
370	bne %xcc, test_fail
371	nop
372
373	acc_debug_port_cfg_in_dbug1_nack:
374	!Write then read data of DEBUG_PORT_CONFIG of DBG1 block
375	setx 0x86f0000000, %g7,%g1
376	setx 0,%g7,%o1
377	ldx [%g1], %g5
378	cmp %g0, %o1 ! check trap active
379	be %xcc, test_fail
380	nop
381
382
383	acc_debug_port_cfg_in_dbug1_1:
384	!Write then read data of DEBUG_PORT_CONFIG of DBG1 block
385	setx 0x8600000000, %g7,%g1
386	setx dbg1_cfg,%g7,%g2
387	ldx [%g2],%g4
388	stx %g4,[%g1]
389	ldx [%g1], %g5
390	cmp %g4, %g5
391	bne %xcc, test_fail
392	ba test_pass
393	nop
394
395
396	My_Precise_data_access_error_trap:
397	! Signal trap taken
398	setx EXECUTED, %l0, %o1
399	! save trap type value
400	rdpr %tt, %o1
401	done
402	nop
403
404
405
406
407
408	******************************************************
409	* Exit code
410	*******************************************************/
411
412	test_pass:
413	EXIT_GOOD
414
415	test_fail:
416	EXIT_BAD
417
418
419	.data
420	.align 0x100
421	int_vec_data:
422	.xword 0x000000000000002a
423	.xword 0x000000000000003f
424	.xword 0x0000000000000015
425	.xword 0x0000000000000001
426	.xword 0x0000000000000002
427	.xword 0x0000000000000004
428	.xword 0x0000000000000008
429	.xword 0x0000000000000010
430	.xword 0x0000000000000020
431
432
433	.align 0x100
434	reset_fee:
435	.xword 0x000000000000ff00
436	.xword 0x000000000000aa00
437	.xword 0x0000000000005500
438	.xword 0x0000000000000000
439	.xword 0x0000000000008800
440	.xword 0x0000000000002200
441
442	.align 0x100
443	mcu_cfg_data:
444	.xword 0x000000000000ff00
445	.xword 0x000000000000aa00
446	.xword 0x0000000000005500
447	.xword 0x0000000000000000
448	.xword 0x0000000000000000
449	.xword 0x0000000000000000
450
451	.align 0x100
452	ssi_timeout:
453	.xword 0x0000000000ffffff
454	.xword 0x0000000000aaaaaa
455	.xword 0x0000000000555555
456	.xword 0x000000000056789a
457	.xword 0x0000000000df0123
458	.xword 0x0000000000789abc
459
460	.align 0x100
461	pll_ctl_data:
462	.xword 0x0000001fffffffff
463	.xword 0x0000001aaaaaaaaa
464	.xword 0x0000000555555555
465	.xword 0x000000123456789a
466	.xword 0x0000000bcedf0123
467	.xword 0x0000001456789abc
468
469	.align 0x100
470	int_en_data:
471	.xword 0x0000000000000fff
472	.xword 0x0000000000000aaa
473	.xword 0x0000000000000555
474	.xword 0x000000000000089a
475	.xword 0x0000000000000123
476	.xword 0x0000000000000abc
477
478	.align 0x100
479	config_data:
480	.xword 0x0000000000ffffff
481	.xword 0x0000000000aaaaaa
482	.xword 0x0000000000555555
483	.xword 0x000000000056789a
484	.xword 0x0000000000df0123
485	.xword 0x0000000000789abc
486
487
488	.align 0x100
489	wdata:
490	.xword 0xffffffffffffffff
491	.xword 0xaaaaaaaaaaaaaaaa
492	.xword 0x0000000000000000
493	.xword 0x5555555555555555
494	.xword 0x0123456789abcdef
495
496	.align 0x100
497	dbg1_cfg:
498	.xword 0x00000000000000ff
499	.xword 0x00000000000000aa
500	.xword 0x0000000000000000
501	.xword 0x0000000000000055
502
503	.align 0x100
504	debug_cnt_en:
505	.xword 0x000000000000000f
506	.xword 0x0000000000000000
507	.xword 0x000000000000000a
508	.xword 0x0000000000000005
509	.xword 0x0000000000000002
510	.xword 0x0000000000000004
511	.align 0x100
512	bit_1_data:
513	.xword 0x0000000000000001
514	.xword 0x0000000000000000
515	.xword 0x0000000000000001
516	.xword 0x0000000000000000
517
518	busy_data:
519	.xword 0x0000000000000040
520	.xword 0x0000000000000000
521	.xword 0x0000000000000040
522	.xword 0x0000000000000000
523
524	.align 0x100
525	data_xword:
526	.xword 0x000000faaa000000
527	.xword 0x000000fcad000000
528	.xword 0x000000f555000000
529	.xword 0x000000fabc000000
530
531	.end
532
533
534