[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_DMU_CORE_BLK_enable1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: interrupt_DMU_CORE_BLK_enable1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop; 

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"

	
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

/*      Initialize the NCU for the interrupt.   */

        ! Disable interrupts

no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

	! Initialize NCU's Mondo Interrupt Vector Register
	! VECTOR = 63

ncu_mondo_int_vec:
	set	63, %g1
	setx	MONDO_INT_VEC, %g2, %g3
	stx	%g1, [%g3]

	! Clear NCU's Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
	setx	MONDO_INT_ABUSY, %g1, %g2
	stx	%g0, [%g2]

	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.

mmu_intr_enable_reg_init:
	setx	PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
	set	PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
	set	1, %g4
	sllx	%g4, %g3, %g4
	stx	%g4, [%g2]

	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.

imu_intr_enable_reg_init:
	setx	PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
	set	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
	set	1, %g4
	sllx	%g4, %g3, %g4
	stx	%g4, [%g2]

        ! Initialize Interrupt Mapping register
	! Valid, thread ID 0, no interrupt controller

pci_intr_map_reg_init:
        setx    PCI_E_INT_MAP_ADDR, %g1, %g7
        setx    PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
        add     %g7, %g3, %g7
        setx    0x80000040, %g1, %g6            ! valid = 1, intr. cntrl. = 1
	ldxa    [%g0]ASI_INTR_ID, %o2		! Full thread ID
	sllx	%o2, 25, %o2
	or	%g6, %o2, %g6			! or in thread ID
        stx     %g6, [%g7]

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate

	! Enable IMU, MMU interrupts in the DMU Core and Block
	! Interrupt Enable register.

dmu_core_block_enable:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
	setx	PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
	or	%g3, %g4, %g4
	setx	PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
	membar	#Sync

	! Generate an interrupt from the IMU block.

gen_imu_intr:
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait for the interrupt trap

intr_wait1:
	setx	0x400, %g1, %g2			! timeout count
	setx	user_data_start, %g1, %g7

intr_wait_loop1:
	ld	[%g7], %g5
	cmp	%g5, 1
	be	intr_wait_exit1
	nop

	cmp	%g2, 0
	be	test_failed		! time out
	nop
	ba	intr_wait_loop1
	dec	%g2

	! Reset the interrupt trap occured flag.

intr_wait_exit1:
	st	%g0, [%g7]
	membar	#Sync

	! Generate an interrupt from the MMU block.

gen_mmu_intr_2:
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait for the interrupt trap

intr_wait2:
	setx	0x400, %g1, %g2			! timeout count
	setx	user_data_start, %g1, %g7

intr_wait_loop2:
	ld	[%g7], %g5
	cmp	%g5, 1
	be	intr_wait_exit2
	nop

	cmp	%g2, 0
	be	test_failed		! time out
	nop
	ba	intr_wait_loop2
	dec	%g2

	! Reset the interrupt trap occured flag.

intr_wait_exit2:
	st	%g0, [%g7]
	membar	#Sync

	! Disable IMU interrupts in the DMU Core
	! and Block Interrupt Enable registers

disable_imu_intr:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
	setx	PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
	membar	#Sync

	! Generate an interrupt from the IMU block.

gen_imu_intr_again:
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait to make sure no interrupt occurs

intr_wait3:
	setx	0x40, %g1, %g2			! wait count
	setx	user_data_start, %g1, %g7

intr_wait_loop3:
	ld	[%g7], %g5
	cmp	%g5, 1
	be	test_failed			! interrupt occured
	nop

	cmp	%g2, 0
	bne	intr_wait_loop3
	dec	%g2

	! Clear the error from the IMU block.

clear_imu_error:
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
	stx	%g0, [%g2]			! removes setting of the error
	membar	#Sync
	setx	PCI_E_IMU_ERR_STAT_CLR_ADDR, %g1, %g2
	sub	%g0, 1, %g1			! a W1C register
	stx	%g1, [%g2]			! clears the error flag
	membar	#Sync

	! Reset the interrupt trap occured flag.

intr_wait_exit3:
	st	%g0, [%g7]
	membar	#Sync

	! Disable MMU interrupts in the DMU Core
	! and Block Interrupt Enable registers

disable_mmu_intr:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
	setx	PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g4
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
	membar	#Sync

	! Generate an interrupt from the MMU block.

gen_mmu_intr_again:
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait to make sure no interrupt occurs

intr_wait4:
	setx	0x40, %g1, %g2			! wait count
	setx	user_data_start, %g1, %g7

intr_wait_loop4:
	ld	[%g7], %g5
	cmp	%g5, 1
	be	test_failed			! interrupt occured
	nop

	cmp	%g2, 0
	bne	intr_wait_loop4
	dec	%g2

	! Clear the MMU error

clear_mmu_err:	
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
	stx	%g0, [%g2]			! removes setting of the error
	membar	#Sync
	setx	PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
	sub	%g0, 1, %g1			! a W1C register
	stx	%g1, [%g2]			! clears the error flag
	membar	#Sync

	! Reset the interrupt trap occured flag.

intr_wait_exit4:
	st	%g0, [%g7]
	membar	#Sync

	! Disable DMC interrupts in the DMU Core
	! and Block Interrupt Enable registers

disable_dmc_intr:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g3
	setx	PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g4
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
	membar	#Sync

	! Generate an interrupt from the MMU

gen_mmu_intr_yet_again:
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Generate an interrupt from the IMU

gen_imu_intr_yet_again:
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait to make sure no more interrupts occurs

intr_wait5:
	setx	0x40, %g1, %g2			! wait count
	setx	user_data_start, %g1, %g7

intr_wait_loop5:
	ld	[%g7], %g5
	cmp	%g5, 1
	be	test_failed			! interrupt occured
	nop

	cmp	%g2, 0
	bne	intr_wait_loop5
	dec	%g2

	! Done

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global my_trap_code

my_trap_code:

	! Record interrupt occured.

trap_intr_flag:
        setx    user_data_start, %l1, %l3
	set	1, %l1
	st	%l1, [%l3]

	! Check Mondo Interrupt Busy reg.

trap_mondo_busy:
        ta      T_RD_THID			! thread id into %o1
	setx	MONDO_INT_BUSY, %l1, %l2
	setx	MONDO_INT_BUSY_STEP, %l1, %l3
	mulx	%l3, %o1, %l3
	add	%l3, %l2, %l2
	ldx	[%l2], %l4
	and	%l4, 0x40, %l5			! Is busy bit set?
	cmp	%l5, 0
	be	test_failed
	nop

	! Clear the mondo interrupt in the PIU.

	! MMU Error Status Set reg.

trap_clear_mmu_err_set:	
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
	stx	%g0, [%l2]			! removes setting of the error

	! MMU Error Status Clear reg.

trap_mmu_err_clear:
	setx	PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
	sub	%g0, 1, %l0			! a W1C register
	stx	%l0, [%l2]			! clears the error flag

	! IMU Error Status Set reg.

trap_clear_imu_err_set:	
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %l1, %l2
	stx	%g0, [%l2]			! removes setting of the error

	! IMU Error Status Clear reg.

trap_imu_err_clear:
	setx	PCI_E_IMU_ERR_STAT_CLR_ADDR, %l1, %l2
	sub	%g0, 1, %l0			! a W1C register
	stx	%l0, [%l2]			! clears the error flag

	! Interrupt Clear reg.

trap_intr_clear:
	setx	PCI_E_INT_CLEAR_ADDR, %l1, %l2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
	add	%l2, %l3, %l2
	stx	%g0, [%l2]

	! Clear the mondo interrupt in the NCU

trap_mondo_intr_clear:
	setx	MONDO_INT_ABUSY, %l0, %l1
	stx	%g0, [%l1]
	membar	#Sync

	ldx	[%l1], %l2
	and	%l2, 0x40, %l2
	cmp	%l2, 0			! Busy should be cleared
	bne	test_failed
	nop

	! Clear the interrupt in the core.

trap_clear_asi_intr_r:
	ldxa	[%g0]ASI_SWVR_INTR_R, %l5
	cmp	%l5, 63			! check for correct vector number
	bne	test_failed
	nop

	! Done.

trap_done:
	jmpl    %o7+0x8, %g0
	nop


/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
        .word   0x0
        .word   0x0
        .word   0x0
        .word   0x0
user_data_end:
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: interrupt_DMU_CORE_BLK_enable1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#define H_HT0_Interrupt_0x60
	41	#define My_HT0_Interrupt_0x60 \
	42	call my_trap_code; \
	43	nop; \
	44	retry; \
	45	nop;
	46
	47	#include "hboot.s"
	48	#include "peu_defines.h"
	49	#include "ncu_defines.h"
	50
	51
	52	/************************************************************************
	53	Test case code start
	54	************************************************************************/
	55	.text
	56	.global main
	57
	58	main:
	59	ta T_CHANGE_HPRIV
	60	nop
	61
	62	/* Initialize the NCU for the interrupt. */
	63
	64	! Disable interrupts
65
66	no_intr:
67	rdpr %pstate, %g7
68	xor %g7, 0x2, %g7 ! Reset interrupt enable
69	wrpr %g7, %pstate
70
71	! Initialize NCU's Mondo Interrupt Vector Register
72	! VECTOR = 63
73
74	ncu_mondo_int_vec:
75	set 63, %g1
76	setx MONDO_INT_VEC, %g2, %g3
77	stx %g1, [%g3]
78
79	! Clear NCU's Mondo Interrupt Busy registers.
80
81	ncu_mondo_int_busy:
82	setx MONDO_INT_ABUSY, %g1, %g2
83	stx %g0, [%g2]
84
85	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.
86
87	mmu_intr_enable_reg_init:
88	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
89	set PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
90	set 1, %g4
91	sllx %g4, %g3, %g4
92	stx %g4, [%g2]
93
94	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.
95
96	imu_intr_enable_reg_init:
97	setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
98	set PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
99	set 1, %g4
100	sllx %g4, %g3, %g4
101	stx %g4, [%g2]
102
103	! Initialize Interrupt Mapping register
104	! Valid, thread ID 0, no interrupt controller
105
106	pci_intr_map_reg_init:
107	setx PCI_E_INT_MAP_ADDR, %g1, %g7
108	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
109	add %g7, %g3, %g7
110	setx 0x80000040, %g1, %g6 ! valid = 1, intr. cntrl. = 1
111	ldxa [%g0]ASI_INTR_ID, %o2 ! Full thread ID
112	sllx %o2, 25, %o2
113	or %g6, %o2, %g6 ! or in thread ID
114	stx %g6, [%g7]
115
116	yes_intr:
117	rdpr %pstate, %g7
118	or %g7, 0x2, %g7 ! Set interrupt enable
119	wrpr %g7, %pstate
120
121	! Enable IMU, MMU interrupts in the DMU Core and Block
122	! Interrupt Enable register.
123
124	dmu_core_block_enable:
125	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
126	setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
127	setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
128	or %g3, %g4, %g4
129	setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
130	or %g3, %g4, %g4
131	stx %g4, [%g2]
132	membar #Sync
133
134	! Generate an interrupt from the IMU block.
135
136	gen_imu_intr:
137	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
138	set 1, %g6
139	setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
140	sllx %g6, %g3, %g6
141	stx %g6, [%g2]
142	membar #Sync
143
144	! Wait for the interrupt trap
145
146	intr_wait1:
147	setx 0x400, %g1, %g2 ! timeout count
148	setx user_data_start, %g1, %g7
149
150	intr_wait_loop1:
151	ld [%g7], %g5
152	cmp %g5, 1
153	be intr_wait_exit1
154	nop
155
156	cmp %g2, 0
157	be test_failed ! time out
158	nop
159	ba intr_wait_loop1
160	dec %g2
161
162	! Reset the interrupt trap occured flag.
163
164	intr_wait_exit1:
165	st %g0, [%g7]
166	membar #Sync
167
168	! Generate an interrupt from the MMU block.
169
170	gen_mmu_intr_2:
171	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
172	set 1, %g6
173	setx PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g1, %g3
174	sllx %g6, %g3, %g6
175	stx %g6, [%g2]
176	membar #Sync
177
178	! Wait for the interrupt trap
179
180	intr_wait2:
181	setx 0x400, %g1, %g2 ! timeout count
182	setx user_data_start, %g1, %g7
183
184	intr_wait_loop2:
185	ld [%g7], %g5
186	cmp %g5, 1
187	be intr_wait_exit2
188	nop
189
190	cmp %g2, 0
191	be test_failed ! time out
192	nop
193	ba intr_wait_loop2
194	dec %g2
195
196	! Reset the interrupt trap occured flag.
197
198	intr_wait_exit2:
199	st %g0, [%g7]
200	membar #Sync
201
202	! Disable IMU interrupts in the DMU Core
203	! and Block Interrupt Enable registers
204
205	disable_imu_intr:
206	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
207	setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
208	setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
209	or %g3, %g4, %g4
210	stx %g4, [%g2]
211	membar #Sync
212
213	! Generate an interrupt from the IMU block.
214
215	gen_imu_intr_again:
216	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
217	set 1, %g6
218	setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
219	sllx %g6, %g3, %g6
220	stx %g6, [%g2]
221	membar #Sync
222
223	! Wait to make sure no interrupt occurs
224
225	intr_wait3:
226	setx 0x40, %g1, %g2 ! wait count
227	setx user_data_start, %g1, %g7
228
229	intr_wait_loop3:
230	ld [%g7], %g5
231	cmp %g5, 1
232	be test_failed ! interrupt occured
233	nop
234
235	cmp %g2, 0
236	bne intr_wait_loop3
237	dec %g2
238
239	! Clear the error from the IMU block.
240
241	clear_imu_error:
242	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
243	stx %g0, [%g2] ! removes setting of the error
244	membar #Sync
245	setx PCI_E_IMU_ERR_STAT_CLR_ADDR, %g1, %g2
246	sub %g0, 1, %g1 ! a W1C register
247	stx %g1, [%g2] ! clears the error flag
248	membar #Sync
249
250	! Reset the interrupt trap occured flag.
251
252	intr_wait_exit3:
253	st %g0, [%g7]
254	membar #Sync
255
256	! Disable MMU interrupts in the DMU Core
257	! and Block Interrupt Enable registers
258
259	disable_mmu_intr:
260	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
261	setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
262	setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g4
263	or %g3, %g4, %g4
264	stx %g4, [%g2]
265	membar #Sync
266
267	! Generate an interrupt from the MMU block.
268
269	gen_mmu_intr_again:
270	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
271	set 1, %g6
272	setx PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g1, %g3
273	sllx %g6, %g3, %g6
274	stx %g6, [%g2]
275	membar #Sync
276
277	! Wait to make sure no interrupt occurs
278
279	intr_wait4:
280	setx 0x40, %g1, %g2 ! wait count
281	setx user_data_start, %g1, %g7
282
283	intr_wait_loop4:
284	ld [%g7], %g5
285	cmp %g5, 1
286	be test_failed ! interrupt occured
287	nop
288
289	cmp %g2, 0
290	bne intr_wait_loop4
291	dec %g2
292
293	! Clear the MMU error
294
295	clear_mmu_err:
296	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
297	stx %g0, [%g2] ! removes setting of the error
298	membar #Sync
299	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
300	sub %g0, 1, %g1 ! a W1C register
301	stx %g1, [%g2] ! clears the error flag
302	membar #Sync
303
304	! Reset the interrupt trap occured flag.
305
306	intr_wait_exit4:
307	st %g0, [%g7]
308	membar #Sync
309
310	! Disable DMC interrupts in the DMU Core
311	! and Block Interrupt Enable registers
312
313	disable_dmc_intr:
314	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
315	setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g3
316	setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g4
317	or %g3, %g4, %g4
318	stx %g4, [%g2]
319	membar #Sync
320
321	! Generate an interrupt from the MMU
322
323	gen_mmu_intr_yet_again:
324	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
325	set 1, %g6
326	setx PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g1, %g3
327	sllx %g6, %g3, %g6
328	stx %g6, [%g2]
329	membar #Sync
330
331	! Generate an interrupt from the IMU
332
333	gen_imu_intr_yet_again:
334	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
335	set 1, %g6
336	setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
337	sllx %g6, %g3, %g6
338	stx %g6, [%g2]
339	membar #Sync
340
341	! Wait to make sure no more interrupts occurs
342
343	intr_wait5:
344	setx 0x40, %g1, %g2 ! wait count
345	setx user_data_start, %g1, %g7
346
347	intr_wait_loop5:
348	ld [%g7], %g5
349	cmp %g5, 1
350	be test_failed ! interrupt occured
351	nop
352
353	cmp %g2, 0
354	bne intr_wait_loop5
355	dec %g2
356
357	! Done
358
359	test_passed:
360	EXIT_GOOD
361
362	test_failed:
363	EXIT_BAD
364
365
366	/**********************************************************************
367	Interrupt trap handler.
368	**********************************************************************/
369
370	.global my_trap_code
371
372	my_trap_code:
373
374	! Record interrupt occured.
375
376	trap_intr_flag:
377	setx user_data_start, %l1, %l3
378	set 1, %l1
379	st %l1, [%l3]
380
381	! Check Mondo Interrupt Busy reg.
382
383	trap_mondo_busy:
384	ta T_RD_THID ! thread id into %o1
385	setx MONDO_INT_BUSY, %l1, %l2
386	setx MONDO_INT_BUSY_STEP, %l1, %l3
387	mulx %l3, %o1, %l3
388	add %l3, %l2, %l2
389	ldx [%l2], %l4
390	and %l4, 0x40, %l5 ! Is busy bit set?
391	cmp %l5, 0
392	be test_failed
393	nop
394
395	! Clear the mondo interrupt in the PIU.
396
397	! MMU Error Status Set reg.
398
399	trap_clear_mmu_err_set:
400	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
401	stx %g0, [%l2] ! removes setting of the error
402
403	! MMU Error Status Clear reg.
404
405	trap_mmu_err_clear:
406	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
407	sub %g0, 1, %l0 ! a W1C register
408	stx %l0, [%l2] ! clears the error flag
409
410	! IMU Error Status Set reg.
411
412	trap_clear_imu_err_set:
413	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %l1, %l2
414	stx %g0, [%l2] ! removes setting of the error
415
416	! IMU Error Status Clear reg.
417
418	trap_imu_err_clear:
419	setx PCI_E_IMU_ERR_STAT_CLR_ADDR, %l1, %l2
420	sub %g0, 1, %l0 ! a W1C register
421	stx %l0, [%l2] ! clears the error flag
422
423	! Interrupt Clear reg.
424
425	trap_intr_clear:
426	setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
427	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
428	add %l2, %l3, %l2
429	stx %g0, [%l2]
430
431	! Clear the mondo interrupt in the NCU
432
433	trap_mondo_intr_clear:
434	setx MONDO_INT_ABUSY, %l0, %l1
435	stx %g0, [%l1]
436	membar #Sync
437
438	ldx [%l1], %l2
439	and %l2, 0x40, %l2
440	cmp %l2, 0 ! Busy should be cleared
441	bne test_failed
442	nop
443
444	! Clear the interrupt in the core.
445
446	trap_clear_asi_intr_r:
447	ldxa [%g0]ASI_SWVR_INTR_R, %l5
448	cmp %l5, 63 ! check for correct vector number
449	bne test_failed
450	nop
451
452	! Done.
453
454	trap_done:
455	jmpl %o7+0x8, %g0
456	nop
457
458
459
460	/************************************************************************
461	Test case data start
462	************************************************************************/
463
464	.align 1024
465	.data
466	user_data_start:
467	.word 0x0
468	.word 0x0
469	.word 0x0
470	.word 0x0
471	user_data_end:
472	.end