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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_INTR_REC_priority.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define H_HT0_Interrupt_0x60 | |
42 | #define My_HT0_Interrupt_0x60 \ | |
43 | call my_trap_code; \ | |
44 | nop; \ | |
45 | retry; \ | |
46 | nop; | |
47 | ||
48 | #include "hboot.s" | |
49 | #include "ncu_defines.h" | |
50 | ||
51 | /************************************************************************ | |
52 | Test case code start | |
53 | ************************************************************************/ | |
54 | ||
55 | .text | |
56 | .global main | |
57 | ||
58 | main: | |
59 | ||
60 | ! Switch to hypervisor mode. | |
61 | ||
62 | ta T_CHANGE_HPRIV | |
63 | nop | |
64 | ||
65 | ! Turn off interrupts. | |
66 | intr_off: | |
67 | rdpr %pstate, %g1 | |
68 | set 0x2, %g2 | |
69 | andn %g1, %g2,%g1 | |
70 | wrpr %g1, %g0, %pstate | |
71 | ||
72 | set INT_VEC_DIS, %g2 | |
73 | wr %g0, %g2, %asi | |
74 | ||
75 | ! Generate a cross thread interrupt to this thread, 0. | |
76 | first_intr: | |
77 | #ifndef PORTABLE_CORE | |
78 | mov 5, %g3 ! send to thread 0 vector number 5 | |
79 | #else | |
80 | ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID | |
81 | sllx %o2, 8, %g3 | |
82 | or %g3, 5, %g3 ! send to this thread vector number 5 | |
83 | #endif | |
84 | stxa %g3, [%g0]%asi | |
85 | membar #Sync | |
86 | ||
87 | ! Wait a bit | |
88 | ||
89 | #ifdef DTM_ENABLED | |
90 | mov 32, %g4 | |
91 | #else | |
92 | mov 8, %g4 | |
93 | #endif | |
94 | ||
95 | wait1: cmp %g4, 0 | |
96 | bne wait1 | |
97 | sub %g4, 1, %g4 | |
98 | ||
99 | ! Generate a 2nd cross thread interrupt to this thread, 0. | |
100 | second_intr: | |
101 | #ifndef PORTABLE_CORE | |
102 | mov 1, %g3 ! send to thread 0 vector number 1 | |
103 | #else | |
104 | ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID | |
105 | sllx %o2, 8, %g3 | |
106 | or %g3, 1, %g3 ! send to this thread vector number 1 | |
107 | #endif | |
108 | stxa %g3, [%g0]%asi | |
109 | membar #Sync | |
110 | ||
111 | ! Wait a bit | |
112 | ||
113 | #ifdef DTM_ENABLED | |
114 | mov 32, %g4 | |
115 | #else | |
116 | mov 8, %g4 | |
117 | #endif | |
118 | ||
119 | wait2: cmp %g4, 0 | |
120 | bne wait2 | |
121 | sub %g4, 1, %g4 | |
122 | ||
123 | ! Generate a 3rd cross thread interrupt to this thread, 0. | |
124 | third_intr: | |
125 | #ifndef PORTABLE_CORE | |
126 | mov 7, %g3 ! send to thread 0 vector number 7 | |
127 | #else | |
128 | ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID | |
129 | sllx %o2, 8, %g3 | |
130 | or %g3, 7, %g3 ! send to this thread vector number 7 | |
131 | #endif | |
132 | stxa %g3, [%g0]%asi | |
133 | membar #Sync | |
134 | ||
135 | ! Wait a bit | |
136 | ||
137 | #ifdef DTM_ENABLED | |
138 | mov 80, %g4 | |
139 | #else | |
140 | mov 20, %g4 | |
141 | #endif | |
142 | ||
143 | ||
144 | wait3: cmp %g4, 0 | |
145 | bne wait3 | |
146 | sub %g4, 1, %g4 | |
147 | ||
148 | ! Make sure no interrupts yet. | |
149 | no_intr_check: | |
150 | setx my_trap_count, %g1, %g2 | |
151 | ld [%g2], %g3 | |
152 | cmp %g3, 0 | |
153 | bne test_failed | |
154 | nop | |
155 | ||
156 | ! Turn on interrupts | |
157 | intr_on: | |
158 | rdpr %pstate, %g1 | |
159 | set 0x2, %g2 | |
160 | or %g1, %g2,%g1 | |
161 | wrpr %g1, %g0, %pstate | |
162 | ||
163 | ! Wait a bit more | |
164 | ||
165 | #ifdef DTM_ENABLED | |
166 | mov 160, %g4 | |
167 | #else | |
168 | mov 40, %g4 | |
169 | #endif | |
170 | ||
171 | ||
172 | wait4: cmp %g4, 0 | |
173 | bne wait4 | |
174 | sub %g4, 1, %g4 | |
175 | ||
176 | ! Did the expected 3 interrupts occur? | |
177 | check_intr_count: | |
178 | setx my_trap_count, %g1, %g2 | |
179 | ld [%g2], %g3 | |
180 | cmp %g3, 3 | |
181 | bne test_failed | |
182 | nop | |
183 | ||
184 | ba test_passed | |
185 | nop | |
186 | ||
187 | /********************************************************************** | |
188 | Interrupt trap handler. | |
189 | **********************************************************************/ | |
190 | ||
191 | .global my_trap_code | |
192 | ||
193 | my_trap_code: | |
194 | ! Increment the count | |
195 | ||
196 | setx my_trap_count, %g6, %g7 | |
197 | ld [%g7], %g5 | |
198 | add %g5, 1, %g5 | |
199 | st %g5, [%g7] | |
200 | membar #Sync | |
201 | ||
202 | ! Check the core interrupt receive. | |
203 | trap0: | |
204 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
205 | cmp %g5, 1 | |
206 | be trap1 | |
207 | nop | |
208 | ||
209 | cmp %g5, 2 | |
210 | be trap2 | |
211 | nop | |
212 | ||
213 | set 0x2, %g3 | |
214 | set 0x1, %g2 | |
215 | mov %g0, %g7 | |
216 | ba trap3 | |
217 | nop | |
218 | trap1: | |
219 | set 0x80, %g3 | |
220 | set 0x7, %g2 | |
221 | set 0x5, %g7 | |
222 | ba trap3 | |
223 | nop | |
224 | trap2: | |
225 | set 0x20, %g3 | |
226 | set 0x5, %g2 | |
227 | set 0x1, %g7 | |
228 | trap3: | |
229 | and %g4, %g3, %g4 | |
230 | cmp %g4, %g3 | |
231 | bne test_failed | |
232 | nop | |
233 | ||
234 | ! Clear the interrupt by a write to Interrupt Receive Reg. | |
235 | trap4: | |
236 | orn %g0, %g3, %g5 ! bit = 0 for interrupt received | |
237 | stxa %g5, [%g0]ASI_SWVR_INTR_RECEIVE | |
238 | membar #Sync | |
239 | ||
240 | ! Check that the interrupt was cleared. | |
241 | trap5: | |
242 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
243 | and %g4, %g3, %g3 | |
244 | cmp %g3, 0 | |
245 | bne test_failed | |
246 | nop | |
247 | ||
248 | jmpl %o7+0x8, %g0 | |
249 | nop | |
250 | ||
251 | ||
252 | test_passed: | |
253 | EXIT_GOOD | |
254 | ||
255 | test_failed: | |
256 | EXIT_BAD | |
257 | ||
258 | ||
259 | /************************************************************************ | |
260 | Test case data start | |
261 | ************************************************************************/ | |
262 | .data | |
263 | user_data_start: | |
264 | my_trap_count: | |
265 | .word 0x0 | |
266 | .word 0x0 | |
267 | .end | |
268 | ||
269 | ||
270 |