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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_INT_MAN_thread_all.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt_INT_MAN_thread_all.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40#ifndef SYNC_THREADS
41#define SYNC_THREADS 0xff
42#endif
43
44#ifndef DIAG_NUM_THREADS
45#define DIAG_NUM_THREADS 8
46#endif
47
48#define H_HT0_Interrupt_0x60
49#define My_HT0_Interrupt_0x60 \
50 call my_trap_code; \
51 nop; \
52 retry; \
53 nop;
54
55#include "hboot.s"
56#include "niu_defines.h"
57#include "ncu_defines.h"
58#include "niu_macros.h"
59#include "cmp_macros.h"
60
61
62
63/************************************************************************
64 Test case code start
65 ************************************************************************/
66.text
67.global main
68
69main:
70 ta T_CHANGE_HPRIV
71 nop
72
73 ! Determine thread running on
74
75 ta T_RD_THID
76 cmp %o1, 0
77 be main_t0 ! Branch if thread 0
78 nop
79
80 ba main_t1_to_t63 ! Branch if not thread 0
81 nop
82
83
84/************************************************************************
85 Thread 0 code
86 ************************************************************************/
87
88main_t0:
89 ta T_CHANGE_HPRIV
90 nop
91
92/* Initialize the NCU for the interrupt. */
93
94 ! Disable interrupts
95
96no_intr:
97 rdpr %pstate, %g7
98 xor %g7, 0x2, %g7 ! Reset interrupt enable
99 wrpr %g7, %pstate
100
101ncu_init:
102 ! Initially set all the Interrupt Management Registers
103 ! Later will set all those not used to have a different vector number
104
105 setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
106 setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
107
108niu_init_loop_top:
109 stx %g0, [%g2]
110 add %g2, INT_MAN_STEP, %g2
111 cmp %g4, 1
112 bne niu_init_loop_top
113 add %g4, -1, %g4
114
115 ! Initialize the NIU for TX DMA interrupt.
116
117 NIU_TX_LD_IM0_INTR_ON_MARK( 0, %g1, %g2, %g3, %g4, 0, 0 )
118
119 ! Enable interrupts
120
121yes_intr:
122 rdpr %pstate, %g7
123 or %g7, 0x2, %g7 ! Set interrupt enable
124 wrpr %g7, %pstate
125
126 ! Wait for other threads to be ready
127
128 SYNC_THREAD_MAIN( local_test_failed, %g1, %g2, %g3 )
129
130 ! All threads are ready
131
132 ! Generate the interrupt via PIO write
133
134gen_intr:
135 setx TDMC_INTR_DBG, %g1, %g2
136 mov %g0, %g7 ! DMA channel 0
137 setx TDMC_STEP, %g1, %g3
138 mulx %g7, %g3, %g7
139 add %g2, %g7, %g2
140
141 setx 0x8000, %g1, %g4
142 stxa %g4, [%g2]ASI_PRIMARY_LITTLE
143
144 ! Wait for an interrupt to occur
145
146wait1:
147 setx 0x800, %g1, %g4
148 setx old_intr_count, %g1, %g3
149 ld [%g3], %g6
150 inc %g6
151 setx user_data_start, %g1, %g5
152
153delay_loop1:
154
155 ld [%g5], %g7
156 cmp %g7, %g6
157 be intr_occured
158 nop
159 dec %g4
160 brnz %g4, delay_loop1
161 nop
162 ba local_test_failed
163 nop
164
165intr_occured:
166 st %g7, [%g3] ! update old_intr_count
167
168 ! Branch back to do next interrupt.
169next_intr:
170 setx user_data_start, %g1, %g3
171 ld [%g3], %g2
172 cmp %g2, DIAG_NUM_THREADS
173 blt gen_intr
174 nop
175 ba test_passed
176 nop
177
178
179/************************************************************************
180 Thread 1 to 63 code
181 ************************************************************************/
182
183 ! Get thread id
184
185main_t1_to_t63:
186 ta T_RD_THID
187
188 ! Sync up with other threads
189
190 SYNC_THREAD_OTHER( %o1, %g1, %g2 )
191
192 ! Wait for interrupt to this thread
193
194wait_t1_to_t63:
195 setx user_data_start, %g1, %g7
196 add %o1, 1, %o1 ! Thread id is incremented on interrupt
197
198t1_to_t63_delay_loop:
199 ld [%g7], %g6
200 cmp %g6, %o1
201 bge test_passed
202 nop
203 ba t1_to_t63_delay_loop
204 nop
205
206 ba local_test_failed
207 nop
208
209
210test_passed:
211 EXIT_GOOD
212
213local_test_failed:
214
215 ! Read related interrupt registers to aid debugging
216
217read_1:
218 ldxa [%g0]ASI_INTR_RECEIVE, %i0
219 ldxa [%g0]ASI_SWVR_INTR_R, %i1
220read_2:
221 setx INT_MAN, %g1, %g2
222 ldx [%g2], %i2
223read_3:
224 set 32, %g3 ! index for logical device number
225 setx LDG_NUM_STEP, %g1, %g4
226 mulx %g4, %g3, %g3
227 setx LDG_NUM, %g1, %g2
228 add %g3, %g2, %g2
229 ldxa [%g2]ASI_PRIMARY_LITTLE, %i3
230 setx LDSV0, %g1, %g2
231 ldxa [%g2]ASI_PRIMARY_LITTLE, %i4
232 setx LDSV1, %g1, %g2
233 ldxa [%g2]ASI_PRIMARY_LITTLE, %i5
234 setx LDSV2, %g1, %g2
235 ldxa [%g2]ASI_PRIMARY_LITTLE, %i6
236 set 32, %g3 ! index for logical device number
237 setx LD_IM0_STEP, %g1, %g4
238 mulx %g4, %g3, %g3
239 setx LD_IM0, %g1, %g2
240 add %g3, %g2, %g2
241 ldxa [%g2]ASI_PRIMARY_LITTLE, %i7
242 setx LDGIMGN, %g1, %g2
243 ldxa [%g2]ASI_PRIMARY_LITTLE, %o1
244 setx LDGITMRES, %g1, %g2
245 ldxa [%g2]ASI_PRIMARY_LITTLE, %o2
246 setx SID, %g1, %g2
247 ldxa [%g2]ASI_PRIMARY_LITTLE, %o3
248read_4:
249 setx TX_ENT_MSK, %g1, %g2
250 ldxa [%g2]ASI_PRIMARY_LITTLE, %o4
251 setx TX_CS, %g1, %g2
252 ldxa [%g2]ASI_PRIMARY_LITTLE, %o5
253 setx TDMC_INTR_DBG, %g1, %g2
254 ldxa [%g2]ASI_PRIMARY_LITTLE, %o6
255
256 EXIT_BAD
257
258
259/**********************************************************************
260 Interrupt trap handler.
261**********************************************************************/
262
263.global my_trap_code
264
265my_trap_code:
266
267 ! Get the thread id.
268 ta T_RD_THID ! %o1 = thread id
269
270 ! Check that interrupt went to correct thread.
271Trap0:
272 setx user_data_start, %l2, %l6
273 ld [%l6], %l5
274 cmp %l5, %o1
275 bne local_test_failed
276 nop
277
278 ! Change the thread id to use in the NCU for next interrupt
279Trap1:
280 add %l5, 1, %l5
281 sllx %l5, 8, %l5 ! put thread id in proper position
282 setx INT_MAN, %l1, %l2 ! %g2 = INT_MAN reg. addr.
283 stx %l5, [%l2]
284 membar #Sync
285
286 ! The following order is important, if reversed a second
287 ! interrupt occurs on same condition.
288
289 ! Re-enable the interrupt in the NIU
290Trap2:
291 setx TX_CS, %g1, %g2 ! TX_CS, Tx DMA channel 0
292 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1 ! Reset MK
293 nop
294
295 ! Re-enable the interrupt in the NIU
296Trap3:
297 setx LDGIMGN, %g1, %g2 ! logical device group 0
298 setx 0x80000001, %g1, %g3
299 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
300 nop
301
302 ! Clear the interrupt in the core.
303Trap4:
304 ldxa [%g0]ASI_SWVR_INTR_R, %l3
305
306 ! Increment the interrupt count.
307Trap5:
308 setx user_data_start, %l2, %l6
309 ld [%l6], %l5
310 add %l5, 1, %l5
311 st %l5, [%l6]
312 membar #Sync
313
314 jmpl %o7+0x8, %g0
315 nop
316
317
318
319
320/************************************************************************
321 Test case data start
322 ************************************************************************/
323
324.align 1024
325.data
326user_data_start:
327 .word 0x0
328 .word 0x0
329 .word 0x0
330 .word 0x0
331old_intr_count:
332 .word 0x0
333 .word 0x0
334 .word 0x0
335 .word 0x0
336
337
338/* These initialization is temporary, as there looks some bug in mempli */
339
340SECTION SetRngConfig_init data_va=0x100000000
341attr_data {
342 Name = SetRngConfig_init,
343 hypervisor,
344 compressimage
345 }
346.data
347SetRngConfig_init:
348 .xword 0x0060452301000484
349/************************************************************************/
350
351SECTION SetTxRingKick_init data_va=0x100000100
352attr_data {
353 Name = SetTxRingKick_init,
354 hypervisor,
355 compressimage
356 }
357.data
358SetTxRingKick_init:
359 .xword 0x0060452301000484
360/************************************************************************/
361
362SECTION SetTxLPMask1_init data_va=0x100000200
363attr_data {
364 Name = SetTxLPMask1_init,
365 hypervisor,
366 compressimage
367 }
368.data
369SetTxLPMask1_init:
370 .xword 0x0060452301000484
371/************************************************************************/
372
373SECTION SetTxLPValue1_init data_va=0x100000300
374attr_data {
375 Name = SetTxLPValue1_init,
376 hypervisor,
377 compressimage
378 }
379.data
380SetTxLPValue1_init:
381 .xword 0x0060452301000484
382/************************************************************************/
383
384SECTION SetTxLPRELOC1_init data_va=0x100000400
385attr_data {
386 Name = SetTxLPRELOC1_init,
387 hypervisor,
388 compressimage
389 }
390.data
391SetTxLPRELOC1_init:
392 .xword 0x0060452301000484
393/************************************************************************/
394SECTION SetTxLPMask2_init data_va=0x100000500
395attr_data {
396 Name = SetTxLPMask2_init,
397 hypervisor,
398 compressimage
399 }
400.data
401SetTxLPMask2_init:
402 .xword 0x0060452301000484
403/************************************************************************/
404SECTION SetTxLPValue2_init data_va=0x100000600
405attr_data {
406 Name = SetTxLPValue2_init,
407 hypervisor,
408 compressimage
409 }
410.data
411SetTxLPValue2_init:
412 .xword 0x0060452301000484
413
414/************************************************************************/
415SECTION SetTxLPRELOC2_init data_va=0x100000700
416attr_data {
417 Name = SetTxLPRELOC2_init,
418 hypervisor,
419 compressimage
420 }
421.data
422SetTxLPRELOC2_init:
423 .xword 0x0060452301000484
424
425/************************************************************************/
426SECTION SetTxLPValid_init data_va=0x100000800
427attr_data {
428 Name = SetTxLPValid_init,
429 hypervisor,
430 compressimage
431 }
432.data
433SetTxLPValid_init:
434 .xword 0x0060452301000484
435
436/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.