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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_INT_VEC_DIS.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define H_HT0_Interrupt_0x60 | |
42 | #define My_HT0_Interrupt_0x60 \ | |
43 | call my_trap_code; \ | |
44 | nop; \ | |
45 | retry; \ | |
46 | nop; | |
47 | ||
48 | #include "hboot.s" | |
49 | #include "ncu_defines.h" | |
50 | ||
51 | ||
52 | /************************************************************************ | |
53 | Test case code start | |
54 | ************************************************************************/ | |
55 | ||
56 | .text | |
57 | .global main | |
58 | ||
59 | main: | |
60 | ||
61 | ! Switch to hypervisor mode. | |
62 | ||
63 | ta T_CHANGE_HPRIV | |
64 | nop | |
65 | ||
66 | ! Generate a cross thread interrupt to this thread, 0. | |
67 | ||
68 | wr %g0, INT_VEC_DIS, %asi | |
69 | mov 5, %g3 ! send to thread 0 vector number 5 | |
70 | stxa %g3, [%g0]%asi | |
71 | membar #Sync | |
72 | ||
73 | ! Wait a bit | |
74 | ||
75 | mov 20, %g4 | |
76 | ||
77 | wait: cmp %g4, 0 | |
78 | bne wait | |
79 | sub %g4, 1, %g4 | |
80 | ||
81 | ! Did the expected interrupt occur? Expect 1 interrupt trap. | |
82 | ||
83 | setx my_trap_count, %g1, %g2 | |
84 | ld [%g2], %g3 | |
85 | cmp %g3, 1 | |
86 | bne test_failed | |
87 | nop | |
88 | ||
89 | ba test_passed | |
90 | nop | |
91 | ||
92 | /********************************************************************** | |
93 | Interrupt trap handler. | |
94 | **********************************************************************/ | |
95 | ||
96 | .global my_trap_code | |
97 | ||
98 | my_trap_code: | |
99 | ! Increment the count | |
100 | ||
101 | setx my_trap_count, %g6, %g7 | |
102 | ld [%g7], %g5 | |
103 | add %g5, 1, %g5 | |
104 | st %g5, [%g7] | |
105 | membar #Sync | |
106 | ||
107 | ! Check the core interrupt receive and incoming vector registers. | |
108 | ||
109 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
110 | cmp %g4, 0x20 ! should be vector number 5 | |
111 | bne test_failed | |
112 | nop | |
113 | ||
114 | ! Clear the interrupt | |
115 | ||
116 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 | |
117 | cmp %g3, 0x5 ! should be vector number 5 | |
118 | bne test_failed | |
119 | nop | |
120 | ||
121 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
122 | cmp %g4, 0 ! now should be 0 | |
123 | bne test_failed | |
124 | nop | |
125 | ||
126 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 | |
127 | cmp %g3, 0x0 ! should also now be 0 | |
128 | bne test_failed | |
129 | nop | |
130 | ||
131 | jmpl %o7+0x8, %g0 | |
132 | nop | |
133 | ||
134 | ||
135 | test_passed: | |
136 | EXIT_GOOD | |
137 | ||
138 | test_failed: | |
139 | EXIT_BAD | |
140 | ||
141 | ||
142 | /************************************************************************ | |
143 | Test case data start | |
144 | ************************************************************************/ | |
145 | .data | |
146 | user_data_start: | |
147 | my_trap_count: | |
148 | .word 0x0 | |
149 | .word 0x0 | |
150 | .end | |
151 | ||
152 | ||
153 |