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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_MAC.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | #define H_HT0_Interrupt_0x60 | |
41 | #define My_HT0_Interrupt_0x60 \ | |
42 | call my_trap_code; \ | |
43 | nop; \ | |
44 | retry; \ | |
45 | nop; | |
46 | ||
47 | ||
48 | #include "hboot.s" | |
49 | #include "niu_defines.h" | |
50 | #include "ncu_defines.h" | |
51 | ||
52 | ||
53 | /************************************************************************ | |
54 | Test case code start | |
55 | ************************************************************************/ | |
56 | .text | |
57 | .global main | |
58 | ||
59 | main: | |
60 | ta T_CHANGE_HPRIV | |
61 | nop | |
62 | ta T_CHANGE_PRIV | |
63 | nop | |
64 | ||
65 | thread_0: | |
66 | ||
67 | /* Initialize the NCU for the interrupt. */ | |
68 | ||
69 | ! Disable interrupts | |
70 | ||
71 | no_intr: | |
72 | rdpr %pstate, %g7 | |
73 | xor %g7, 0x2, %g7 ! Reset interrupt enable | |
74 | wrpr %g7, %pstate | |
75 | ||
76 | ncu_init: | |
77 | ! Initially set all the Interrupt Management Registers | |
78 | ! Later will set all those not used to have a different vector number | |
79 | ||
80 | setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr. | |
81 | setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value | |
82 | set 1, %g5 ! %g5 = value to write to INT_MAN reg. | |
83 | ||
84 | niu_init_loop_top: | |
85 | stx %g5, [%g2] | |
86 | add %g2, INT_MAN_STEP, %g2 | |
87 | cmp %g4, 1 | |
88 | bne niu_init_loop_top | |
89 | add %g4, -1, %g4 | |
90 | ||
91 | ! Enable interrupts | |
92 | ||
93 | yes_intr: | |
94 | rdpr %pstate, %g7 | |
95 | or %g7, 0x2, %g7 ! Set interrupt enable | |
96 | wrpr %g7, %pstate | |
97 | ||
98 | ||
99 | /* Initialize the NIU */ | |
100 | ||
101 | #include "niu_init_rx.h" ! Temporary added this initialization. Need to merg with niu_init.h | |
102 | !#include "niu_init.h" | |
103 | ! | |
104 | ! Thread 0 Start | |
105 | ! | |
106 | ! | |
107 | ||
108 | Init_flow: | |
109 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> RxGenConfig() | |
110 | nop | |
111 | ||
112 | rx_begin: | |
113 | nop ! $EV trig_pc_d(1, @VA(.MAIN.rx_begin)) -> printf("Configuration for Rx port",*,1) | |
114 | ||
115 | Gen_Packet: | |
116 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> Rxpktgen(0,10) | |
117 | ||
118 | setx TX_CS, %g1, %g2 | |
119 | nop | |
120 | setx Rx_loop_count, %g1, %g4 | |
121 | delay_loop: | |
122 | ldx [%g2], %g5 | |
123 | nop | |
124 | nop | |
125 | nop | |
126 | nop | |
127 | dec %g4 | |
128 | brnz %g4, delay_loop | |
129 | nop | |
130 | ||
131 | ! Have the 2 interrupts occured? | |
132 | ||
133 | intr_check: | |
134 | setx user_data_start, %g1, %g2 | |
135 | ldx [%g3], %g7 | |
136 | cmp %g7, 2 | |
137 | bne test_failed | |
138 | nop | |
139 | ||
140 | ||
141 | /********************************************************************** | |
142 | Interrupt trap handler. | |
143 | **********************************************************************/ | |
144 | ||
145 | .global my_trap_code | |
146 | ||
147 | my_trap_code: | |
148 | ||
149 | setx user_data_start, %l2, %l6 | |
150 | ||
151 | ! Increment the count | |
152 | Trap1: | |
153 | ld [%l6], %l5 | |
154 | add %l5, 1, %l5 | |
155 | st %l5, [%l6] | |
156 | membar #Sync | |
157 | ||
158 | ! Clear the interrupt | |
159 | Trap2: | |
160 | ldxa [%g0]ASI_SWVR_INTR_R, %l3 | |
161 | ||
162 | ! Re-enable the interrupt in the NIU | |
163 | Trap3: | |
164 | setx 0x8100800018, %g1, %g2 ! LDGIMGN | |
165 | setx 0x80000001, %g1, %g3 | |
166 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
167 | nop | |
168 | ||
169 | jmpl %o7+0x8, %g0 | |
170 | nop | |
171 | ||
172 | ||
173 | ||
174 | test_passed: | |
175 | EXIT_GOOD | |
176 | ||
177 | test_failed: | |
178 | EXIT_BAD | |
179 | ||
180 | ||
181 | /************************************************************************ | |
182 | Test case data start | |
183 | ************************************************************************/ | |
184 | ||
185 | .data | |
186 | user_data_start: | |
187 | .word 0x0 | |
188 | .word 0x0 | |
189 | ||
190 | SECTION descriptor data_va=0x100000200 | |
191 | attr_data { | |
192 | Name = descriptor, | |
193 | hypervisor, | |
194 | compressimage | |
195 | } | |
196 | .data | |
197 | descriptor: | |
198 | .xword 0x00008967452301 | |
199 | .xword 0x08008967452301 | |
200 | .xword 0x10008967452301 | |
201 | .xword 0x18008967452301 | |
202 | .xword 0x20008967452301 | |
203 | .xword 0x28008967452301 | |
204 | .xword 0x30008967452301 | |
205 | .xword 0x38008967452301 | |
206 | .xword 0x40008967452301 | |
207 | .xword 0x48008967452301 | |
208 | .xword 0x50008967452301 | |
209 | .xword 0x58008967452301 | |
210 | .xword 0x60008967452301 | |
211 | .xword 0x68008967452301 | |
212 | .xword 0x70008967452301 | |
213 | .xword 0x78008967452301 | |
214 | .xword 0x80008967452301 | |
215 | .xword 0x88008967452301 | |
216 | .xword 0x90008967452301 | |
217 | .xword 0x98008967452301 | |
218 | ||
219 | /************************************************************************/ |