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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_SWVR_INTR_R.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define H_HT0_Interrupt_0x60 | |
42 | #define My_HT0_Interrupt_0x60 \ | |
43 | call my_trap_code; \ | |
44 | nop; \ | |
45 | retry; \ | |
46 | nop; | |
47 | ||
48 | #include "hboot.s" | |
49 | ||
50 | #include "ncu_defines.h" | |
51 | ||
52 | /************************************************************************ | |
53 | Test case code start | |
54 | ************************************************************************/ | |
55 | ||
56 | .text | |
57 | .global main | |
58 | ||
59 | main: | |
60 | ||
61 | ! Switch to hypervisor mode. | |
62 | ||
63 | ta T_CHANGE_HPRIV | |
64 | nop | |
65 | ||
66 | ! Turn off interrupts. | |
67 | intr_off: | |
68 | rdpr %pstate, %g1 | |
69 | set 0x2, %g2 | |
70 | andn %g1, %g2,%g1 | |
71 | wrpr %g1, %g0, %pstate | |
72 | ||
73 | wr %g0, INT_VEC_DIS, %asi | |
74 | ||
75 | ||
76 | ! Generate a cross thread interrupt to this thread, 0. | |
77 | first_intr: | |
78 | mov 5, %g3 ! send to thread 0 vector number 5 | |
79 | stxa %g3, [%g0]%asi | |
80 | membar #Sync | |
81 | ||
82 | ! Wait a bit | |
83 | ||
84 | mov 8, %g4 | |
85 | ||
86 | wait1: cmp %g4, 0 | |
87 | bne wait1 | |
88 | sub %g4, 1, %g4 | |
89 | ||
90 | ! Generate a 2nd cross thread interrupt to this thread, 0. | |
91 | second_intr: | |
92 | mov 1, %g3 ! send to thread 0 vector number 1 | |
93 | stxa %g3, [%g0]%asi | |
94 | membar #Sync | |
95 | ||
96 | ! Wait a bit | |
97 | ||
98 | mov 8, %g4 | |
99 | ||
100 | wait2: cmp %g4, 0 | |
101 | bne wait2 | |
102 | sub %g4, 1, %g4 | |
103 | ||
104 | ! Generate a 3rd cross thread interrupt to this thread, 0. | |
105 | third_intr: | |
106 | mov 7, %g3 ! send to thread 0 vector number 7 | |
107 | stxa %g3, [%g0]%asi | |
108 | membar #Sync | |
109 | ||
110 | ! Wait a bit | |
111 | ||
112 | mov 20, %g4 | |
113 | ||
114 | wait3: cmp %g4, 0 | |
115 | bne wait3 | |
116 | sub %g4, 1, %g4 | |
117 | ||
118 | ! Make sure no interrupts yet. | |
119 | no_intr_check: | |
120 | setx my_trap_count, %g1, %g2 | |
121 | ld [%g2], %g3 | |
122 | cmp %g3, 0 | |
123 | bne test_failed | |
124 | nop | |
125 | ||
126 | ! Turn on interrupts | |
127 | intr_on: | |
128 | rdpr %pstate, %g1 | |
129 | set 0x2, %g2 | |
130 | or %g1, %g2,%g1 | |
131 | wrpr %g1, %g0, %pstate | |
132 | ||
133 | ! Wait a bit more | |
134 | ||
135 | mov 40, %g4 | |
136 | ||
137 | wait4: cmp %g4, 0 | |
138 | bne wait4 | |
139 | sub %g4, 1, %g4 | |
140 | ||
141 | ! Did the expected 3 interrupts occur? | |
142 | check_intr_count: | |
143 | setx my_trap_count, %g1, %g2 | |
144 | ld [%g2], %g3 | |
145 | cmp %g3, 3 | |
146 | bne test_failed | |
147 | nop | |
148 | ||
149 | ba test_passed | |
150 | nop | |
151 | ||
152 | /********************************************************************** | |
153 | Interrupt trap handler. | |
154 | **********************************************************************/ | |
155 | ||
156 | .global my_trap_code | |
157 | ||
158 | my_trap_code: | |
159 | ! Increment the count | |
160 | ||
161 | setx my_trap_count, %g6, %g7 | |
162 | ld [%g7], %g5 | |
163 | add %g5, 1, %g5 | |
164 | st %g5, [%g7] | |
165 | membar #Sync | |
166 | ||
167 | ! Check the core interrupt receive. | |
168 | trap0: | |
169 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
170 | cmp %g5, 1 | |
171 | be trap1 | |
172 | nop | |
173 | ||
174 | cmp %g5, 2 | |
175 | be trap2 | |
176 | nop | |
177 | ||
178 | set 0x2, %g3 | |
179 | set 0x1, %g2 | |
180 | ba trap3 | |
181 | nop | |
182 | trap1: | |
183 | set 0x80, %g3 | |
184 | set 0x7, %g2 | |
185 | ba trap3 | |
186 | nop | |
187 | trap2: | |
188 | set 0x20, %g3 | |
189 | set 0x5, %g2 | |
190 | trap3: | |
191 | and %g4, %g3, %g4 | |
192 | cmp %g4, %g3 | |
193 | bne test_failed | |
194 | nop | |
195 | ||
196 | ! Check the incomming vector register to make sure highest priority | |
197 | ! interrupt was done first. | |
198 | trap4: | |
199 | ldxa [%g0]ASI_SWVR_INTR_R, %g5 | |
200 | cmp %g5, %g2 | |
201 | bne test_failed | |
202 | nop | |
203 | membar #Sync | |
204 | ||
205 | ! Check that the interrupt was cleared. | |
206 | trap5: | |
207 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
208 | and %g4, %g3, %g3 | |
209 | cmp %g3, 0 | |
210 | bne test_failed | |
211 | nop | |
212 | ||
213 | jmpl %o7+0x8, %g0 | |
214 | nop | |
215 | ||
216 | ||
217 | test_passed: | |
218 | EXIT_GOOD | |
219 | ||
220 | test_failed: | |
221 | EXIT_BAD | |
222 | ||
223 | ||
224 | /************************************************************************ | |
225 | Test case data start | |
226 | ************************************************************************/ | |
227 | .data | |
228 | user_data_start: | |
229 | my_trap_count: | |
230 | .word 0x0 | |
231 | .word 0x0 | |
232 | .end | |
233 | ||
234 | ||
235 |