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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_SWVR_INTR_W.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define H_HT0_Interrupt_0x60 | |
42 | #define My_HT0_Interrupt_0x60 \ | |
43 | call my_trap_code; \ | |
44 | nop; \ | |
45 | retry; \ | |
46 | nop; | |
47 | ||
48 | #include "hboot.s" | |
49 | #include "asi_s.h" | |
50 | ||
51 | /************************************************************************ | |
52 | Test case code start | |
53 | ************************************************************************/ | |
54 | ||
55 | .text | |
56 | .global main | |
57 | ||
58 | main: | |
59 | ||
60 | ! Switch to hypervisor mode. | |
61 | ||
62 | ta T_CHANGE_HPRIV | |
63 | nop | |
64 | ||
65 | ! Generate a cross thread interrupt to this thread, 0. | |
66 | ||
67 | mov 5, %g3 ! send to thread 0 vector number 5 | |
68 | stxa %g3, [%g0]ASI_SWVR_UDB_INTR_W | |
69 | membar #Sync | |
70 | ||
71 | ! Wait a bit | |
72 | ||
73 | mov 20, %g4 | |
74 | ||
75 | wait: cmp %g4, 0 | |
76 | bne wait | |
77 | sub %g4, 1, %g4 | |
78 | ||
79 | ! Did the expected interrupt occur? Expect 1 interrupt trap. | |
80 | ||
81 | setx my_trap_count, %g1, %g2 | |
82 | ld [%g2], %g3 | |
83 | cmp %g3, 1 | |
84 | bne test_failed | |
85 | nop | |
86 | ||
87 | ba test_passed | |
88 | nop | |
89 | ||
90 | /********************************************************************** | |
91 | Interrupt trap handler. | |
92 | **********************************************************************/ | |
93 | ||
94 | .global my_trap_code | |
95 | ||
96 | my_trap_code: | |
97 | ! Increment the count | |
98 | ||
99 | setx my_trap_count, %g6, %g7 | |
100 | ld [%g7], %g5 | |
101 | add %g5, 1, %g5 | |
102 | st %g5, [%g7] | |
103 | membar #Sync | |
104 | ||
105 | ! Check the core interrupt receive and incoming vector registers. | |
106 | ||
107 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
108 | cmp %g4, 0x20 ! should be vector number 5 | |
109 | bne test_failed | |
110 | nop | |
111 | ||
112 | ! Clear the interrupt | |
113 | ||
114 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 | |
115 | cmp %g3, 0x5 ! should be vector number 5 | |
116 | bne test_failed | |
117 | nop | |
118 | ||
119 | ldxa [%g0]ASI_SWVR_INTR_RECEIVE, %g4 | |
120 | cmp %g4, 0 ! now should be 0 | |
121 | bne test_failed | |
122 | nop | |
123 | ||
124 | ldxa [%g0]ASI_SWVR_INTR_R, %g3 | |
125 | cmp %g3, 0x0 ! should also now be 0 | |
126 | bne test_failed | |
127 | nop | |
128 | ||
129 | jmpl %o7+0x8, %g0 | |
130 | nop | |
131 | ||
132 | ||
133 | test_passed: | |
134 | EXIT_GOOD | |
135 | ||
136 | test_failed: | |
137 | EXIT_BAD | |
138 | ||
139 | ||
140 | /************************************************************************ | |
141 | Test case data start | |
142 | ************************************************************************/ | |
143 | .data | |
144 | user_data_start: | |
145 | my_trap_count: | |
146 | .word 0x0 | |
147 | .word 0x0 | |
148 | .end | |
149 | ||
150 | ||
151 |