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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_SWVR_INTR_W_all_threads.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt_SWVR_INTR_W_all_threads.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#define H_HT0_Interrupt_0x60
42#define My_HT0_Interrupt_0x60 \
43 call my_trap_code; \
44 nop; \
45 retry; \
46 nop;
47
48#include "hboot.s"
49#include "asi_s.h"
50
51/************************************************************************
52 Test case code start
53 ************************************************************************/
54
55.text
56.global main
57
58main:
59
60 ! Switch to hypervisor mode.
61
62 ta T_CHANGE_HPRIV
63 nop
64
65 ! Initialize the global registers.
66 mov %g0, %g1
67 mov %g0, %g2
68 mov %g0, %g3
69 mov %g0, %g4
70 mov %g0, %g5
71 mov %g0, %g6
72 mov %g0, %g7
73
74 ta T_RD_THID
75 mov %o1, %g6 ! %o1, %g6 = thread ID
76 set 8, %l7
77 umul %g6, %l7, %l7
78 setx user_data_start, %g1, %g3
79 add %l7, %g3, %g7 ! %g7 = pointer to thread's data area
80
81 cmp %g6, 0x0
82 be main_t0 ! branch if tread 0
83 nop
84 ba main_t1_to_t63 ! branch if not thread 0
85 nop
86
87!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
88!
89! Thread 0 Start Here
90!
91!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
92
93#ifndef PORTABLE_CORE
94
95 ! For each of the 64 threads generate an interrupt to that thread
96main_t0:
97 set 63, %g3 ! %g3 = destination thread number
98 sllx %g3, 8, %g3
99 set 0x100, %g4
100
101 ! Generate a cross thread interrupt to each thread.
102t0_send_loop_top:
103 stxa %g3, [%g0]ASI_SWVR_UDB_INTR_W ! send an interrupt
104 membar #Sync
105
106 cmp %g3, 0
107 bgt t0_send_loop_top
108 sub %g3, %g4, %g3 ! decrement destination thread number
109
110#else /* ifndef PORTABLE_CORE */
111
112 ! For each thread in this core generate an interrupt to it
113main_t0:
114
115 ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID
116 or %o2, 7, %g3 ! g3 = destination thread ID
117 sllx %g3, 8, %g3
118 set 0x100, %g4
119
120 ! Loop to generate the interrupts
121t0_send_loop_top:
122 stxa %g3, [%g0]ASI_SWVR_UDB_INTR_W ! send an interrupt
123 membar #Sync
124
125 and %g3, 0x700, %g5
126 cmp %g5, 0
127 bgt t0_send_loop_top
128 sub %g3, %g4, %g3 ! decrement destination thread number
129
130#endif /* ifndef PORTABLE_CORE */
131
132 ! Wait a bit
133
134 mov 20, %g4
135
136t0_wait:
137 cmp %g4, 0
138 bne t0_wait
139 sub %g4, 1, %g4
140
141 ! Wait until interrupt occurs in this thread, 0.
142t0_1:
143 set 4000, %l4 ! l4 = timeout counter
144 mov %g7, %l2 ! l2 = interrupt count
145
146t0_wait_loop_top:
147 cmp %l4, 0
148 be test_failed ! branch if no interrupt occured
149 add %l4, -1, %l4 ! decrement wait count
150
151 ld [%l2], %l1
152 cmp %l1, 1
153 bne t0_wait_loop_top
154 nop
155
156 ! Done
157t0_2:
158 ba test_passed
159 nop
160
161!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
162!
163! All Threads Except 0 Start Here
164!
165!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
166
167 ! Wait for interrup to arrive to this thread.
168
169main_t1_to_t63:
170
171 setx 8000, %i6, %i5 ! i5 = timeout counter
172 mov %g7, %i2 ! i2 = interrupt count address
173
174wait_loop_top:
175 cmp %i5, 0
176 be test_failed ! branch if no interrupt occured
177 add %i5, -1, %i5
178
179 ld [%i2], %i1
180 cmp %i1, 1
181 bne wait_loop_top
182 nop
183
184 ! Done
185finished:
186 ba test_passed
187 nop
188
189/**********************************************************************
190 Interrupt trap handler. Same interrupt handler for all threads.
191**********************************************************************/
192
193.global my_trap_code
194
195my_trap_code:
196
197 ! Get the thread ID & find data area
198
199 ta T_RD_THID ! %o1 = thread id
200 set 8, %l0
201 umul %o1, %l0, %l1
202 setx user_data_start, %l2, %l3
203 add %l3, %l1, %l6
204
205
206 ! Increment the count
207Trap1:
208 ld [%l6], %g5
209 add %g5, 1, %g5
210 st %g5, [%l6]
211 membar #Sync
212
213 ! Clear the interrupt
214Trap2:
215 ldxa [%g0]ASI_SWVR_INTR_R, %g3
216
217 jmpl %o7+0x8, %g0
218 nop
219
220
221test_passed:
222 EXIT_GOOD
223
224test_failed:
225 EXIT_BAD
226
227
228/************************************************************************
229 Test case data start
230 ************************************************************************/
231.data
232user_data_start:
233 .word 0x0 ! Thread 0 interrupt count
234 .word 0x0
235 .word 0x0 ! Thread 1 interrupt count
236 .word 0x0
237 .word 0x0 ! etc. ...
238 .word 0x0
239 .word 0x0
240 .word 0x0
241 .word 0x0
242 .word 0x0
243 .word 0x0
244 .word 0x0
245 .word 0x0
246 .word 0x0
247 .word 0x0
248 .word 0x0
249 .word 0x0
250 .word 0x0
251 .word 0x0
252 .word 0x0
253 .word 0x0
254 .word 0x0
255 .word 0x0
256 .word 0x0
257 .word 0x0
258 .word 0x0
259 .word 0x0
260 .word 0x0
261 .word 0x0
262 .word 0x0
263 .word 0x0
264 .word 0x0
265 .word 0x0
266 .word 0x0
267 .word 0x0
268 .word 0x0
269 .word 0x0
270 .word 0x0
271 .word 0x0
272 .word 0x0
273 .word 0x0
274 .word 0x0
275 .word 0x0
276 .word 0x0
277 .word 0x0
278 .word 0x0
279 .word 0x0
280 .word 0x0
281 .word 0x0
282 .word 0x0
283 .word 0x0
284 .word 0x0
285 .word 0x0
286 .word 0x0
287 .word 0x0
288 .word 0x0
289 .word 0x0
290 .word 0x0
291 .word 0x0
292 .word 0x0
293 .word 0x0
294 .word 0x0
295 .word 0x0
296 .word 0x0
297 .word 0x0
298 .word 0x0
299 .word 0x0
300 .word 0x0
301 .word 0x0
302 .word 0x0
303 .word 0x0
304 .word 0x0
305 .word 0x0
306 .word 0x0
307 .word 0x0
308 .word 0x0
309 .word 0x0
310 .word 0x0
311 .word 0x0
312 .word 0x0
313 .word 0x0
314 .word 0x0
315 .word 0x0
316 .word 0x0
317 .word 0x0
318 .word 0x0
319 .word 0x0
320 .word 0x0
321 .word 0x0
322 .word 0x0
323 .word 0x0
324 .word 0x0
325 .word 0x0
326 .word 0x0
327 .word 0x0
328 .word 0x0
329 .word 0x0
330 .word 0x0
331 .word 0x0
332 .word 0x0
333 .word 0x0
334 .word 0x0
335 .word 0x0
336 .word 0x0
337 .word 0x0
338 .word 0x0
339 .word 0x0
340 .word 0x0
341 .word 0x0
342 .word 0x0
343 .word 0x0
344 .word 0x0
345 .word 0x0
346 .word 0x0
347 .word 0x0
348 .word 0x0
349 .word 0x0
350 .word 0x0
351 .word 0x0
352 .word 0x0
353 .word 0x0
354 .word 0x0
355 .word 0x0
356 .word 0x0
357 .word 0x0
358 .word 0x0
359 .word 0x0
360 .word 0x0
361 .word 0x0
362 .word 0x0
363 .word 0x0
364 .word 0x0
365 .word 0x0
366 .word 0x0
367 .word 0x0
368 .word 0x0
369 .word 0x0
370 .word 0x0
371.end
372
373
374
Full OpenSPARC design & verification tarball including full HDL.