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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_SWVR_INTR_W_all_vectors.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define H_HT0_Interrupt_0x60 | |
42 | #define My_HT0_Interrupt_0x60 \ | |
43 | call my_trap_code; \ | |
44 | nop; \ | |
45 | retry; \ | |
46 | nop; | |
47 | ||
48 | #include "hboot.s" | |
49 | #include "asi_s.h" | |
50 | ||
51 | /************************************************************************ | |
52 | Test case code start | |
53 | ************************************************************************/ | |
54 | ||
55 | .text | |
56 | .global main | |
57 | ||
58 | main: | |
59 | ||
60 | ! Switch to hypervisor mode. | |
61 | ||
62 | ta T_CHANGE_HPRIV | |
63 | nop | |
64 | ||
65 | ! Initialize the global registers. | |
66 | mov %g0, %g1 | |
67 | mov %g0, %g2 | |
68 | mov %g0, %g3 | |
69 | mov %g0, %g4 | |
70 | mov %g0, %g5 | |
71 | mov %g0, %g6 | |
72 | mov %g0, %g7 | |
73 | ||
74 | ! Generate 64 interrupts using all possible vector values. | |
75 | gen_intr: | |
76 | set 63, %g3 ! %g3 = vector value | |
77 | ||
78 | ! Generate a cross thread interrupt to each thread. | |
79 | send_loop_top: | |
80 | stxa %g3, [%g0]ASI_SWVR_UDB_INTR_W ! send an interrupt | |
81 | membar #Sync | |
82 | ||
83 | cmp %g3, 0 | |
84 | bgt send_loop_top | |
85 | sub %g3, 1, %g3 ! decrement vector value | |
86 | ||
87 | ! Wait a bit | |
88 | ||
89 | #ifdef DTM_ENABLED | |
90 | setx 0x140, %g1, %g4 | |
91 | #else | |
92 | setx 0x50, %g1, %g4 | |
93 | #endif | |
94 | ||
95 | wait: | |
96 | cmp %g4, 0 | |
97 | bne wait | |
98 | sub %g4, 1, %g4 | |
99 | ||
100 | ! Check to see if 64 interrupts have occured. | |
101 | intr_check: | |
102 | setx user_data_start, %g1, %g2 | |
103 | ld [%g2], %g3 | |
104 | cmp %g3, 64 | |
105 | bne test_failed | |
106 | nop | |
107 | ||
108 | ! Done | |
109 | finished: | |
110 | ba test_passed | |
111 | nop | |
112 | ||
113 | ||
114 | /********************************************************************** | |
115 | Interrupt trap handler. | |
116 | **********************************************************************/ | |
117 | ||
118 | .global my_trap_code | |
119 | ||
120 | my_trap_code: | |
121 | ||
122 | ! Get interrupt count | |
123 | ||
124 | setx user_data_start, %l2, %l6 | |
125 | ||
126 | ! Increment the count | |
127 | Trap1: | |
128 | ld [%l6], %g5 | |
129 | add %g5, 1, %g5 | |
130 | st %g5, [%l6] | |
131 | membar #Sync | |
132 | ||
133 | ! Check the interupt value | |
134 | Trap2: | |
135 | setx interrupt_value, %l2, %l3 | |
136 | ld [%l3], %l4 | |
137 | set 1, %l0 | |
138 | sllx %l0, %l4, %l0 | |
139 | ||
140 | ldxa [%g0]ASI_INTR_RECEIVE, %l7 | |
141 | and %l7, %l0, %l7 | |
142 | cmp %l7, %l0 | |
143 | bne test_failed | |
144 | nop | |
145 | ||
146 | ! Clear the interrupt and check the interrupt value | |
147 | Trap3: | |
148 | ldxa [%g0]ASI_SWVR_INTR_R, %l5 | |
149 | cmp %l5, %l4 | |
150 | bne test_failed | |
151 | nop | |
152 | ||
153 | ! Save the next expected vector value | |
154 | Trap4: | |
155 | sub %l4, 1, %l4 | |
156 | st %l4, [%l3] | |
157 | ||
158 | jmpl %o7+0x8, %g0 | |
159 | nop | |
160 | ||
161 | ||
162 | test_passed: | |
163 | EXIT_GOOD | |
164 | ||
165 | test_failed: | |
166 | EXIT_BAD | |
167 | ||
168 | ||
169 | /************************************************************************ | |
170 | Test case data start | |
171 | ************************************************************************/ | |
172 | .data | |
173 | user_data_start: | |
174 | .word 0x0 | |
175 | .word 0x0 | |
176 | interrupt_value: | |
177 | .word 63 | |
178 | .word 0x0 | |
179 | .end | |
180 | ||
181 | ||
182 |