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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_ether_send.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt_ether_send.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40#define H_HT0_Interrupt_0x60
41#define My_HT0_Interrupt_0x60 \
42 call my_trap_code; \
43 nop; \
44 retry; \
45 nop;
46
47
48#include "hboot.s"
49#include "niu_defines.h"
50#include "ncu_defines.h"
51#include "niu_macros.h"
52
53
54
55/************************************************************************
56 Test case code start
57 ************************************************************************/
58.text
59.global main
60
61main:
62 ta T_CHANGE_HPRIV
63 nop
64
65/* Initialize the NCU for the interrupt. */
66
67 ! Disable interrupts
68
69no_intr:
70 rdpr %pstate, %g7
71 xor %g7, 0x2, %g7 ! Reset interrupt enable
72 wrpr %g7, %pstate
73
74ncu_init:
75 ! Initially set all the Interrupt Management Registers
76 ! Later will set all those not used to have a different vector number
77
78 setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
79 setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
80 set 1, %g5 ! %g5 = value to write to INT_MAN reg.
81
82niu_init_loop_top:
83 stx %g5, [%g2]
84 add %g2, INT_MAN_STEP, %g2
85 cmp %g4, 1
86 bne niu_init_loop_top
87 add %g4, -1, %g4
88
89/* Initialize the NIU for TX DMA interrupt. */
90
91 NIU_TX_LD_IM0_INTR_ON_MARK( 0, %g1, %g2, %g3, %g4, 0, 0 )
92
93 ! Enable interrupts
94
95yes_intr:
96 rdpr %pstate, %g7
97 or %g7, 0x2, %g7 ! Set interrupt enable
98 wrpr %g7, %pstate
99
100Init_flow:
101 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
102
103P_TxDMAActivate:
104 setx MAC_ID, %g1, %o0 ! 1st Parameter
105 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
106 call SetTxDMAActive
107 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
108
109P_AddTxChannels :
110 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
111
112 setx LDGIMGN, %g1, %g2
113 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
114 nop
115
116P_SetTxMaxBurst :
117 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
118 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
119 call SetTxMaxBurst
120 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
121
122 setx LDGIMGN, %g1, %g2
123 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
124 nop
125
126P_InitTxDma:
127 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
128 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
129 call InitTxDma
130 nop
131
132 setx LDGIMGN, %g1, %g2
133 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
134 nop
135
136Gen_Packet:
137 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
138 nop
139
140 setx 0x5, %g1, %g4
141delay_loop_tmp:
142 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
143 nop
144 nop
145 nop
146 nop
147 dec %g4
148 brnz %g4, delay_loop_tmp
149 nop
150
151
152SetTxRingKick:
153 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
154 setx NIU_TxDmaNo, %g1, %o0
155 ldx [%g2] , %g3
156 nop
157 mulx %o0, 0x200, %g5
158 setx TX_RING_KICK_Addr, %g1, %g2
159 add %g2, %g5, %g2
160 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
161 nop
162
163SetTxCs :
164 setx NIU_TxDmaNo, %g1, %o0
165 setx TX_CS_Data, %g1, %g3
166 mulx %o0, 0x200, %g5
167 setx TX_CS_Addr, %g1, %g2
168 add %g2, %g5, %g2
169 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
170 nop
171
172#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
173 setx loop_count, %g1, %g4
174 setx LDGIMGN, %g1, %g2
175delay_loop:
176 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
177 nop
178 nop
179 nop
180 nop
181 dec %g4
182 brnz %g4, delay_loop
183 nop
184#endif
185
186 ! Wait for the interrupt to occur.
187
188 setx 0x400, %g1, %g4
189 setx old_intr_count, %g1, %g3
190 ld [%g3], %g6
191 inc %g6
192 setx user_data_start, %g1, %g5
193delay_loop:
194
195 ld [%g5], %g7
196 cmp %g7, %g6
197 beq intr_occured
198 nop
199 dec %g4
200 brnz %g4, delay_loop
201 nop
202 ba local_test_failed ! timeout waiting for interrupt
203 nop
204
205intr_occured:
206 st %g7, [%g3] ! undate old_intr_count
207
208 ! Disable the transmit dma channel
209
210disable_tx_dma:
211 setx NIU_TxDmaNo, %g1, %o0
212 setx 0x10000000, %g1, %g3 ! Set STOP_N_GO bit to halt tx dma
213 mulx %o0, 0x200, %g5
214 setx TX_CS_Addr, %g1, %g2
215 add %g2, %g5, %g2
216 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
217 nop
218
219 ! Branch back to do second packet.
220next_pkt:
221 setx user_data_start, %g1, %g2
222 cmp %g2, 1
223 beq Gen_Packet
224 nop
225 ba test_passed
226 nop
227
228 ! Check the packet count.
229
230NIUTx_Pkt_Cnt_Chk:
231 setx MAC_ID, %g1, %o0
232 setx NIU_TX_PKT_CNT, %g1, %o1
233 call NiuTx_check_pkt_cnt
234 nop
235
236 setx loop_count, %g1, %g4
237 setx LDGIMGN, %g1, %g2
238delay_loop_end:
239 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
240 nop
241 nop
242 nop
243 nop
244 dec %g4
245 brnz %g4, delay_loop_end
246 nop
247
248
249
250test_passed:
251 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
252 EXIT_GOOD
253
254local_test_failed:
255
256 ! Read related interrupt registers to aid debugging
257
258read_1:
259 ldxa [%g0]ASI_INTR_RECEIVE, %i0
260 ldxa [%g0]ASI_SWVR_INTR_R, %i1
261read_2:
262 setx INT_MAN, %g1, %g2
263 ldx [%g2], %i2
264read_3:
265 set 32, %g3 ! index for logical device number
266 setx LDG_NUM_STEP, %g1, %g4
267 mulx %g4, %g3, %g3
268 setx LDG_NUM, %g1, %g2
269 add %g3, %g2, %g2
270 ldxa [%g2]ASI_PRIMARY_LITTLE, %i3
271 setx LDSV0, %g1, %g2
272 ldxa [%g2]ASI_PRIMARY_LITTLE, %i4
273 setx LDSV1, %g1, %g2
274 ldxa [%g2]ASI_PRIMARY_LITTLE, %i5
275 setx LDSV2, %g1, %g2
276 ldxa [%g2]ASI_PRIMARY_LITTLE, %i6
277 set 32, %g3 ! index for logical device number
278 setx LD_IM0_STEP, %g1, %g4
279 mulx %g4, %g3, %g3
280 setx LD_IM0, %g1, %g2
281 add %g3, %g2, %g2
282 ldxa [%g2]ASI_PRIMARY_LITTLE, %i7
283 setx LDGIMGN, %g1, %g2
284 ldxa [%g2]ASI_PRIMARY_LITTLE, %o1
285 setx LDGITMRES, %g1, %g2
286 ldxa [%g2]ASI_PRIMARY_LITTLE, %o2
287 setx SID, %g1, %g2
288 ldxa [%g2]ASI_PRIMARY_LITTLE, %o3
289read_4:
290 setx TX_ENT_MSK, %g1, %g2
291 ldxa [%g2]ASI_PRIMARY_LITTLE, %o4
292 setx TX_CS, %g1, %g2
293 ldxa [%g2]ASI_PRIMARY_LITTLE, %o5
294 setx TDMC_INTR_DBG, %g1, %g2
295 ldxa [%g2]ASI_PRIMARY_LITTLE, %o6
296
297
298 EXIT_BAD
299
300
301
302
303/**********************************************************************
304 Interrupt trap handler.
305**********************************************************************/
306
307.global my_trap_code
308
309my_trap_code:
310
311 setx user_data_start, %l2, %l6
312
313 ! Increment the count
314Trap1:
315 ld [%l6], %l5
316 add %l5, 1, %l5
317 st %l5, [%l6]
318 membar #Sync
319
320 ! Clear the interrupt in the core
321Trap2:
322 ldxa [%g0]ASI_SWVR_INTR_R, %l3
323
324 ! The following order is important, if reversed a second
325 ! interrupt occurs on same condition.
326
327 ! Re-enable the interrupt in the transmit DMA channel
328Trap4:
329 setx TX_CS, %g1, %g2 ! TX_CS, Tx DMA channel 0
330 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1 ! Reset MK
331 nop
332
333 ! Re-enable the interrupt in the NIU
334Trap3:
335 setx LDGIMGN, %g1, %g2 ! logical device group 0
336 setx 0x80000001, %g1, %g3
337 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
338 nop
339
340 jmpl %o7+0x8, %g0
341 nop
342
343
344
345
346/************************************************************************
347 Test case data start
348 ************************************************************************/
349
350.align 1024
351.data
352user_data_start:
353 .word 0x0
354 .word 0x0
355 .word 0x0
356 .word 0x0
357old_intr_count:
358 .word 0x0
359 .word 0x0
360 .word 0x0
361 .word 0x0
362
363
364/* These initialization is temporary, as there looks some bug in mempli */
365
366SECTION SetRngConfig_init data_va=0x100000000
367attr_data {
368 Name = SetRngConfig_init,
369 hypervisor,
370 compressimage
371 }
372.data
373SetRngConfig_init:
374 .xword 0x0060452301000484
375/************************************************************************/
376
377SECTION SetTxRingKick_init data_va=0x100000100
378attr_data {
379 Name = SetTxRingKick_init,
380 hypervisor,
381 compressimage
382 }
383.data
384SetTxRingKick_init:
385 .xword 0x0060452301000484
386/************************************************************************/
387
388SECTION SetTxLPMask1_init data_va=0x100000200
389attr_data {
390 Name = SetTxLPMask1_init,
391 hypervisor,
392 compressimage
393 }
394.data
395SetTxLPMask1_init:
396 .xword 0x0060452301000484
397/************************************************************************/
398
399SECTION SetTxLPValue1_init data_va=0x100000300
400attr_data {
401 Name = SetTxLPValue1_init,
402 hypervisor,
403 compressimage
404 }
405.data
406SetTxLPValue1_init:
407 .xword 0x0060452301000484
408/************************************************************************/
409
410SECTION SetTxLPRELOC1_init data_va=0x100000400
411attr_data {
412 Name = SetTxLPRELOC1_init,
413 hypervisor,
414 compressimage
415 }
416.data
417SetTxLPRELOC1_init:
418 .xword 0x0060452301000484
419/************************************************************************/
420SECTION SetTxLPMask2_init data_va=0x100000500
421attr_data {
422 Name = SetTxLPMask2_init,
423 hypervisor,
424 compressimage
425 }
426.data
427SetTxLPMask2_init:
428 .xword 0x0060452301000484
429/************************************************************************/
430SECTION SetTxLPValue2_init data_va=0x100000600
431attr_data {
432 Name = SetTxLPValue2_init,
433 hypervisor,
434 compressimage
435 }
436.data
437SetTxLPValue2_init:
438 .xword 0x0060452301000484
439
440/************************************************************************/
441SECTION SetTxLPRELOC2_init data_va=0x100000700
442attr_data {
443 Name = SetTxLPRELOC2_init,
444 hypervisor,
445 compressimage
446 }
447.data
448SetTxLPRELOC2_init:
449 .xword 0x0060452301000484
450
451/************************************************************************/
452SECTION SetTxLPValid_init data_va=0x100000800
453attr_data {
454 Name = SetTxLPValid_init,
455 hypervisor,
456 compressimage
457 }
458.data
459SetTxLPValid_init:
460 .xword 0x0060452301000484
461
462/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.