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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: interrupt_mix.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | #define ENABLE_PCIE_LINK_TRAINING | |
40 | ||
41 | #define ENABLE_INTR0x60 1 | |
42 | ||
43 | #define INTR0x60_CC_IV_0 44 | |
44 | ||
45 | #define INTR0x60_CC_DEST_1 | |
46 | ||
47 | ||
48 | #define INTR0x60_MONDO_IV 61 | |
49 | ||
50 | #define INTR0x60_MONDO_20_V 1 | |
51 | #define INTR0x60_MONDO_20_THREAD 0 | |
52 | #define INTR0x60_MONDO_20_CNTRL 0 | |
53 | ||
54 | #define INTR0x60_INITIALIZE_INT_MAN 1 | |
55 | ||
56 | #define INTR0x60_NIU_TX_IV_0 7 | |
57 | #define INTR0x60_NIU_TX_DMA_0 3 | |
58 | #define INTR0x60_NIU_TX_THREAD_0 5 | |
59 | ||
60 | #define INTR0x60_SSI_INT_IV 31 | |
61 | #define INTR0x60_SSI_INT_THREAD 6 | |
62 | ||
63 | ||
64 | #define INTR0x60_INTA_EXTRA_HANDLER \ | |
65 | setx intr_count, %g4, %g3; \ | |
66 | add %g3, %g1, %g3; \ | |
67 | ldub [%g3], %g4; \ | |
68 | inc %g4; \ | |
69 | stb %g4, [%g3] | |
70 | #define INTR0x60_CC_EXTRA_HANDLER INTR0x60_INTA_EXTRA_HANDLER | |
71 | #define INTR0x60_NIU_TX_EXTRA_HANDLER INTR0x60_INTA_EXTRA_HANDLER | |
72 | #define INTR0x60_SSI_INT_EXTRA_HANDLER INTR0x60_INTA_EXTRA_HANDLER | |
73 | ||
74 | #include "interrupt0x60_defines.h" | |
75 | ||
76 | ||
77 | #define SYNC_THREADS 1 | |
78 | ||
79 | #include "hboot.s" | |
80 | ||
81 | #include "interrupt0x60_handler.s" | |
82 | ||
83 | ||
84 | /************************************************************************ | |
85 | Test case code start | |
86 | ************************************************************************/ | |
87 | SECTION .MAIN | |
88 | .text | |
89 | .global main | |
90 | ||
91 | main: | |
92 | ta T_CHANGE_HPRIV | |
93 | nop | |
94 | ||
95 | ldxa [%g0] ASI_INTR_ID, %g1 ! Get the thread number | |
96 | brz %g1, t0_main | |
97 | sub %g1, 2, %g2 | |
98 | brz %g2, t2_main | |
99 | sub %g1, 3, %g2 | |
100 | brz %g2, t3_main | |
101 | sub %g1, 4, %g2 | |
102 | brz %g2, t4_main | |
103 | nop | |
104 | ba intr_wait ! All other threads just wait | |
105 | nop | |
106 | ||
107 | ||
108 | /**************************************************************/ | |
109 | /* Thread 0 */ | |
110 | t0_main: | |
111 | /* Kick off an INTA interrupt */ | |
112 | ||
113 | send_inta_intr: | |
114 | #ifdef FC_NO_PEU_VERA | |
115 | ! Setup ASI - little-endian access to PCI space | |
116 | wr %g0, ASI_NL, %asi | |
117 | ||
118 | ! Offset accesses by PART_0_BASE + PCIE_MEM64_OFFSET since | |
119 | ! BAR is set that way. Physical addresses generated via TSB | |
120 | ! have this offset so mimic that when accessing directly, as here. | |
121 | best_set_reg(mpeval(N2_PCIE_BASE_ADDR | |
122 | + MEM64_OFFSET_BASE_REG_DATA | |
123 | + PCIE_MEM64_OFFSET | |
124 | + PART_0_BASE | |
125 | + (INTR0x60_MONDO_20_DMAEPT_ENGINE << 8)), | |
126 | %l7, %l2) | |
127 | mov %g0, %i1 /* Address 0 for now */ | |
128 | ! Store upper half of address | |
129 | srlx %i1, 32, %l0 | |
130 | !setx 0xfffc0000, %l1, %l0 ! Always bypass for now. | |
131 | stwa %l0, [%l2+DMAEPT_DATA_ADDR_UPPER] %asi | |
132 | ||
133 | ! Store lower half of address | |
134 | stwa %i1, [%l2+DMAEPT_DATA_ADDR_LOWER] %asi | |
135 | ||
136 | ! Store pattern value | |
137 | mov %g0, %i2 /* Pattern 0 */ | |
138 | stwa %i2, [%l2+DMAEPT_PATTERN] %asi | |
139 | ||
140 | ! Interrupt type | |
141 | best_set_reg(DMAEPT_ENDING_INTERRUPT_INTA, %l7, %l5) | |
142 | stwa %l5, [%l2+DMAEPT_ENDING_INTERRUPT] %asi | |
143 | ||
144 | ! Packet size | |
145 | mov 4, %i4 /* Max of 4 DW */ | |
146 | stwa %i4, [%l2+DMAEPT_MAX_PYLD] %asi | |
147 | ||
148 | ! Tag for MR operations, use engine ID | |
149 | mov INTR0x60_MONDO_20_DMAEPT_ENGINE, %i0 | |
150 | stwa %i0, [%l2+DMAEPT_TAG] %asi | |
151 | ||
152 | ! Fire the DMA | |
153 | best_set_reg(DMAEPT_OPERATION_MW, %l7, %i1) /* 0-byte write */ | |
154 | stwa %i1, [%l2+DMAEPT_OPERATION] %asi | |
155 | ||
156 | #else /* FC_NO_PEU_VERA */ | |
157 | ! user event to generate ASSERT_INTA msg. | |
158 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_inta_intr)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1, *, 1 ) | |
159 | nop | |
160 | #endif /* FC_NO_PEU_VERA */ | |
161 | ||
162 | /* We are all done sending interrupts, so go to the wait loop */ | |
163 | ba intr_wait | |
164 | nop | |
165 | ||
166 | ||
167 | /**************************************************************/ | |
168 | /* Thread 2 */ | |
169 | t2_main: | |
170 | /* Kick off an NIU interrupt */ | |
171 | ||
172 | send_niu_intr: | |
173 | ! Generate the interrupt via PIO write | |
174 | best_set_reg(TDMC_INTR_DBG, %l1, %l2) | |
175 | mov INTR0x60_NIU_TX_DMA_0, %l7 | |
176 | best_set_reg(TDMC_STEP, %l1, %l3) | |
177 | mulx %l7, %l3, %l7 | |
178 | add %l2, %l7, %l2 | |
179 | best_set_reg(0x8000, %l1, %l4) | |
180 | stxa %l4, [%l2]ASI_PRIMARY_LITTLE | |
181 | ||
182 | ||
183 | /* We are all done sending interrupts, so go to the wait loop */ | |
184 | ba intr_wait | |
185 | nop | |
186 | ||
187 | ||
188 | /**************************************************************/ | |
189 | /* Thread 3 */ | |
190 | t3_main: | |
191 | /* Kick off an SSI_EXT_INT_L interrupt to thread 6 */ | |
192 | ||
193 | send_ssi_intr: | |
194 | ! user event to generate SSI_EXT_INT_L as soon as possible | |
195 | nop ! $EV trig_pc_d(1, @VA(.MAIN.send_ssi_intr)) -> extint (0, 8) | |
196 | /* We are all done sending interrupts, so go to the wait loop */ | |
197 | ba intr_wait | |
198 | nop | |
199 | ||
200 | ||
201 | /**************************************************************/ | |
202 | /* Thread 4 */ | |
203 | t4_main: | |
204 | /* Kick off an cross-call interrupt to thread 1 */ | |
205 | ||
206 | send_cc_intr_to_thread_1: | |
207 | best_set_reg(mpeval((1<<8)+INTR0x60_CC_IV_0), %g2, %g3) | |
208 | stxa %g3, [%g0]ASI_INTR_W | |
209 | ||
210 | /* We are all done sending interrupts, so go to the wait loop */ | |
211 | ba intr_wait | |
212 | nop | |
213 | ||
214 | ||
215 | /**************************************************************/ | |
216 | /* Common wait loop for all threads */ | |
217 | intr_wait: | |
218 | setx intr_expect, %l1, %g4 | |
219 | add %g4, %g1, %g4 ! address of expected interrupt count for this thread | |
220 | ldub [%g4], %g4 | |
221 | ||
222 | setx intr_count, %l1, %g3 | |
223 | add %g3, %g1, %g3 ! address of interrupt count for this thread | |
224 | ||
225 | best_set_reg(0x200, %l1, %g2) ! timeout count | |
226 | ||
227 | intr_wait_loop_top: | |
228 | ldub [%g3], %g5 | |
229 | cmp %g5, %g4 | |
230 | be thread_passed | |
231 | dec %g2 | |
232 | ||
233 | cmp %g2, 0 | |
234 | bne intr_wait_loop_top | |
235 | nop | |
236 | ||
237 | intr_timeout: | |
238 | !$EV trig_pc_d(1, @VA(.MAIN.intr_timeout)) -> printf("ERROR: Timeout waiting for interrupt",*,1) | |
239 | EXIT_BAD | |
240 | ||
241 | thread_passed: | |
242 | EXIT_GOOD | |
243 | ||
244 | local_test_failed: | |
245 | EXIT_BAD | |
246 | ||
247 | ||
248 | ||
249 | /************************************************************************ | |
250 | Test case data start | |
251 | ************************************************************************/ | |
252 | ||
253 | .align 1024 | |
254 | .data | |
255 | user_data_start: | |
256 | intr_expect: | |
257 | .byte 0x1 ! expected interrupt count for thread 0 | |
258 | .byte 0x1 ! expected interrupt count for thread 1 | |
259 | .byte 0x0 ! expected interrupt count for thread 2 | |
260 | .byte 0x0 ! expected interrupt count for thread 3 | |
261 | .byte 0x0 ! expected interrupt count for thread 4 | |
262 | .byte 0x1 ! expected interrupt count for thread 5 | |
263 | .byte 0x1 ! expected interrupt count for thread 6 | |
264 | .byte 0x0 ! expected interrupt count for thread 7 | |
265 | user_data_end: | |
266 | ||
267 | ||
268 | SECTION .HTRAPS | |
269 | .data | |
270 | .global intr_count | |
271 | intr_count: | |
272 | .byte 0x0 ! interrupt count for thread 0 | |
273 | .byte 0x0 ! interrupt count for thread 1 | |
274 | .byte 0x0 ! interrupt count for thread 2 | |
275 | .byte 0x0 ! interrupt count for thread 3 | |
276 | .byte 0x0 ! interrupt count for thread 4 | |
277 | .byte 0x0 ! interrupt count for thread 5 | |
278 | .byte 0x0 ! interrupt count for thread 6 | |
279 | .byte 0x0 ! interrupt count for thread 7 | |
280 | ||
281 | .end | |
282 | ||
283 | /************************************************************************/ |