[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_ncu_regs_rw.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: interrupt_ncu_regs_rw.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "asi_s.h"
#include "ncu_defines.h"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:

	! Switch to hypervisor mode.

	ta	T_CHANGE_HPRIV
	nop
	ta	T_CHANGE_PRIV
	nop
pstate:	
	rdpr	%pstate, %l0
	and	%l0, 0x2, %l1
	wrpr	%l0, %l1, %pstate	! Disable interrupts

	setx	-1, %l0, %l7			! l7 = data of all 1's

	! Test the 128 INT_MAN regs.

int_man0:
	setx	INT_MAN, %l0, %l1
	set	INT_MAN_COUNT, %l2

	! First store data of all 1's
int_man_loop_top0:
	stx	%l7, [%l1]
	add	%l1, INT_MAN_STEP, %l1
	cmp	%l2, 1
	bne	int_man_loop_top0
	add	%l2, -1, %l2

int_man1:
	setx	INT_MAN, %l0, %l1
	set	INT_MAN_COUNT, %l2
	setx	0x3f3f, %l0, %l3	! expected data

	! Read and test the data, only bits [13:8] and [5:0] are R/W
int_man_loop_top1:
	ldx	[%l1], %l4
	add	%l1, INT_MAN_STEP, %l1
	cmp	%l4, %l3
	bne	test_failed
	nop
	cmp	%l2, 1
	bne	int_man_loop_top1
	add	%l2, -1, %l2
	
int_man2:
	setx	INT_MAN, %l0, %l1
	set	INT_MAN_COUNT, %l2

	! First store data of all 0's
int_man_loop_top2:
	stx	%g0, [%l1]
	add	%l1, INT_MAN_STEP, %l1
	cmp	%l2, 1
	bne	int_man_loop_top2
	add	%l2, -1, %l2

int_man3:
	setx	INT_MAN, %l0, %l1
	set	INT_MAN_COUNT, %l2

	! Read and test the data
int_man_loop_top3:
	ldx	[%l1], %l4
	add	%l1, INT_MAN_STEP, %l1
	cmp	%l4, 0
	bne	test_failed
	nop
	cmp	%l2, 1
	bne	int_man_loop_top3
	add	%l2, -1, %l2


	! Test the MONDO_INT_VEC register

mondo_int_vec1:
	setx	MONDO_INT_VEC, %l0, %l1
	orn	%g0, %g0, %l2
	stx	%l2, [%l1]		! write data of all 1's
	membar	#Sync

	set	0x3f, %l3
	ldx	[%l1], %l4
	cmp	%l4, %l3
	bne	test_failed		! Only bits [5:0] are R/W, rest R0
	nop

mondo_int_vec2:
	stx	%g0, [%l1]		! write data of all 0's
	membar	#Sync

	ldx	[%l1], %l4
	cmp	%l4, %g0
	bne	test_failed
	nop

	! Test the Interrupt Vector Dispatch Register
	! Note that this is a write only register

int_vec_dis1:
	wr      %g0, INT_VEC_DIS, %asi
	orn	%g0, %g0, %l3
	stxa	%l3, [%g0]%asi		! write data of all 1's
	membar	#Sync

int_vec_dis2:
	stxa	%g0, [%g0]%asi		! write data of all 0's
	membar	#Sync

	! Test the Mondo Interrupt Registers
	! Can't be tested until a mondo interrupt occurs
	! which is beyond the scope of this diag.

	ba	test_passed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
	.word	0x0
	.word	0x0
user_data_end:	
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: interrupt_ncu_regs_rw.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#include "hboot.s"
	42	#include "asi_s.h"
	43	#include "ncu_defines.h"
	44
	45	/************************************************************************
	46	Test case code start
	47	************************************************************************/
	48
	49	.text
	50	.global main
	51
	52	main:
	53
	54	! Switch to hypervisor mode.
	55
	56	ta T_CHANGE_HPRIV
	57	nop
	58	ta T_CHANGE_PRIV
	59	nop
	60	pstate:
	61	rdpr %pstate, %l0
	62	and %l0, 0x2, %l1
	63	wrpr %l0, %l1, %pstate ! Disable interrupts
	64
65	setx -1, %l0, %l7 ! l7 = data of all 1's
66
67	! Test the 128 INT_MAN regs.
68
69	int_man0:
70	setx INT_MAN, %l0, %l1
71	set INT_MAN_COUNT, %l2
72
73	! First store data of all 1's
74	int_man_loop_top0:
75	stx %l7, [%l1]
76	add %l1, INT_MAN_STEP, %l1
77	cmp %l2, 1
78	bne int_man_loop_top0
79	add %l2, -1, %l2
80
81	int_man1:
82	setx INT_MAN, %l0, %l1
83	set INT_MAN_COUNT, %l2
84	setx 0x3f3f, %l0, %l3 ! expected data
85
86	! Read and test the data, only bits [13:8] and [5:0] are R/W
87	int_man_loop_top1:
88	ldx [%l1], %l4
89	add %l1, INT_MAN_STEP, %l1
90	cmp %l4, %l3
91	bne test_failed
92	nop
93	cmp %l2, 1
94	bne int_man_loop_top1
95	add %l2, -1, %l2
96
97	int_man2:
98	setx INT_MAN, %l0, %l1
99	set INT_MAN_COUNT, %l2
100
101	! First store data of all 0's
102	int_man_loop_top2:
103	stx %g0, [%l1]
104	add %l1, INT_MAN_STEP, %l1
105	cmp %l2, 1
106	bne int_man_loop_top2
107	add %l2, -1, %l2
108
109	int_man3:
110	setx INT_MAN, %l0, %l1
111	set INT_MAN_COUNT, %l2
112
113	! Read and test the data
114	int_man_loop_top3:
115	ldx [%l1], %l4
116	add %l1, INT_MAN_STEP, %l1
117	cmp %l4, 0
118	bne test_failed
119	nop
120	cmp %l2, 1
121	bne int_man_loop_top3
122	add %l2, -1, %l2
123
124
125	! Test the MONDO_INT_VEC register
126
127	mondo_int_vec1:
128	setx MONDO_INT_VEC, %l0, %l1
129	orn %g0, %g0, %l2
130	stx %l2, [%l1] ! write data of all 1's
131	membar #Sync
132
133	set 0x3f, %l3
134	ldx [%l1], %l4
135	cmp %l4, %l3
136	bne test_failed ! Only bits [5:0] are R/W, rest R0
137	nop
138
139	mondo_int_vec2:
140	stx %g0, [%l1] ! write data of all 0's
141	membar #Sync
142
143	ldx [%l1], %l4
144	cmp %l4, %g0
145	bne test_failed
146	nop
147
148	! Test the Interrupt Vector Dispatch Register
149	! Note that this is a write only register
150
151	int_vec_dis1:
152	wr %g0, INT_VEC_DIS, %asi
153	orn %g0, %g0, %l3
154	stxa %l3, [%g0]%asi ! write data of all 1's
155	membar #Sync
156
157	int_vec_dis2:
158	stxa %g0, [%g0]%asi ! write data of all 0's
159	membar #Sync
160
161	! Test the Mondo Interrupt Registers
162	! Can't be tested until a mondo interrupt occurs
163	! which is beyond the scope of this diag.
164
165	ba test_passed
166	nop
167
168	test_passed:
169	EXIT_GOOD
170
171	test_failed:
172	EXIT_BAD
173
174
175	/************************************************************************
176	Test case data start
177	************************************************************************/
178	.data
179	user_data_start:
180	.word 0x0
181	.word 0x0
182	user_data_end:
183	.end
184
185
186