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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_niu_sys_data.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt_niu_sys_data.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40#define H_HT0_Interrupt_0x60
41#define My_HT0_Interrupt_0x60 \
42 call my_trap_code; \
43 nop; \
44 retry; \
45 nop;
46
47
48#include "hboot.s"
49#include "niu_defines.h"
50#include "ncu_defines.h"
51#include "niu_macros.h"
52
53
54
55/************************************************************************
56 Test case code start
57 ************************************************************************/
58.text
59.global main
60
61main:
62 ta T_CHANGE_HPRIV
63 nop
64
65/* Initialize the NCU for the interrupt. */
66
67 ! Disable interrupts
68
69no_intr:
70 rdpr %pstate, %g7
71 xor %g7, 0x2, %g7 ! Reset interrupt enable
72 wrpr %g7, %pstate
73
74ncu_init:
75 ! Initially set all the Interrupt Management Registers
76
77 setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
78 setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
79 mov %g0, %g5
80
81niu_init_loop_top:
82 stx %g5, [%g2]
83 add %g2, INT_MAN_STEP, %g2
84 stx %g5, [%g2]
85 add %g2, INT_MAN_STEP, %g2
86 add %g5, 1, %g5 ! increment the vector number
87 add %g4, -2, %g4
88 cmp %g4, 0
89 bgt niu_init_loop_top
90 nop
91
92/* Initialize the NIU for TX DMA interrupt. */
93
94 NIU_TX_LD_IM0_INTR_ON_MARK( 0, %g1, %g2, %g3, %g4, 0, 0x40 )
95
96 ! Enable interrupts
97
98yes_intr:
99 rdpr %pstate, %g7
100 or %g7, 0x2, %g7 ! Set interrupt enable
101 wrpr %g7, %pstate
102
103Init_flow:
104 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
105
106P_TxDMAActivate:
107 setx MAC_ID, %g1, %o0 ! 1st Parameter
108 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
109 call SetTxDMAActive
110 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
111
112P_AddTxChannels :
113 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
114
115 setx LDGIMGN, %g1, %g2
116 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
117 nop
118
119P_SetTxMaxBurst :
120 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
121 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
122 call SetTxMaxBurst
123 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
124
125 setx LDGIMGN, %g1, %g2
126 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
127 nop
128
129P_InitTxDma:
130 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
131 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
132 call InitTxDma
133 nop
134
135 setx LDGIMGN, %g1, %g2
136 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
137 nop
138
139Gen_Packet:
140 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
141 nop
142
143 setx 0x5, %g1, %g4
144delay_loop_tmp:
145 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
146 nop
147 nop
148 nop
149 nop
150 dec %g4
151 brnz %g4, delay_loop_tmp
152 nop
153
154
155SetTxRingKick:
156 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
157 setx NIU_TxDmaNo, %g1, %o0
158 ldx [%g2] , %g3
159 nop
160 mulx %o0, 0x200, %g5
161 setx TX_RING_KICK_Addr, %g1, %g2
162 add %g2, %g5, %g2
163 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
164 nop
165
166SetTxCs :
167 setx NIU_TxDmaNo, %g1, %o0
168 setx TX_CS_Data, %g1, %g3
169 mulx %o0, 0x200, %g5
170 setx TX_CS_Addr, %g1, %g2
171 add %g2, %g5, %g2
172 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
173 nop
174
175#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
176 setx loop_count, %g1, %g4
177 setx LDGIMGN, %g1, %g2
178delay_loop:
179 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
180 nop
181 nop
182 nop
183 nop
184 dec %g4
185 brnz %g4, delay_loop
186 nop
187#endif
188
189 ! Wait for the interrupt to occur.
190
191 setx 0x400, %g1, %g4
192 setx user_data_start, %g1, %g5
193delay_loop:
194
195 ld [%g5], %g7
196 cmp %g7, 1
197 beq intr_occured
198 nop
199 dec %g4
200 brnz %g4, delay_loop
201 nop
202 ba local_test_failed ! timeout waiting for interrupt
203 nop
204
205intr_occured:
206 st %g7, [%g3] ! undate old_intr_count
207
208 ! Check the packet count.
209
210NIUTx_Pkt_Cnt_Chk:
211 setx MAC_ID, %g1, %o0
212 setx NIU_TX_PKT_CNT, %g1, %o1
213 call NiuTx_check_pkt_cnt
214 nop
215
216 setx loop_count, %g1, %g4
217 setx LDGIMGN, %g1, %g2
218delay_loop_end:
219 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
220 nop
221 nop
222 nop
223 nop
224 dec %g4
225 brnz %g4, delay_loop_end
226 nop
227
228
229test_passed:
230 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
231 EXIT_GOOD
232
233local_test_failed:
234
235 ! Read related interrupt registers to aid debugging
236
237read_1:
238 ldxa [%g0]ASI_INTR_RECEIVE, %i0
239 ldxa [%g0]ASI_SWVR_INTR_R, %i1
240read_2:
241 setx INT_MAN, %g1, %g2
242 ldx [%g2], %i2
243read_3:
244 set 32, %g3 ! index for logical device number
245 setx LDG_NUM_STEP, %g1, %g4
246 mulx %g4, %g3, %g3
247 setx LDG_NUM, %g1, %g2
248 add %g3, %g2, %g2
249 ldxa [%g2]ASI_PRIMARY_LITTLE, %i3
250 setx LDSV0, %g1, %g2
251 ldxa [%g2]ASI_PRIMARY_LITTLE, %i4
252 setx LDSV1, %g1, %g2
253 ldxa [%g2]ASI_PRIMARY_LITTLE, %i5
254 setx LDSV2, %g1, %g2
255 ldxa [%g2]ASI_PRIMARY_LITTLE, %i6
256 set 32, %g3 ! index for logical device number
257 setx LD_IM0_STEP, %g1, %g4
258 mulx %g4, %g3, %g3
259 setx LD_IM0, %g1, %g2
260 add %g3, %g2, %g2
261 ldxa [%g2]ASI_PRIMARY_LITTLE, %i7
262 setx LDGIMGN, %g1, %g2
263 ldxa [%g2]ASI_PRIMARY_LITTLE, %o1
264 setx LDGITMRES, %g1, %g2
265 ldxa [%g2]ASI_PRIMARY_LITTLE, %o2
266 setx SID, %g1, %g2
267 ldxa [%g2]ASI_PRIMARY_LITTLE, %o3
268read_4:
269 setx TX_ENT_MSK, %g1, %g2
270 ldxa [%g2]ASI_PRIMARY_LITTLE, %o4
271 setx TX_CS, %g1, %g2
272 ldxa [%g2]ASI_PRIMARY_LITTLE, %o5
273 setx TDMC_INTR_DBG, %g1, %g2
274 ldxa [%g2]ASI_PRIMARY_LITTLE, %o6
275
276
277 EXIT_BAD
278
279
280
281
282/**********************************************************************
283 Interrupt trap handler.
284**********************************************************************/
285
286.global my_trap_code
287
288my_trap_code:
289
290 setx user_data_start, %l2, %l6
291
292 ! Increment the count
293Trap0:
294 ld [%l6], %l5
295 add %l5, 1, %l5
296 st %l5, [%l6]
297 membar #Sync
298
299 ! Check the expected vector number and clear the interrupt in the core.
300Trap1:
301 ldxa [%g0]ASI_INTR_R, %l7
302 cmp %l7, 0x20
303 bne local_test_failed
304 nop
305
306 ! The following order is important, if reversed a second
307 ! interrupt occurs on same condition.
308
309 ! Re-enable the interrupt in the transmit DMA channel
310Trap4:
311 setx TX_CS, %g1, %g2 ! TX_CS, Tx DMA channel 0
312 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1 ! Reset MK
313 nop
314
315 ! Re-enable the interrupt in the NIU
316Trap3:
317 setx LDGIMGN, %g1, %g2 ! logical device group 0
318 setx 0x80000001, %g1, %g3
319 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
320 nop
321
322 jmpl %o7+0x8, %g0
323 nop
324
325
326
327
328/************************************************************************
329 Test case data start
330 ************************************************************************/
331
332.align 1024
333.data
334user_data_start:
335 .word 0x0
336 .word 0x0
337 .word 0x0
338 .word 0x0
339old_intr_count:
340 .word 0x0
341 .word 0x0
342 .word 0x0
343 .word 0x0
344
345
346/* These initialization is temporary, as there looks some bug in mempli */
347
348SECTION SetRngConfig_init data_va=0x100000000
349attr_data {
350 Name = SetRngConfig_init,
351 hypervisor,
352 compressimage
353 }
354.data
355SetRngConfig_init:
356 .xword 0x0060452301000484
357/************************************************************************/
358
359SECTION SetTxRingKick_init data_va=0x100000100
360attr_data {
361 Name = SetTxRingKick_init,
362 hypervisor,
363 compressimage
364 }
365.data
366SetTxRingKick_init:
367 .xword 0x0060452301000484
368/************************************************************************/
369
370SECTION SetTxLPMask1_init data_va=0x100000200
371attr_data {
372 Name = SetTxLPMask1_init,
373 hypervisor,
374 compressimage
375 }
376.data
377SetTxLPMask1_init:
378 .xword 0x0060452301000484
379/************************************************************************/
380
381SECTION SetTxLPValue1_init data_va=0x100000300
382attr_data {
383 Name = SetTxLPValue1_init,
384 hypervisor,
385 compressimage
386 }
387.data
388SetTxLPValue1_init:
389 .xword 0x0060452301000484
390/************************************************************************/
391
392SECTION SetTxLPRELOC1_init data_va=0x100000400
393attr_data {
394 Name = SetTxLPRELOC1_init,
395 hypervisor,
396 compressimage
397 }
398.data
399SetTxLPRELOC1_init:
400 .xword 0x0060452301000484
401/************************************************************************/
402SECTION SetTxLPMask2_init data_va=0x100000500
403attr_data {
404 Name = SetTxLPMask2_init,
405 hypervisor,
406 compressimage
407 }
408.data
409SetTxLPMask2_init:
410 .xword 0x0060452301000484
411/************************************************************************/
412SECTION SetTxLPValue2_init data_va=0x100000600
413attr_data {
414 Name = SetTxLPValue2_init,
415 hypervisor,
416 compressimage
417 }
418.data
419SetTxLPValue2_init:
420 .xword 0x0060452301000484
421
422/************************************************************************/
423SECTION SetTxLPRELOC2_init data_va=0x100000700
424attr_data {
425 Name = SetTxLPRELOC2_init,
426 hypervisor,
427 compressimage
428 }
429.data
430SetTxLPRELOC2_init:
431 .xword 0x0060452301000484
432
433/************************************************************************/
434SECTION SetTxLPValid_init data_va=0x100000800
435attr_data {
436 Name = SetTxLPValid_init,
437 hypervisor,
438 compressimage
439 }
440.data
441SetTxLPValid_init:
442 .xword 0x0060452301000484
443
444/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.