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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_pci_regs.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt_pci_regs.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#include "hboot.s"
42#include "asi_s.h"
43#include "peu_defines.h"
44
45/************************************************************************
46 Test case code start
47 ************************************************************************/
48
49.text
50.global main
51
52main:
53
54 ! Switch to hypervisor mode.
55
56 ta T_CHANGE_HPRIV
57 nop
58 ta T_CHANGE_PRIV
59 nop
60pstate:
61 rdpr %pstate, %l0
62 and %l0, 0x2, %l1
63 wrpr %l0, %l1, %pstate ! Disable interrupts
64
65 ! Interrupt Mapping registers
66map_write_1:
67 setx PCI_E_INT_MAP_ADDR, %g1, %g2
68 set PCI_E_INT_MAP_COUNT, %g3
69 set PCI_E_INT_MAP_STEP, %g4
70 setx 0x80000000fe0003C0, %g1, %g5
71
72map_write_1_loop:
73 stx %g5, [%g2]
74 addx %g2, %g4, %g2
75 cmp %g3, 1
76 bne map_write_1_loop
77 dec %g3
78
79 ! Two more registers to write, and skip over "missing" 2 registers.
80map_write_1_extra:
81 addx %g2, %g4, %g2
82 addx %g2, %g4, %g2
83 stx %g5, [%g2]
84 addx %g2, %g4, %g2
85 stx %g5, [%g2]
86
87map_read_1:
88 setx PCI_E_INT_MAP_ADDR, %g1, %g2
89 set PCI_E_INT_MAP_COUNT, %g3
90
91map_read_1_loop:
92 ldx [%g2], %g7
93 addx %g2, %g4, %g2
94 cmp %g7, %g5
95 bne test_failed
96 nop
97 cmp %g3, 1
98 bne map_read_1_loop
99 dec %g3
100
101 ! Two more registers to read, and ship over "missing" 2 registers.
102map_read_1_extra:
103 addx %g2, %g4, %g2
104 addx %g2, %g4, %g2
105 ldx [%g2], %g7
106 addx %g2, %g4, %g2
107 cmp %g7, %g5
108 bne test_failed
109 nop
110 ldx [%g2], %g7
111 cmp %g7, %g5
112 bne test_failed
113 nop
114
115map_write_0:
116 setx PCI_E_INT_MAP_ADDR, %g1, %g2
117 set PCI_E_INT_MAP_COUNT, %g3
118 set PCI_E_INT_MAP_STEP, %g4
119
120map_write_0_loop:
121 stx %g0, [%g2]
122 addx %g2, %g4, %g2
123 cmp %g3, 1
124 bne map_write_0_loop
125 dec %g3
126
127 ! Two more registers to write, and skip over "missing" 2 registers.
128map_write_0_extra:
129 addx %g2, %g4, %g2
130 addx %g2, %g4, %g2
131 stx %g0, [%g2]
132 addx %g2, %g4, %g2
133 stx %g0, [%g2]
134
135map_read_0:
136 setx PCI_E_INT_MAP_ADDR, %g1, %g2
137 set PCI_E_INT_MAP_COUNT, %g3
138
139map_read_0_loop:
140 ldx [%g2], %g7
141 addx %g2, %g4, %g2
142 cmp %g7, 0
143 bne test_failed
144 nop
145 cmp %g3, 1
146 bne map_read_0_loop
147 dec %g3
148
149 ! Two more registers to read, and ship over "missing" 2 registers.
150map_read_0_extra:
151 addx %g2, %g4, %g2
152 addx %g2, %g4, %g2
153 ldx [%g2], %g7
154 addx %g2, %g4, %g2
155 cmp %g7, 0
156 bne test_failed
157 nop
158 ldx [%g2], %g7
159 cmp %g7, 0
160 bne test_failed
161 nop
162
163 ! Interrupt Clear registers
164
165clear:
166 setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
167 set PCI_E_INT_CLEAR_COUNT, %g3
168 set PCI_E_INT_CLEAR_STEP, %g4
169 set 3, %g5
170
171clear_write_1_loop:
172 stx %g5, [%g2]
173 addx %g2, %g4, %g2
174 cmp %g3, 1
175 bne clear_write_1_loop
176 dec %g3
177
178 ! Two more registers to write, and skip over "missing" 2 registers.
179clear_write_1_extra:
180 addx %g2, %g4, %g2
181 addx %g2, %g4, %g2
182 stx %g5, [%g2]
183 addx %g2, %g4, %g2
184 stx %g5, [%g2]
185
186clear_read_1:
187 setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
188 set PCI_E_INT_CLEAR_COUNT, %g3
189
190clear_read_1_loop:
191 ldx [%g2], %g7
192 addx %g2, %g4, %g2
193 cmp %g7, %g5
194 bne test_failed
195 nop
196 cmp %g3, 1
197 bne clear_read_1_loop
198 dec %g3
199
200 ! Two more registers to read, and ship over "missing" 2 registers.
201clear_read_1_extra:
202 addx %g2, %g4, %g2
203 addx %g2, %g4, %g2
204 ldx [%g2], %g7
205 addx %g2, %g4, %g2
206 cmp %g7, %g5
207 bne test_failed
208 nop
209 ldx [%g2], %g7
210 cmp %g7, %g5
211 bne test_failed
212 nop
213
214clear_write_0:
215 setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
216 set PCI_E_INT_CLEAR_COUNT, %g3
217 set PCI_E_INT_CLEAR_STEP, %g4
218
219clear_write_0_loop:
220 stx %g0, [%g2]
221 addx %g2, %g4, %g2
222 cmp %g3, 1
223 bne clear_write_0_loop
224 dec %g3
225
226 ! Two more registers to write, and skip over "missing" 2 registers.
227clear_write_0_extra:
228 addx %g2, %g4, %g2
229 addx %g2, %g4, %g2
230 stx %g0, [%g2]
231 addx %g2, %g4, %g2
232 stx %g0, [%g2]
233
234clear_read_0:
235 setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
236 set PCI_E_INT_CLEAR_COUNT, %g3
237
238clear_read_0_loop:
239 ldx [%g2], %g7
240 addx %g2, %g4, %g2
241 cmp %g7, 0
242 bne test_failed
243 nop
244 cmp %g3, 1
245 bne clear_read_0_loop
246 dec %g3
247
248 ! Two more registers to read, and ship over "missing" 2 registers.
249clear_read_0_extra:
250 addx %g2, %g4, %g2
251 addx %g2, %g4, %g2
252 ldx [%g2], %g7
253 addx %g2, %g4, %g2
254 cmp %g7, 0
255 bne test_failed
256 nop
257 ldx [%g2], %g7
258 cmp %g7, 0
259 bne test_failed
260 nop
261
262 ! Interrupt Retry Timer register
263
264retry_timer_write_1:
265 setx PCI_E_INT_RETRY_TIMER_ADDR, %g1, %g2
266 setx 0x01ffffff, %g1, %g3
267 stx %g3, [%g2]
268
269retry_timer_read_1:
270 ldx [%g2], %g4
271 cmp %g4, %g3
272 bne test_failed
273 nop
274
275retry_timer_write_0:
276 stx %g0, [%g2]
277
278retry_timer_read_0:
279 ldx [%g2], %g5
280 cmp %g5, 0
281 bne test_failed
282 nop
283
284 ! Interrupt State Status registers 1 and 2, read only
285
286state_status:
287 setx PCI_E_INT_STATE_STATUS_1_ADDR, %g1, %g2
288 setx PCI_E_INT_STATE_STATUS_2_ADDR, %g1, %g3
289 ldx [%g2], %g0
290 ldx [%g3], %g0
291
292 ! INTX Status register, read only
293
294intx_status:
295 setx PCI_E_INTX_STATUS_ADDR, %g1, %g2
296 ldx [%g2], %g0
297
298 ! INT A/B/C/D Clear registers, RW1C
299
300int_abcd_clear:
301 set 1, %g7
302 setx PCI_E_INT_A_CLEAR_ADDR, %g1, %g2
303 setx PCI_E_INT_B_CLEAR_ADDR, %g1, %g3
304 setx PCI_E_INT_C_CLEAR_ADDR, %g1, %g4
305 setx PCI_E_INT_D_CLEAR_ADDR, %g1, %g5
306
307int_abcd_clear_write:
308 stx %g7, [%g2]
309 stx %g7, [%g3]
310 stx %g7, [%g4]
311 stx %g7, [%g5]
312
313int_abce_clear_read:
314 ldx [%g2], %g6
315 cmp %g6, 0
316 bne test_failed
317 nop
318
319 ldx [%g3], %g6
320 cmp %g6, 0
321 bne test_failed
322 nop
323
324 ldx [%g4], %g6
325 cmp %g6, 0
326 bne test_failed
327 nop
328
329 ldx [%g5], %g6
330 cmp %g6, 0
331 bne test_failed
332 nop
333
334 ! Event Queue Base Address register.
335
336event_que_base_addr:
337 setx PCI_E_EV_QUE_BASE_ADDRESS_ADDR, %g1, %g2
338
339event_que_base_addr_write_1:
340 subx %g0, 1, %g3
341 stx %g3, [%g2]
342
343event_que_base_addr_read_1:
344 setx 0xfffffffffff80000, %g1, %g3
345 ldx [%g2], %g4
346 cmp %g4, %g3
347 bne test_failed
348 nop
349
350event_que_base_addr_write_0:
351 stx %g0, [%g2]
352
353event_que_base_addr_read_0:
354 ldx [%g2], %g4
355 cmp %g4, %g0
356 bne test_failed
357 nop
358
359 ! Event Queue Control Set registers, WO
360
361event_que_ctl_set:
362 setx PCI_E_EV_QUE_CTL_SET_ADDR, %g1, %g2
363 set PCI_E_EV_QUE_CTL_SET_COUNT, %g3
364 set PCI_E_EV_QUE_CTL_SET_STEP, %g4
365
366event_que_ctl_set_write_1:
367 setx 0x100000000000, %g1, %g5 ! First only write the EN bit
368
369event_que_ctl_set_write_en_loop:
370 stx %g5, [%g2]
371 addx %g2, %g4, %g2
372 cmp %g3, 1
373 bne event_que_ctl_set_write_en_loop
374 dec %g3
375
376 setx PCI_E_EV_QUE_CTL_SET_ADDR, %g1, %g2
377 set PCI_E_EV_QUE_CTL_SET_COUNT, %g3
378 setx 0x200000000000000, %g1, %g5 ! Next write the ENOVERR bit
379
380event_que_ctl_set_write_enoverr_loop:
381 stx %g5, [%g2]
382 addx %g2, %g4, %g2
383 cmp %g3, 1
384 bne event_que_ctl_set_write_enoverr_loop
385 dec %g3
386
387 ! Event Queue State registers, RO
388
389event_que_ctl_state:
390 setx PCI_E_EV_QUE_STATE_ADDR, %g1, %g2
391 setx PCI_E_EV_QUE_STATE_COUNT, %g1, %g3
392 setx PCI_E_EV_QUE_STATE_STEP, %g1, %g4
393
394event_que_ctl_state_loop:
395 ldx [%g2], %g5
396 addx %g2, %g4, %g2
397 cmp %g5, 4
398 bne test_failed
399 nop
400
401 cmp %g3, 1
402 bne event_que_ctl_state_loop
403 dec %g3
404
405 ! Event Queue Control Clear registers, WO
406
407event_que_ctl_clear:
408 setx PCI_E_EV_QUE_CTL_CLEAR_ADDR, %g1, %g2
409 setx PCI_E_EV_QUE_CTL_CLEAR_COUNT, %g1, %g3
410 setx PCI_E_EV_QUE_CTL_CLEAR_STEP, %g1, %g4
411 setx 0x200900000000000, %g1, %g5
412
413event_que_ctl_clear_write_loop:
414 stx %g5, [%g2]
415 addx %g2, %g4, %g2
416 cmp %g3, 1
417 bne event_que_ctl_clear_write_loop
418 dec %g3
419
420 ! Event Queue Tail registers
421
422event_que_tail:
423 setx PCI_E_EV_QUE_TAIL_ADDR, %g1, %g2
424 setx PCI_E_EV_QUE_TAIL_COUNT, %g1, %g3
425 setx PCI_E_EV_QUE_TAIL_STEP, %g1, %g4
426
427event_que_tail_write_1:
428 set 0x7f, %g5
429
430event_que_tail_write_1_loop:
431 stx %g5, [%g2]
432 addx %g2, %g4, %g2
433 cmp %g3, 1
434 bne event_que_tail_write_1_loop
435 dec %g3
436
437event_que_tail_read_1:
438 setx PCI_E_EV_QUE_TAIL_ADDR, %g1, %g2
439 setx PCI_E_EV_QUE_TAIL_COUNT, %g1, %g3
440
441event_que_tail_read_1_loop:
442 ldx [%g2], %g7
443 cmp %g7, %g5
444 bne test_failed
445 nop
446
447 addx %g2, %g4, %g2
448 cmp %g3, 1
449 bne event_que_tail_read_1_loop
450 dec %g3
451
452event_que_tail_write_0:
453 setx PCI_E_EV_QUE_TAIL_ADDR, %g1, %g2
454 setx PCI_E_EV_QUE_TAIL_COUNT, %g1, %g3
455
456event_que_tail_write_0_loop:
457 stx %g0, [%g2]
458 addx %g2, %g4, %g2
459 cmp %g3, 1
460 bne event_que_tail_write_0_loop
461 dec %g3
462
463event_que_tail_read_0:
464 setx PCI_E_EV_QUE_TAIL_ADDR, %g1, %g2
465 setx PCI_E_EV_QUE_TAIL_COUNT, %g1, %g3
466
467event_que_tail_read_0_loop:
468 ldx [%g2], %g7
469 cmp %g7, 0
470 bne test_failed
471 nop
472
473 addx %g2, %g4, %g2
474 cmp %g3, 1
475 bne event_que_tail_read_0_loop
476 dec %g3
477
478 ! Event Queue Head registers
479
480event_que_head:
481 setx PCI_E_EV_QUE_HEAD_ADDR, %g1, %g2
482 setx PCI_E_EV_QUE_HEAD_COUNT, %g1, %g3
483 setx PCI_E_EV_QUE_HEAD_STEP, %g1, %g4
484
485event_que_head_write_1:
486 set 0x7f, %g5
487
488event_que_head_write_1_loop:
489 stx %g5, [%g2]
490 addx %g2, %g4, %g2
491 cmp %g3, 1
492 bne event_que_head_write_1_loop
493 dec %g3
494
495event_que_head_read_1:
496 setx PCI_E_EV_QUE_HEAD_ADDR, %g1, %g2
497 setx PCI_E_EV_QUE_HEAD_COUNT, %g1, %g3
498
499event_que_head_read_1_loop:
500 ldx [%g2], %g7
501 cmp %g7, %g5
502 bne test_failed
503 nop
504
505 addx %g2, %g4, %g2
506 cmp %g3, 1
507 bne event_que_head_read_1_loop
508 dec %g3
509
510event_que_head_write_0:
511 setx PCI_E_EV_QUE_HEAD_ADDR, %g1, %g2
512 setx PCI_E_EV_QUE_HEAD_COUNT, %g1, %g3
513
514event_que_head_write_0_loop:
515 stx %g0, [%g2]
516 addx %g2, %g4, %g2
517 cmp %g3, 1
518 bne event_que_head_write_0_loop
519 dec %g3
520
521event_que_head_read_0:
522 setx PCI_E_EV_QUE_HEAD_ADDR, %g1, %g2
523 setx PCI_E_EV_QUE_HEAD_COUNT, %g1, %g3
524
525event_que_head_read_0_loop:
526 ldx [%g2], %g7
527 cmp %g7, 0
528 bne test_failed
529 nop
530
531 addx %g2, %g4, %g2
532 cmp %g3, 1
533 bne event_que_head_read_0_loop
534 dec %g3
535
536 ! MSI Mapping registers
537
538msi_mapping:
539 setx PCI_E_MSI_MAP_ADDR, %g1, %g2
540 setx PCI_E_MSI_MAP_COUNT, %g1, %g3
541 setx PCI_E_MSI_MAP_STEP, %g1, %g4
542
543msi_mapping_write_1:
544 setx 0x800000000000003f, %g1, %g5
545
546msi_mapping_write_1_loop:
547 stx %g5, [%g2]
548 addx %g2, %g4, %g2
549 cmp %g3, 1
550 bne msi_mapping_write_1_loop
551 dec %g3
552
553msi_mapping_read_1:
554 setx PCI_E_MSI_MAP_ADDR, %g1, %g2
555 setx PCI_E_MSI_MAP_COUNT, %g1, %g3
556
557msi_mapping_read_1_loop:
558 ldx [%g2], %g7
559 cmp %g7, %g5
560 addx %g2, %g4, %g2
561 cmp %g3, 1
562 bne msi_mapping_read_1_loop
563 dec %g3
564
565
566msi_mapping_write_0:
567 setx PCI_E_MSI_MAP_ADDR, %g1, %g2
568 setx PCI_E_MSI_MAP_COUNT, %g1, %g3
569 setx PCI_E_MSI_MAP_STEP, %g1, %g4
570
571msi_mapping_write_0_loop:
572 stx %g0, [%g2]
573 addx %g2, %g4, %g2
574 cmp %g3, 1
575 bne msi_mapping_write_0_loop
576 dec %g3
577
578msi_mapping_read_0:
579 setx PCI_E_MSI_MAP_ADDR, %g1, %g2
580 setx PCI_E_MSI_MAP_COUNT, %g1, %g3
581
582msi_mapping_read_0_loop:
583 ldx [%g2], %g7
584 cmp %g7, 0
585 addx %g2, %g4, %g2
586 cmp %g3, 1
587 bne msi_mapping_read_0_loop
588 dec %g3
589
590 ! MSI Clear registers
591
592msi_clear:
593 setx PCI_E_MSI_CLEAR_ADDR, %g1, %g2
594 setx PCI_E_MSI_CLEAR_COUNT, %g1, %g3
595 setx PCI_E_MSI_CLEAR_STEP, %g1, %g4
596
597msi_clear_write_1:
598 setx 0x4000000000000000, %g1, %g5
599
600msi_clear_write_1_loop:
601 stx %g5, [%g2]
602 addx %g2, %g4, %g2
603 cmp %g3, 1
604 bne msi_clear_write_1_loop
605 dec %g3
606
607msi_clear_read_1:
608 setx PCI_E_MSI_CLEAR_ADDR, %g1, %g2
609 setx PCI_E_MSI_CLEAR_COUNT, %g1, %g3
610
611msi_clear_read_1_loop:
612 ldx [%g2], %g7
613 cmp %g7, 0
614 addx %g2, %g4, %g2
615 cmp %g3, 1
616 bne msi_clear_read_1_loop
617 dec %g3
618
619
620msi_clear_write_0:
621 setx PCI_E_MSI_CLEAR_ADDR, %g1, %g2
622 setx PCI_E_MSI_CLEAR_COUNT, %g1, %g3
623 setx PCI_E_MSI_CLEAR_STEP, %g1, %g4
624
625msi_clear_write_0_loop:
626 stx %g0, [%g2]
627 addx %g2, %g4, %g2
628 cmp %g3, 1
629 bne msi_clear_write_0_loop
630 dec %g3
631
632msi_clear_read_0:
633 setx PCI_E_MSI_CLEAR_ADDR, %g1, %g2
634 setx PCI_E_MSI_CLEAR_COUNT, %g1, %g3
635
636msi_clear_read_0_loop:
637 ldx [%g2], %g7
638 cmp %g7, 0
639 addx %g2, %g4, %g2
640 cmp %g3, 1
641 bne msi_clear_read_0_loop
642 dec %g3
643
644 ! Interrupt Mondo Data 0 and 1 registers
645
646intr_mondo_data:
647 setx PCI_E_INT_MONDO_DATA_0_ADDR, %g1, %g2
648 setx PCI_E_INT_MONDO_DATA_1_ADDR, %g1, %g3
649
650intr_mondo_data_write_1:
651 subx %g0, 1, %g7
652 stx %g7, [%g2]
653 stx %g7, [%g3]
654
655intr_mondo_data_read_1:
656 ldx [%g2], %g6
657 andn %g7, 0x3f, %g1
658 cmp %g6, %g1
659 bne test_failed
660 nop
661
662 ldx [%g3], %g5
663 cmp %g5, %g7
664 bne test_failed
665 nop
666
667intr_mondo_data_write_0:
668 stx %g0, [%g2]
669 stx %g0, [%g3]
670
671intr_mondo_data_read_0:
672 ldx [%g2], %g6
673 cmp %g6, 0
674 bne test_failed
675 nop
676
677 ldx [%g3], %g5
678 cmp %g5, 0
679 bne test_failed
680 nop
681
682 ! ERR COR Mapping register
683
684err_cor_map:
685 setx PCI_E_ERR_COR_MAP_ADDR, %g1, %g2
686
687err_cor_map_write_1:
688 subx %g0, 1, %g5
689 stx %g5, [%g2]
690
691err_core_map_read_1:
692 ldx [%g2], %g6
693 setx 0x800000000000003f, %g1, %g7
694 cmp %g6, %g7
695 bne test_failed
696 nop
697
698err_cor_map_write_0:
699 stx %g0, [%g2]
700
701err_cor_map_read_0:
702 ldx [%g2], %g3
703 cmp %g3, 0
704 bne test_failed
705 nop
706
707 ! ERR NONFATAL Mapping register
708
709err_nonfatal_map:
710 setx PCI_E_ERR_NONFATAL_MAP_ADDR, %g1, %g2
711
712err_nonfatal_map_write_1:
713 subx %g0, 1, %g5
714 stx %g5, [%g2]
715
716err_nonfatal_map_read_1:
717 ldx [%g2], %g6
718 setx 0x800000000000003f, %g1, %g7
719 cmp %g6, %g7
720 bne test_failed
721 nop
722
723err_nonfatal_map_write_0:
724 stx %g0, [%g2]
725
726err_nonfatal_map_read_0:
727 ldx [%g2], %g3
728 cmp %g3, 0
729 bne test_failed
730 nop
731
732 ! ERR FATAL Mapping register
733
734err_fatal_map:
735 setx PCI_E_ERR_FATAL_MAP_ADDR, %g1, %g2
736
737err_fatal_map_write_1:
738 subx %g0, 1, %g5
739 stx %g5, [%g2]
740
741err_fatal_map_read_1:
742 ldx [%g2], %g6
743 setx 0x800000000000003f, %g1, %g7
744 cmp %g6, %g7
745 bne test_failed
746 nop
747
748err_fatal_map_write_0:
749 stx %g0, [%g2]
750
751err_fatal_map_read_0:
752 ldx [%g2], %g3
753 cmp %g3, 0
754 bne test_failed
755 nop
756
757 ! PM PME Mapping register
758
759pm_pme_map:
760 setx PCI_E_PM_PME_MAP_ADDR, %g1, %g2
761
762pm_pme_map_write_1:
763 subx %g0, 1, %g5
764 stx %g5, [%g2]
765
766pm_pme_map_read_1:
767 ldx [%g2], %g6
768 setx 0x800000000000003f, %g1, %g7
769 cmp %g6, %g7
770 bne test_failed
771 nop
772
773pm_pme_map_write_0:
774 stx %g0, [%g2]
775
776pm_pme_map_read_0:
777 ldx [%g2], %g3
778 cmp %g3, 0
779 bne test_failed
780 nop
781
782 ! PME To ACK Mapping register
783
784pme_ack_map:
785 setx PCI_E_PME_ACK_MAP_ADDR, %g1, %g2
786
787pme_ack_map_write_1:
788 subx %g0, 1, %g5
789 stx %g5, [%g2]
790
791pme_ack_map_read_1:
792 ldx [%g2], %g6
793 setx 0x800000000000003f, %g1, %g7
794 cmp %g6, %g7
795 bne test_failed
796 nop
797
798pme_ack_map_write_0:
799 stx %g0, [%g2]
800
801pme_ack_map_read_0:
802 ldx [%g2], %g3
803 cmp %g3, 0
804 bne test_failed
805 nop
806
807 ! IMU Interrupt Enable register
808
809imu_int_enable:
810 setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
811
812imu_int_enable_write_1:
813 setx 0x7fff00007fff, %g1, %g3 ! Writeable fields
814 stx %g3, [%g2]
815
816imu_int_enable_read_1:
817 ldx [%g2], %g4
818 cmp %g4, %g3
819 bne test_failed
820 nop
821
822imu_int_enable_write_0:
823 stx %g0, [%g2]
824
825imu_int_enable_read_0:
826 ldx [%g2], %g5
827 cmp %g5, 0
828 bne test_failed
829 nop
830
831 ! IMU Interrupt Status register, RO
832
833imu_int_stat:
834 setx PCI_E_IMU_INT_STAT_ADDR, %g1, %g2
835 ldx [%g2], %g4
836 cmp %g4, 0
837 bne test_failed
838 nop
839
840 ! DMU Core and Block Interrupt Enable register
841
842dmu_int_enable:
843 setx PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
844
845dmu_int_enable_write_1:
846 setx 0xc000000000000003, %g1, %g3
847 stx %g3, [%g2]
848
849dmu_int_enable_read_1:
850 ldx [%g2], %g4
851 cmp %g4, %g3
852 bne test_failed
853 nop
854
855dmu_int_enable_write_0:
856 stx %g0, [%g2]
857
858dmu_int_enable_read_0:
859 ldx [%g2], %g5
860 cmp %g5, 0
861 bne test_failed
862 nop
863
864 ! DMU Core and Block Error Status register, RO
865
866dmu_err_status:
867 setx PCI_E_DMU_ERR_STAT_ADDR, %g1, %g2
868 ldx [%g2], %g1
869 cmp %g1, 0
870 bne test_failed
871 nop
872
873 ! MSI 32-bit Address register
874
875msi_32_addr:
876 setx PCI_E_MSI_32_ADDRESS_ADDR, %g1, %g2
877
878
879msi_32_addr_write_1:
880 subx %g0, 1, %g3
881 stx %g3, [%g2]
882
883msi_32_addr_read_1:
884 ldx [%g2], %g5
885 setx 0xffff0000, %g1, %g4
886 cmp %g5, %g4
887 bne test_failed
888 nop
889
890msi_32_addr_write_0:
891 stx %g0, [%g2]
892
893msi_32_addr_read_0:
894 ldx [%g2], %g1
895 cmp %g1, 0
896 bne test_failed
897 nop
898
899 ! MSI 64-bit Address register
900
901msi_64_addr:
902 setx PCI_E_MSI_64_ADDRESS_ADDR, %g1, %g2
903
904msi_64_addr_write_1:
905 subx %g0, 1, %g3
906 stx %g3, [%g2]
907
908msi_64_addr_read_1:
909 ldx [%g2], %g5
910 setx 0xffffffffffff0000, %g1, %g4
911 cmp %g5, %g4
912 bne test_failed
913 nop
914
915msi_64_addr_write_0:
916 stx %g0, [%g2]
917
918msi_64_addr_read_0:
919 ldx [%g2], %g1
920 cmp %g1, 0
921 bne test_failed
922 nop
923
924 ! MMU Interrupt Enable register
925
926mmu_int_enable:
927 setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
928
929mmu_int_enable_write_1:
930 subx %g0, 1, %g4
931 stx %g4, [%g2]
932
933mmu_int_enable_read_1:
934 ldx [%g2], %g3
935 setx 0x1fffff001fffff, %g1, %g5
936 cmp %g3, %g5
937 bne test_failed
938 nop
939
940mmu_int_enable_write_0:
941 stx %g0, [%g2]
942
943mmu_int_enable_read_0:
944 ldx [%g2], %g3
945 cmp %g3, 0
946 bne test_failed
947 nop
948
949 ! MMU Interrupt Status register, RO
950
951mmu_int_status:
952 setx PCI_E_MMU_INT_STAT_ADDR, %g1, %g2
953 ldx [%g2], %g3
954 cmp %g3, 0
955 bne test_failed
956 nop
957
958 ! MMU Error Status Clear register, RW1C
959
960mmu_error_status:
961 setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
962
963mmu_error_status_write_1:
964 subx %g0, 1, %g5
965 stx %g5, [%g2]
966
967mmu_error_status_read_0:
968 ldx [%g2], %g3
969 cmp %g3, 0
970 bne test_failed
971 nop
972
973 ! MMU Error Status Set register, RW1S
974
975mmu_err_status_set:
976 setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
977
978mmu_err_status_set_write_0:
979 stx %g0, [%g2]
980
981mmu_err_status_set_read_0:
982 ldx [%g2], %g4
983 cmp %g4, 0
984 bne test_failed
985 nop
986
987mmu_err_status_set_write_1:
988 subx %g0, 1, %g1
989 stx %g1, [%g2]
990
991mmu_err_status_set_read_1:
992 ldx [%g2], %g6
993 setx 0x1fffff001fffff, %g1, %g4
994 cmp %g6, %g4
995 bne test_failed
996 nop
997
998 ! MMU Error Status Clear register, RW1C,
999 ! status is set in MMU Error Status Set register above
1000
1001mmu_error_status_2:
1002 setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
1003
1004mmu_error_status_read_1_2:
1005 ldx [%g2], %g6
1006 setx 0x1fffff001fffff, %g1, %g4
1007 cmp %g6, %g4
1008 bne test_failed
1009 nop
1010
1011mmu_error_status_write_1_2:
1012 subx %g0, 1, %g5
1013 stx %g5, [%g2]
1014
1015mmu_error_status_read_0_2:
1016 ldx [%g2], %g3
1017 cmp %g3, 0
1018 bne test_failed
1019 nop
1020
1021 ! ILU Interrupt Enable register
1022
1023ilu_int_enable:
1024 setx PCI_E_ILU_INT_ENB_ADDR, %g1, %g2
1025
1026ilu_int_enable_write_1:
1027 subx %g0, 1, %g4
1028 stx %g4, [%g2]
1029
1030ilu_int_enable_read_1:
1031 ldx [%g2], %g3
1032 setx 0xf0000000f0, %g1, %g5
1033 cmp %g3, %g5
1034 bne test_failed
1035 nop
1036
1037ilu_int_enable_write_0:
1038 stx %g0, [%g2]
1039
1040ilu_int_enable_read_0:
1041 ldx [%g2], %g3
1042 cmp %g3, 0
1043 bne test_failed
1044 nop
1045
1046 ! ILU Interrupt Status register, RO
1047
1048ilu_int_status:
1049 setx PCI_E_ILU_INT_STAT_ADDR, %g1, %g2
1050 ldx [%g2], %g3
1051 cmp %g3, 0
1052 bne test_failed
1053 nop
1054
1055 ! ILU Error Status Clear register, RW1C
1056
1057ilu_error_status:
1058 setx PCI_E_ILU_ERR_STAT_CL_ADDR, %g1, %g2
1059
1060ilu_error_status_write_1:
1061 subx %g0, 1, %g5
1062 stx %g5, [%g2]
1063
1064ilu_error_status_read_0:
1065 ldx [%g2], %g3
1066 cmp %g3, 0
1067 bne test_failed
1068 nop
1069
1070 ! ILU Error Status Set register, RW1S
1071
1072ilu_err_status_set:
1073 setx PCI_E_ILU_ERR_STAT_SET_ADDR, %g1, %g2
1074
1075ilu_err_status_set_write_0:
1076 stx %g0, [%g2]
1077
1078ilu_err_status_set_read_0:
1079 ldx [%g2], %g4
1080 cmp %g4, 0
1081 bne test_failed
1082 nop
1083
1084ilu_err_status_set_write_1:
1085 subx %g0, 1, %g1
1086 stx %g1, [%g2]
1087
1088ilu_err_status_set_read_1:
1089 ldx [%g2], %g6
1090 setx 0xf0000000f0, %g1, %g4
1091 cmp %g6, %g4
1092 bne test_failed
1093 nop
1094
1095 ! ILU Error Status Clear register, RW1C,
1096 ! status is set in ILU Error Status Set register above
1097
1098ilu_error_status_2:
1099 setx PCI_E_ILU_ERR_STAT_CL_ADDR, %g1, %g2
1100
1101ilu_error_status_read_1_2:
1102 ldx [%g2], %g6
1103 setx 0xf0000000f0, %g1, %g4
1104 cmp %g6, %g4
1105 bne test_failed
1106 nop
1107
1108ilu_error_status_write_1_2:
1109 subx %g0, 1, %g5
1110 stx %g5, [%g2]
1111
1112ilu_error_status_read_0_2:
1113 ldx [%g2], %g3
1114 cmp %g3, 0
1115 bne test_failed
1116 nop
1117
1118 ! PEU Core and Block Interrupt Enable register
1119
1120peu_int_enable:
1121 setx PCI_E_PEU_INT_ENB_ADDR, %g1, %g2
1122
1123peu_int_enable_write_1:
1124 setx 0x800000000000000f, %g1, %g3
1125 stx %g3, [%g2]
1126
1127peu_int_enable_read_1:
1128 ldx [%g2], %g4
1129 cmp %g4, %g3
1130 bne test_failed
1131 nop
1132
1133peu_int_enable_write_0:
1134 stx %g0, [%g2]
1135
1136peu_int_enable_read_0:
1137 ldx [%g2], %g5
1138 cmp %g5, 0
1139 bne test_failed
1140 nop
1141
1142 ! PEU Core and Block Error Status register, RO
1143
1144peu_err_status:
1145 setx PCI_E_PEU_INT_STAT_ADDR, %g1, %g2
1146 ldx [%g2], %g1
1147 cmp %g1, 0
1148 bne test_failed
1149 nop
1150
1151 ! PEU Other Interrupt Enable register
1152
1153peu_other_int_enable:
1154 setx PCI_E_PEU_OTHER_INT_ENB_ADDR, %g1, %g2
1155
1156peu_other_int_enable_write_1:
1157 subx %g0, 1, %g4
1158 stx %g4, [%g2]
1159
1160peu_other_int_enable_read_1:
1161 ldx [%g2], %g3
1162 setx 0xffffff00ffffff, %g1, %g5
1163 cmp %g3, %g5
1164 bne test_failed
1165 nop
1166
1167peu_other_int_enable_write_0:
1168 stx %g0, [%g2]
1169
1170peu_other_int_enable_read_0:
1171 ldx [%g2], %g3
1172 cmp %g3, 0
1173 bne test_failed
1174 nop
1175
1176 ! PEU Other Interrupt Status register, RO
1177
1178peu_other_int_status:
1179 setx PCI_E_PEU_OTHER_INT_STAT_ADDR, %g1, %g2
1180 ldx [%g2], %g3
1181 cmp %g3, 0
1182 bne test_failed
1183 nop
1184
1185 ! PEU Other Error Status Clear register, RW1C
1186
1187peu_other_error_status:
1188 setx PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, %g1, %g2
1189
1190peu_other_error_status_write_1:
1191 subx %g0, 1, %g5
1192 stx %g5, [%g2]
1193
1194peu_other_error_status_read_0:
1195 ldx [%g2], %g3
1196 cmp %g3, 0
1197 bne test_failed
1198 nop
1199
1200 ! PEU Other Error Status Set register, RW1S
1201
1202peu_other_err_status_set:
1203 setx PCI_E_PEU_OTHER_ERR_STAT_SET_ADDR, %g1, %g2
1204
1205peu_other_err_status_set_write_0:
1206 stx %g0, [%g2]
1207
1208peu_other_err_status_set_read_0:
1209 ldx [%g2], %g4
1210 cmp %g4, 0
1211 bne test_failed
1212 nop
1213
1214peu_other_err_status_set_write_1:
1215 subx %g0, 1, %g1
1216 stx %g1, [%g2]
1217
1218peu_other_err_status_set_read_1:
1219 ldx [%g2], %g6
1220 setx 0xffffff00ffffff, %g1, %g5
1221 cmp %g6, %g5
1222 bne test_failed
1223 nop
1224
1225 ! PEU Other Error Status Clear register, RW1C,
1226 ! status is set in PEU Other Error Status Set register above
1227
1228peu_other_error_status_2:
1229 setx PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR, %g1, %g2
1230
1231peu_other_error_status_read_1_2:
1232 ldx [%g2], %g6
1233 setx 0xffffff00ffffff, %g1, %g5
1234 cmp %g6, %g5
1235 bne test_failed
1236 nop
1237
1238peu_other_error_status_write_1_2:
1239 subx %g0, 1, %g5
1240 stx %g5, [%g2]
1241
1242peu_other_error_status_read_0_2:
1243 ldx [%g2], %g3
1244 cmp %g3, 0
1245 bne test_failed
1246 nop
1247
1248 ! PEU UE Interrupt Enable register
1249
1250peu_ue_int_enable:
1251 setx PCI_E_PEU_UE_INT_ENB_ADDR, %g1, %g2
1252
1253peu_ue_int_enable_write_1:
1254 subx %g0, 1, %g4
1255 stx %g4, [%g2]
1256
1257peu_ue_int_enable_read_1:
1258 ldx [%g2], %g3
1259 setx 0x001fffff001fffff, %g1, %g5
1260 cmp %g3, %g5
1261 bne test_failed
1262 nop
1263
1264peu_ue_int_enable_write_0:
1265 stx %g0, [%g2]
1266
1267peu_ue_int_enable_read_0:
1268 ldx [%g2], %g3
1269 cmp %g3, 0
1270 bne test_failed
1271 nop
1272
1273 ! PEU UE Interrupt Status register, RO
1274
1275peu_ue_int_status:
1276 setx PCI_E_PEU_UE_INT_STAT_ADDR, %g1, %g2
1277 ldx [%g2], %g3
1278 cmp %g3, 0
1279 bne test_failed
1280 nop
1281
1282 ! PEU UE Status Clear register, RW1C
1283
1284peu_ue_status:
1285 setx PCI_E_PEU_UE_STAT_CL_ADDR, %g1, %g2
1286
1287peu_ue_status_write_1:
1288 subx %g0, 1, %g5
1289 stx %g5, [%g2]
1290
1291peu_ue_status_read_0:
1292 ldx [%g2], %g3
1293 cmp %g3, 0
1294 bne test_failed
1295 nop
1296
1297 ! PEU UE Status Set register, RW1S
1298
1299peu_ue_status_set:
1300 setx PCI_E_PEU_UE_STAT_SET_ADDR, %g1, %g2
1301
1302peu_ue_status_set_write_0:
1303 stx %g0, [%g2]
1304
1305peu_ue_status_set_read_0:
1306 ldx [%g2], %g4
1307 cmp %g4, 0
1308 bne test_failed
1309 nop
1310
1311peu_ue_status_set_write_1:
1312 subx %g0, 1, %g1
1313 stx %g1, [%g2]
1314
1315peu_ue_status_set_read_1:
1316 ldx [%g2], %g6
1317 setx 0x17f0110017f011, %g1, %g5
1318 cmp %g6, %g5
1319 bne test_failed
1320 nop
1321
1322 ! PEU UE Status Clear register, RW1C,
1323 ! status is set in PEU UE Status Set register above
1324
1325peu_ue_status_2:
1326 setx PCI_E_PEU_UE_STAT_CL_ADDR, %g1, %g2
1327
1328peu_ue_status_read_1_2:
1329 ldx [%g2], %g6
1330 setx 0x17f0110017f011, %g1, %g5
1331 cmp %g6, %g5
1332 bne test_failed
1333 nop
1334
1335peu_ue_status_write_1_2:
1336 subx %g0, 1, %g5
1337 stx %g5, [%g2]
1338
1339peu_ue_status_read_0_2:
1340 ldx [%g2], %g3
1341 cmp %g3, 0
1342 bne test_failed
1343 nop
1344
1345 ! PEU CE Interrupt Enable register
1346
1347peu_ce_int_enable:
1348 setx PCI_E_PEU_CE_INT_ENB_ADDR, %g1, %g2
1349
1350peu_ce_int_enable_write_1:
1351 subx %g0, 1, %g4
1352 stx %g4, [%g2]
1353
1354peu_ce_int_enable_read_1:
1355 ldx [%g2], %g3
1356 setx 0x00001fff00001fff, %g1, %g5
1357 cmp %g3, %g5
1358 bne test_failed
1359 nop
1360
1361peu_ce_int_enable_write_0:
1362 stx %g0, [%g2]
1363
1364peu_ce_int_enable_read_0:
1365 ldx [%g2], %g3
1366 cmp %g3, 0
1367 bne test_failed
1368 nop
1369
1370 ! PEU CE Interrupt Status register, RO
1371
1372peu_ce_int_status:
1373 setx PCI_E_PEU_CE_INT_STAT_ADDR, %g1, %g2
1374 ldx [%g2], %g3
1375 cmp %g3, 0
1376 bne test_failed
1377 nop
1378
1379 ! PEU CE Status Clear register, RW1C
1380
1381peu_ce_status:
1382 setx PCI_E_PEU_CE_STAT_CL_ADDR, %g1, %g2
1383
1384peu_ce_status_write_1:
1385 subx %g0, 1, %g5
1386 stx %g5, [%g2]
1387
1388peu_ce_status_read_0:
1389 ldx [%g2], %g3
1390 cmp %g3, 0
1391 bne test_failed
1392 nop
1393
1394 ! PEU CE Status Set register, RW1S
1395
1396peu_ce_status_set:
1397 setx PCI_E_PEU_CE_STAT_SET_ADDR, %g1, %g2
1398
1399peu_ce_status_set_write_0:
1400 stx %g0, [%g2]
1401
1402peu_ce_status_set_read_0:
1403 ldx [%g2], %g4
1404 cmp %g4, 0
1405 bne test_failed
1406 nop
1407
1408peu_ce_status_set_write_1:
1409 subx %g0, 1, %g1
1410 stx %g1, [%g2]
1411
1412peu_ce_status_set_read_1:
1413 ldx [%g2], %g6
1414 setx 0x11c10000000011c1, %g1, %g5
1415 cmp %g6, %g5
1416 bne test_failed
1417 nop
1418
1419 ! PEU CE Status Clear register, RW1C,
1420 ! status is set in PEU CE Status Set register above
1421
1422peu_ce_status_2:
1423 setx PCI_E_PEU_CE_STAT_CL_ADDR, %g1, %g2
1424
1425peu_ce_status_read_1_2:
1426 ldx [%g2], %g6
1427 setx 0x11c10000000011c1, %g1, %g5
1428 cmp %g6, %g5
1429 bne test_failed
1430 nop
1431
1432peu_ce_status_write_1_2:
1433 subx %g0, 1, %g5
1434 stx %g5, [%g2]
1435
1436peu_ce_status_read_0_2:
1437 ldx [%g2], %g3
1438 cmp %g3, 0
1439 bne test_failed
1440 nop
1441
1442 ! PEU DLPL Interrupt Enable register
1443
1444peu_dlpl_int_enable:
1445 setx PCI_E_PEU_DLPL_INT_ENB_ADDR, %g1, %g2
1446
1447peu_dlpl_int_enable_write_1:
1448 subx %g0, 1, %g4
1449 stx %g4, [%g2]
1450
1451peu_dlpl_int_enable_read_1:
1452 ldx [%g2], %g3
1453 setx 0xff03ffff, %g1, %g5
1454 cmp %g3, %g5
1455 bne test_failed
1456 nop
1457
1458peu_dlpl_int_enable_write_0:
1459 stx %g0, [%g2]
1460
1461peu_dlpl_int_enable_read_0:
1462 ldx [%g2], %g3
1463 cmp %g3, 0
1464 bne test_failed
1465 nop
1466
1467 ! PEU DLPL Interrupt Status register, RO
1468
1469peu_dlpl_int_status:
1470 setx PCI_E_PEU_DLPL_INT_STAT_ADDR, %g1, %g2
1471 ldx [%g2], %g3
1472 cmp %g3, 0
1473 bne test_failed
1474 nop
1475
1476 ! PEU DLPL Status Clear register, RW1C
1477
1478peu_dlpl_status:
1479 setx PCI_E_PEU_DLPL_STAT_CL_ADDR, %g1, %g2
1480
1481peu_dlpl_status_write_1:
1482 subx %g0, 1, %g5
1483 stx %g5, [%g2]
1484
1485peu_dlpl_status_read_0:
1486 ldx [%g2], %g3
1487 cmp %g3, 0
1488 bne test_failed
1489 nop
1490
1491 ! PEU DLPL Status Set register, RW1S
1492 ! Note since the link is not being trained some
1493 ! bits in this register can be set. So for the
1494 ! write of zeros just check that the register
1495 ! contents don't change.
1496
1497peu_dlpl_status_set:
1498 setx PCI_E_PEU_DLPL_STAT_SET_ADDR, %g1, %g2
1499 ldx [%g2], %g5
1500
1501peu_dlpl_status_set_write_0:
1502 stx %g0, [%g2]
1503
1504peu_dlpl_status_set_read_0:
1505 ldx [%g2], %g4
1506 cmp %g4, %g5
1507 bne test_failed
1508 nop
1509
1510peu_dlpl_status_set_write_1:
1511 subx %g0, 1, %g1
1512 stx %g1, [%g2]
1513
1514peu_dlpl_status_set_read_1:
1515 ldx [%g2], %g6
1516 setx 0xff03ffff, %g1, %g5
1517 cmp %g6, %g5
1518 bne test_failed
1519 nop
1520
1521 ! PEU DLPL Status Clear register, RW1C,
1522 ! status is set in PEU DLPL Status Set register above
1523
1524peu_dlpl_status_2:
1525 setx PCI_E_PEU_DLPL_STAT_CL_ADDR, %g1, %g2
1526
1527peu_dlpl_status_read_1_2:
1528 ldx [%g2], %g6
1529 setx 0xff03ffff, %g1, %g5
1530 cmp %g6, %g5
1531 bne test_failed
1532 nop
1533
1534peu_dlpl_status_write_1_2:
1535 subx %g0, 1, %g5
1536 stx %g5, [%g2]
1537
1538peu_dlpl_status_read_0_2:
1539 setx 0x4000, %g2, %g7
1540 ldx [%g2], %g3
1541 andn %g3, %g7, %g3
1542 cmp %g3, 0
1543 bne test_failed
1544 nop
1545
1546 ! Done
1547
1548 ba test_passed
1549 nop
1550
1551test_passed:
1552 EXIT_GOOD
1553
1554test_failed:
1555 EXIT_BAD
1556
1557
1558/************************************************************************
1559 Test case data start
1560 ************************************************************************/
1561.data
1562user_data_start:
1563 .word 0x0
1564 .word 0x0
1565user_data_end:
1566.end
Full OpenSPARC design & verification tarball including full HDL.