[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_pci_spurious_error.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: interrupt_pci_spurious_error.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop; 

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"
#include "cmp_macros.h"

	
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	stx	%g0, [%g7]		! Clear this thread's interrupt count
	membar	#Sync

/*      Initialize the NCU for the interrupt.   */

        ! Disable interrupts

no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

        ! Initially set all the Interrupt Management Registers
        ! Not used in this diag, so set vector number to 1, thread to 0.
ncu_init:
        setx    INT_MAN, %g1, %g2       ! %g2 = INT_MAN reg. addr.
        setx    INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
	set	1, %g1

ncu_init_loop_top:
        stx     %g1, [%g2]
        add     %g2, INT_MAN_STEP, %g2
        cmp     %g4, 1
        bne     ncu_init_loop_top
        add     %g4, -1, %g4

	! Initialize Mondo Interrupt Vector Register
	! VECTOR = 63

ncu_mondo_int_vec:
	set	63, %g1
	setx	MONDO_INT_VEC, %g2, %g3
	stx	%g1, [%g3]

	! Clear Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
	setx	MONDO_INT_BUSY, %g1, %g2
	setx	MONDO_INT_BUSY_STEP, %g1, %g3
	setx	MONDO_INT_BUSY_COUNT, %g1, %g4

ncu_mondo_int_busy_loop_top:
	stx	%g0, [%g2]
	add	%g2, %g3, %g2
	cmp	%g4, 1
	bne	ncu_mondo_int_busy_loop_top
	dec	%g4

	! Initialize for error interrupt in PIU
	! First clear error in case one pending.

peu_error_clear:
	setx	PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
	sub	%g0, 1, %g3			! W1C
	stx	%g3, [%g2]

	! Also clear in Interrupt Clear reg.

peu_intr_clear:
	setx	PCI_E_INT_CLEAR_ADDR, %g1, %g2
	setx	PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
	add	%g2, %g4, %g2
	stx	%g0, [%g2]

	! Now enable Mondo 62 in PIU and set destination thread

peu_mondo62_enable:
	setx	PCI_E_INT_MAP_ADDR, %g1, %g7
	setx	PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
	add	%g7, %g3, %g7
	setx	0x80000040, %g1, %g6		! valid = 1, thread id = 0
	stx	%g6, [%g7]			! interrupt controller = 1

	! Enable MMU block mondo 62 interrupts

peu_dmu_error_enable:
	setx	PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
	setx	0x8000000000000002, %g1, %g3	! DMC = 1, MMU = 1
	stx	%g3, [%g2]

	! Enable Bypass access with BE = 0 primary error

peu_mmu_error_enable:
	setx	PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
	set	1, %g3
	stx	%g3, [%g2]

        ! Enable interrupts

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate


        /* Generate the error and therefore the interrupt */

mmu_error_set:
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g3
	stx	%g3, [%g2]

	/* Wait for two interrupts to occur */

intr_wait_2:
	setx	0x800, %g1, %g2		! timeout count
        setx    user_data_start, %g1, %g3

intr_wait_loop_top_2:
	ldx	[%g3], %g5
	cmp	%g5, 2
	be	test_passed
	dec	%g2

	cmp	%g2, 0
	bne	intr_wait_loop_top_2
	nop
	ba	local_test_failed
	nop
	
test_passed:
	EXIT_GOOD

local_test_failed:
	EXIT_BAD


/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global my_trap_code

my_trap_code:

        ! Get the thread id.
        ta      T_RD_THID               ! %o1 = thread id

	! Check Mondo Interrupt Busy reg. for this thread

trap_mondo_busy:
	setx	MONDO_INT_BUSY, %l1, %l2
	setx	MONDO_INT_BUSY_STEP, %l1, %l3
	mulx	%l3, %o1, %l3
	add	%l3, %l2, %l2
	ldx	[%l2], %l4
	and	%l4, 0x40, %l5			! Is busy bit set?
	cmp	%l5, 0
	be	local_test_failed
	nop

	! Check Mondo Interrupt Alias Busy reg.

trap_mondo_abusy:	
	setx	MONDO_INT_ABUSY, %l1, %l2
	ldx	[%l2], %l3
	cmp	%l3, %l4			! ABUSY = BUSY ?
	bne	local_test_failed
	nop

	! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1

trap_mondo_data0:
	setx	MONDO_INT_DATA0, %l1, %l2
	setx	MONDO_INT_DATA0_STEP, %l1, %l3
	mulx	%l3, %o1, %l3
	add	%l3, %l2, %l2
	ldx	[%l2], %l0			! %l0 = mondo_int_busy0

trap_mondo_adata0:
	setx	MONDO_INT_ADATA0, %l1, %l4	! %l5 = mondo_int_abusy0
	ldx	[%l4], %l5			
	cmp	%l5, %l0
	bne	local_test_failed
	nop

trap_mondo_data1:
	setx	MONDO_INT_DATA1, %l1, %l2
	setx	MONDO_INT_DATA1_STEP, %l1, %l3
	mulx	%l3, %o1, %l3
	add	%l3, %l2, %l2
	ldx	[%l2], %l0			! %l0 = mondo_int_busy1

trap_mondo_adata1:
	setx	MONDO_INT_ADATA1, %l1, %l4	! %l5 = mondo_int_abusy1
	ldx	[%l4], %l5			
	cmp	%l5, %l0
	bne	local_test_failed
	nop

	! Check error status in PIU

	! Interrupt Clear reg.

trap_peu_intr_clear:
	setx	PCI_E_INT_CLEAR_ADDR, %l1, %l2
	setx	PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
	add	%l2, %l3, %l2
	ldx	[%l2], %l0
	cmp	%l0, 3			! Should be in pending state
	bne	local_test_failed
	nop

	! MMU Interrupt Status reg.

trap_mmu_intr_status:
	setx	PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
	ldx	[%l2], %l0
	cmp	%l0, 1
	bne	local_test_failed
	nop

	! MMU Error Status Clear reg.

trap_mmu_err_status_clear:
	setx	PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
	ldx	[%l2], %l0
	cmp	%l0, 1
	bne	local_test_failed
	nop

	! All status checking done.

	! Only on second interrupt, clear the error, MMU Error Status Set reg.

trap_intr_check:
	setx	user_data_start, %l2, %l6	! Do not overwrite %l6 !
	ldx	[%l6], %l7			! Do not overwrite %l7 !
	cmp	%l7, 1
	bgt	local_test_failed		! Should only get 2
	nop
	be	trap_piu_mondo_clear
	nop

	! Clear error in MMU Error Status Set reg.

trap_clear_error:
	setx	PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
	stx	%g0, [%l2]
	membar	#Sync
	ldx	[%l2], %g0
	membar	#Sync				! Don't be hasty

	! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.

trap_piu_mondo_clear:
	setx	PCI_E_INT_CLEAR_ADDR, %l0, %l2
	setx	PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
	add	%l2, %l3, %l2
	set	1, %l4
	stx	%l4, [%l2]
	membar	#Sync				! Don't be hasty

	! Clear the mondo interrupt in the NCU

trap_mondo_intr_clear:
	setx	MONDO_INT_ABUSY, %l0, %l1
	stx	%g0, [%l1]
	membar	#Sync

	ldx	[%l1], %l2
	and	%l2, 0x40, %l2
	cmp	%l2, 0			! Busy should be cleared
	bne	local_test_failed
	nop
	membar	#Sync			! Don't be hasty

	! Clear the interrupt in the core

trap_clear_asi_intr_r:	
	ldxa	[%g0]ASI_SWVR_INTR_R, %l5
	cmp	%l5, 63			! check for correct vector number
	bne	local_test_failed
	nop

	! Indicate that the interrupt trap occured

trap_flag:
	inc	%l7
	stx	%l7, [%l6]
	membar	#Sync

	! Done.

trap_done:
	jmpl    %o7+0x8, %g0
	nop


/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
user_data_end:
.end

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: interrupt_pci_spurious_error.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#define H_HT0_Interrupt_0x60
	41	#define My_HT0_Interrupt_0x60 \
	42	call my_trap_code; \
	43	nop; \
	44	retry; \
	45	nop;
	46
	47	#include "hboot.s"
	48	#include "peu_defines.h"
	49	#include "ncu_defines.h"
	50	#include "cmp_macros.h"
	51
	52
	53	/************************************************************************
	54	Test case code start
	55	************************************************************************/
	56	.text
	57	.global main
	58
	59	main:
	60	ta T_CHANGE_HPRIV
	61	nop
	62
	63	stx %g0, [%g7] ! Clear this thread's interrupt count
	64	membar #Sync
65
66	/* Initialize the NCU for the interrupt. */
67
68	! Disable interrupts
69
70	no_intr:
71	rdpr %pstate, %g7
72	xor %g7, 0x2, %g7 ! Reset interrupt enable
73	wrpr %g7, %pstate
74
75	! Initially set all the Interrupt Management Registers
76	! Not used in this diag, so set vector number to 1, thread to 0.
77	ncu_init:
78	setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
79	setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
80	set 1, %g1
81
82	ncu_init_loop_top:
83	stx %g1, [%g2]
84	add %g2, INT_MAN_STEP, %g2
85	cmp %g4, 1
86	bne ncu_init_loop_top
87	add %g4, -1, %g4
88
89	! Initialize Mondo Interrupt Vector Register
90	! VECTOR = 63
91
92	ncu_mondo_int_vec:
93	set 63, %g1
94	setx MONDO_INT_VEC, %g2, %g3
95	stx %g1, [%g3]
96
97	! Clear Mondo Interrupt Busy registers.
98
99	ncu_mondo_int_busy:
100	setx MONDO_INT_BUSY, %g1, %g2
101	setx MONDO_INT_BUSY_STEP, %g1, %g3
102	setx MONDO_INT_BUSY_COUNT, %g1, %g4
103
104	ncu_mondo_int_busy_loop_top:
105	stx %g0, [%g2]
106	add %g2, %g3, %g2
107	cmp %g4, 1
108	bne ncu_mondo_int_busy_loop_top
109	dec %g4
110
111	! Initialize for error interrupt in PIU
112	! First clear error in case one pending.
113
114	peu_error_clear:
115	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
116	sub %g0, 1, %g3 ! W1C
117	stx %g3, [%g2]
118
119	! Also clear in Interrupt Clear reg.
120
121	peu_intr_clear:
122	setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
123	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
124	add %g2, %g4, %g2
125	stx %g0, [%g2]
126
127	! Now enable Mondo 62 in PIU and set destination thread
128
129	peu_mondo62_enable:
130	setx PCI_E_INT_MAP_ADDR, %g1, %g7
131	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
132	add %g7, %g3, %g7
133	setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
134	stx %g6, [%g7] ! interrupt controller = 1
135
136	! Enable MMU block mondo 62 interrupts
137
138	peu_dmu_error_enable:
139	setx PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
140	setx 0x8000000000000002, %g1, %g3 ! DMC = 1, MMU = 1
141	stx %g3, [%g2]
142
143	! Enable Bypass access with BE = 0 primary error
144
145	peu_mmu_error_enable:
146	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
147	set 1, %g3
148	stx %g3, [%g2]
149
150	! Enable interrupts
151
152	yes_intr:
153	rdpr %pstate, %g7
154	or %g7, 0x2, %g7 ! Set interrupt enable
155	wrpr %g7, %pstate
156
157
158	/* Generate the error and therefore the interrupt */
159
160	mmu_error_set:
161	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
162	set 1, %g3
163	stx %g3, [%g2]
164
165	/* Wait for two interrupts to occur */
166
167	intr_wait_2:
168	setx 0x800, %g1, %g2 ! timeout count
169	setx user_data_start, %g1, %g3
170
171	intr_wait_loop_top_2:
172	ldx [%g3], %g5
173	cmp %g5, 2
174	be test_passed
175	dec %g2
176
177	cmp %g2, 0
178	bne intr_wait_loop_top_2
179	nop
180	ba local_test_failed
181	nop
182
183	test_passed:
184	EXIT_GOOD
185
186	local_test_failed:
187	EXIT_BAD
188
189
190	/**********************************************************************
191	Interrupt trap handler.
192	**********************************************************************/
193
194	.global my_trap_code
195
196	my_trap_code:
197
198	! Get the thread id.
199	ta T_RD_THID ! %o1 = thread id
200
201	! Check Mondo Interrupt Busy reg. for this thread
202
203	trap_mondo_busy:
204	setx MONDO_INT_BUSY, %l1, %l2
205	setx MONDO_INT_BUSY_STEP, %l1, %l3
206	mulx %l3, %o1, %l3
207	add %l3, %l2, %l2
208	ldx [%l2], %l4
209	and %l4, 0x40, %l5 ! Is busy bit set?
210	cmp %l5, 0
211	be local_test_failed
212	nop
213
214	! Check Mondo Interrupt Alias Busy reg.
215
216	trap_mondo_abusy:
217	setx MONDO_INT_ABUSY, %l1, %l2
218	ldx [%l2], %l3
219	cmp %l3, %l4 ! ABUSY = BUSY ?
220	bne local_test_failed
221	nop
222
223	! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1
224
225	trap_mondo_data0:
226	setx MONDO_INT_DATA0, %l1, %l2
227	setx MONDO_INT_DATA0_STEP, %l1, %l3
228	mulx %l3, %o1, %l3
229	add %l3, %l2, %l2
230	ldx [%l2], %l0 ! %l0 = mondo_int_busy0
231
232	trap_mondo_adata0:
233	setx MONDO_INT_ADATA0, %l1, %l4 ! %l5 = mondo_int_abusy0
234	ldx [%l4], %l5
235	cmp %l5, %l0
236	bne local_test_failed
237	nop
238
239	trap_mondo_data1:
240	setx MONDO_INT_DATA1, %l1, %l2
241	setx MONDO_INT_DATA1_STEP, %l1, %l3
242	mulx %l3, %o1, %l3
243	add %l3, %l2, %l2
244	ldx [%l2], %l0 ! %l0 = mondo_int_busy1
245
246	trap_mondo_adata1:
247	setx MONDO_INT_ADATA1, %l1, %l4 ! %l5 = mondo_int_abusy1
248	ldx [%l4], %l5
249	cmp %l5, %l0
250	bne local_test_failed
251	nop
252
253	! Check error status in PIU
254
255	! Interrupt Clear reg.
256
257	trap_peu_intr_clear:
258	setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
259	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
260	add %l2, %l3, %l2
261	ldx [%l2], %l0
262	cmp %l0, 3 ! Should be in pending state
263	bne local_test_failed
264	nop
265
266	! MMU Interrupt Status reg.
267
268	trap_mmu_intr_status:
269	setx PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
270	ldx [%l2], %l0
271	cmp %l0, 1
272	bne local_test_failed
273	nop
274
275	! MMU Error Status Clear reg.
276
277	trap_mmu_err_status_clear:
278	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
279	ldx [%l2], %l0
280	cmp %l0, 1
281	bne local_test_failed
282	nop
283
284	! All status checking done.
285
286	! Only on second interrupt, clear the error, MMU Error Status Set reg.
287
288	trap_intr_check:
289	setx user_data_start, %l2, %l6 ! Do not overwrite %l6 !
290	ldx [%l6], %l7 ! Do not overwrite %l7 !
291	cmp %l7, 1
292	bgt local_test_failed ! Should only get 2
293	nop
294	be trap_piu_mondo_clear
295	nop
296
297	! Clear error in MMU Error Status Set reg.
298
299	trap_clear_error:
300	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
301	stx %g0, [%l2]
302	membar #Sync
303	ldx [%l2], %g0
304	membar #Sync ! Don't be hasty
305
306	! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.
307
308	trap_piu_mondo_clear:
309	setx PCI_E_INT_CLEAR_ADDR, %l0, %l2
310	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
311	add %l2, %l3, %l2
312	set 1, %l4
313	stx %l4, [%l2]
314	membar #Sync ! Don't be hasty
315
316	! Clear the mondo interrupt in the NCU
317
318	trap_mondo_intr_clear:
319	setx MONDO_INT_ABUSY, %l0, %l1
320	stx %g0, [%l1]
321	membar #Sync
322
323	ldx [%l1], %l2
324	and %l2, 0x40, %l2
325	cmp %l2, 0 ! Busy should be cleared
326	bne local_test_failed
327	nop
328	membar #Sync ! Don't be hasty
329
330	! Clear the interrupt in the core
331
332	trap_clear_asi_intr_r:
333	ldxa [%g0]ASI_SWVR_INTR_R, %l5
334	cmp %l5, 63 ! check for correct vector number
335	bne local_test_failed
336	nop
337
338	! Indicate that the interrupt trap occured
339
340	trap_flag:
341	inc %l7
342	stx %l7, [%l6]
343	membar #Sync
344
345	! Done.
346
347	trap_done:
348	jmpl %o7+0x8, %g0
349	nop
350
351
352
353	/************************************************************************
354	Test case data start
355	************************************************************************/
356
357	.align 1024
358	.data
359	user_data_start:
360	.word 0xffffffff
361	.word 0xffffffff
362	.word 0xffffffff
363	.word 0xffffffff
364	user_data_end:
365	.end
366
367	/************************************************************************/