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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / l2 / allcores_allbanks.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: allcores_allbanks.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40
41#define TEST_DATA1 0x5555555555555555
42#define L2_ENTRY_PA0 0x2020000008
43#define L2_ES_W1C_VALUE 0xc03ffff800000000
44#define SPARC_ES_W1C_VALUE 0xefffffff
45#define TT_SW_Error 0x40
46
47#include "hboot.s"
48#include "asi_s.h"
49#include "err_defines.h"
50
51
52
53#define MAIN_PAGE_NUCLEUS_ALSO
54
55
56/************************************************************************
57 Test case code start
58 ************************************************************************/
59
60.text
61.global main
62
63main:
64 ta T_CHANGE_HPRIV
65
66 ! Initialize the global registers.
67 mov %g0, %g1
68 mov %g0, %g2
69 mov %g0, %g3
70 mov %g0, %g4
71 mov %g0, %g5
72 mov %g0, %g6
73 mov %g0, %g7
74
75 ! Set up seperate result data area for each core.
76 ta T_RD_THID
77 mov %o1, %l6
78 umul %l6, 64, %l7
79 setx result_area, %g1, %g3
80 add %l7, %g3, %l7
81
82 ! All threads use the same code.
83
84disable_l1_DCache:
85 ldxa [%g0] ASI_LSU_CONTROL, %l0
86 ! Remove bit 2
87 andn %l0, 0x2, %l0
88 stxa %l0, [%g0] ASI_LSU_CONTROL
89
90
91clear_l2_ESR:
92 setx L2_ES_W1C_VALUE, %l0, %l1
93 setx L2ES_PA0, %l6, %g1
94 stx %l1, [%g1]
95
96
97set_L2_Directly_Mapped_Mode:
98 setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
99 mov 0x2, %l0
100 stx %l0, [%g1]
101
102store_to_L2:
103 setx TEST_DATA1, %l0, %g5
104
105store_to_L2_Bank0:
106 setx 0x20000000, %l0, %g2 ! bits [8:6] select Bank
107 stx %g5, [%g2]
108 stx %g5, [%g2+8]
109 membar #Sync
110 ldx [%g2], %g3
111 ldx [%g2+8], %g4
112 membar #Sync
113 cmp %g4,%g5
114 bne test_fail
115 nop
116
117store_to_L2_Bank1:
118 setx 0x20000040, %l0, %g2 ! bits [8:6] select Bank
119 stx %g5, [%g2]
120 stx %g5, [%g2+8]
121 membar #Sync
122 ldx [%g2], %g3
123 ldx [%g2+8], %g4
124 membar #Sync
125 cmp %g4,%g5
126 bne test_fail
127 nop
128
129store_to_L2_Bank2:
130 setx 0x20000080, %l0, %g2 ! bits [8:6] select Bank
131 stx %g5, [%g2]
132 stx %g5, [%g2+8]
133 membar #Sync
134 ldx [%g2], %g3
135 ldx [%g2+8], %g4
136 membar #Sync
137 cmp %g4,%g5
138 bne test_fail
139 nop
140
141store_to_L2_Bank3:
142 setx 0x200000c0, %l0, %g2 ! bits [8:6] select Bank
143 stx %g5, [%g2]
144 stx %g5, [%g2+8]
145 membar #Sync
146 ldx [%g2], %g3
147 ldx [%g2+8], %g4
148 membar #Sync
149 cmp %g4,%g5
150 bne test_fail
151 nop
152
153store_to_L2_Bank4:
154 setx 0x20000100, %l0, %g2 ! bits [8:6] select Bank
155 stx %g5, [%g2]
156 stx %g5, [%g2+8]
157 membar #Sync
158 ldx [%g2], %g3
159 ldx [%g2+8], %g4
160 membar #Sync
161 cmp %g4,%g5
162 bne test_fail
163 nop
164
165store_to_L2_Bank5:
166 setx 0x20000140, %l0, %g2 ! bits [8:6] select Bank
167 stx %g5, [%g2]
168 stx %g5, [%g2+8]
169 membar #Sync
170 ldx [%g2], %g3
171 ldx [%g2+8], %g4
172 membar #Sync
173 cmp %g4,%g5
174 bne test_fail
175 nop
176
177store_to_L2_Bank6:
178 setx 0x20000180, %l0, %g2 ! bits [8:6] select Bank
179 stx %g5, [%g2]
180 stx %g5, [%g2+8]
181 membar #Sync
182 ldx [%g2], %g3
183 ldx [%g2+8], %g4
184 membar #Sync
185 cmp %g4,%g5
186 bne test_fail
187 nop
188
189store_to_L2_Bank7:
190 setx 0x200001c0, %l0, %g2 ! bits [8:6] select Bank
191 stx %g5, [%g2]
192 stx %g5, [%g2+8]
193 membar #Sync
194 ldx [%g2], %g3
195 ldx [%g2+8], %g4
196 membar #Sync
197 cmp %g4,%g5
198 bne test_fail
199 nop
200
201
202ba test_pass
203nop
204
205
206
207/*******************************************************
208 * Exit code
209 *******************************************************/
210
211test_pass:
212ta T_GOOD_TRAP
213
214test_fail:
215ta T_BAD_TRAP
216nop
217
218
219user_text_end:
220
221
222/************************************************************************
223 * Test case data start
224 ************************************************************************/
225
226SECTION .DATA DATA_VA=0x70000000
227attr_data {
228 Name = .DATA,
229 hypervisor,
230 compressimage
231}
232
233.data
234.global result_area
235.global alias1
236.global alias2
237.global alias3
238.global alias4
239.global alias5
240.global alias6
241.global alias7
242.global alias8
243.global alias9
244.global alias10
245.global alias11
246.global alias12
247.global alias13
248.global alias14
249.global alias15
250.global alias16
251
252user_data_start:
253result_area:
254 .skip 512 ! 64 bytes per core
255
256 .align 0x40000 ! each 246kb, 0x40000, aliases to same L2$ line
257alias1:
258 .skip 1024
259 .align 0x40000
260alias2:
261 .skip 1024
262 .align 0x40000
263alias3:
264 .skip 1024
265 .align 0x40000
266alias4:
267 .skip 1024
268 .align 0x40000
269alias5:
270 .skip 1024
271 .align 0x40000
272alias6:
273 .skip 1024
274 .align 0x40000
275alias7:
276 .skip 1024
277 .align 0x40000
278alias8:
279 .skip 1024
280 .align 0x40000
281alias9:
282 .skip 1024
283 .align 0x40000
284alias10:
285 .skip 1024
286 .align 0x40000
287alias11:
288 .skip 1024
289 .align 0x40000
290alias12:
291 .skip 1024
292 .align 0x40000
293alias13:
294 .skip 1024
295 .align 0x40000
296alias14:
297 .skip 1024
298 .align 0x40000
299alias15:
300 .skip 1024
301 .align 0x40000
302alias16:
303 .skip 1024
304
305user_data_end:
306.end
Full OpenSPARC design & verification tarball including full HDL.