projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: n2_pm_all_dimm_rdwr_5.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
| 39 | #define MAIN_PAGE_HV_ALSO | |
| 40 | ||
| 41 | ||
| 42 | #include "hboot.s" | |
| 43 | #include "asi_s.h" | |
| 44 | ||
| 45 | #ifdef PM_8BANK | |
| 46 | #define L20_MCU_DM0_BK0 0x0000134000 | |
| 47 | #define L20_MCU_DM0_BK2 0x0000134200 | |
| 48 | #define L20_MCU_DM0_BK4 0x0000134400 | |
| 49 | #define L20_MCU_DM0_BK6 0x0000134600 | |
| 50 | ||
| 51 | #define L20_MCU_DM1_BK0 0x0800134000 | |
| 52 | #define L20_MCU_DM1_BK2 0x0800134200 | |
| 53 | #define L20_MCU_DM1_BK4 0x0800134400 | |
| 54 | #define L20_MCU_DM1_BK6 0x0800134600 | |
| 55 | ||
| 56 | #define L20_MCU_DM2_BK0 0x1000134000 | |
| 57 | #define L20_MCU_DM2_BK2 0x1000134200 | |
| 58 | #define L20_MCU_DM2_BK4 0x1000134400 | |
| 59 | #define L20_MCU_DM2_BK6 0x1000134600 | |
| 60 | ||
| 61 | #define L20_MCU_DM3_BK0 0x1800134000 | |
| 62 | #define L20_MCU_DM3_BK2 0x1800134200 | |
| 63 | #define L20_MCU_DM3_BK4 0x1800134400 | |
| 64 | #define L20_MCU_DM3_BK6 0x1800134600 | |
| 65 | ||
| 66 | #define L20_MCU_DM4_BK0 0x2000134000 | |
| 67 | #define L20_MCU_DM4_BK2 0x2000134200 | |
| 68 | #define L20_MCU_DM4_BK4 0x2000134400 | |
| 69 | #define L20_MCU_DM4_BK6 0x2000134600 | |
| 70 | ||
| 71 | #define L20_MCU_DM5_BK0 0x2800134000 | |
| 72 | #define L20_MCU_DM5_BK2 0x2800134200 | |
| 73 | #define L20_MCU_DM5_BK4 0x2800134400 | |
| 74 | #define L20_MCU_DM5_BK6 0x2800134600 | |
| 75 | ||
| 76 | #define L20_MCU_DM6_BK0 0x3000134000 | |
| 77 | #define L20_MCU_DM6_BK2 0x3000134200 | |
| 78 | #define L20_MCU_DM6_BK4 0x3000134400 | |
| 79 | #define L20_MCU_DM6_BK6 0x3000134600 | |
| 80 | ||
| 81 | #define L20_MCU_DM7_BK0 0x3800134000 | |
| 82 | #define L20_MCU_DM7_BK2 0x3800134200 | |
| 83 | #define L20_MCU_DM7_BK4 0x3800134400 | |
| 84 | #define L20_MCU_DM7_BK6 0x3800134600 | |
| 85 | ||
| 86 | #define L2_1_MCU_DM0_BK1 0x0000134040 | |
| 87 | #define L2_1_MCU_DM0_BK3 0x0000134240 | |
| 88 | #define L2_1_MCU_DM0_BK5 0x0000134440 | |
| 89 | #define L2_1_MCU_DM0_BK7 0x0000134640 | |
| 90 | ||
| 91 | #define L2_1_MCU_DM1_BK1 0x0800134040 | |
| 92 | #define L2_1_MCU_DM1_BK3 0x0800134240 | |
| 93 | #define L2_1_MCU_DM1_BK5 0x0800134440 | |
| 94 | #define L2_1_MCU_DM1_BK7 0x0800134640 | |
| 95 | ||
| 96 | #define L2_1_MCU_DM2_BK1 0x1000134040 | |
| 97 | #define L2_1_MCU_DM2_BK3 0x1000134240 | |
| 98 | #define L2_1_MCU_DM2_BK5 0x1000134440 | |
| 99 | #define L2_1_MCU_DM2_BK7 0x1000134640 | |
| 100 | ||
| 101 | #define L2_1_MCU_DM3_BK1 0x1800134040 | |
| 102 | #define L2_1_MCU_DM3_BK3 0x1800134240 | |
| 103 | #define L2_1_MCU_DM3_BK5 0x1800134440 | |
| 104 | #define L2_1_MCU_DM3_BK7 0x1800134640 | |
| 105 | ||
| 106 | #define L2_1_MCU_DM4_BK1 0x2000134040 | |
| 107 | #define L2_1_MCU_DM4_BK3 0x2000134240 | |
| 108 | #define L2_1_MCU_DM4_BK5 0x2000134440 | |
| 109 | #define L2_1_MCU_DM4_BK7 0x2000134640 | |
| 110 | ||
| 111 | #define L2_1_MCU_DM5_BK1 0x2800134040 | |
| 112 | #define L2_1_MCU_DM5_BK3 0x2800134240 | |
| 113 | #define L2_1_MCU_DM5_BK5 0x2800134440 | |
| 114 | #define L2_1_MCU_DM5_BK7 0x2800134640 | |
| 115 | ||
| 116 | #define L2_1_MCU_DM6_BK1 0x3000134040 | |
| 117 | #define L2_1_MCU_DM6_BK3 0x3000134240 | |
| 118 | #define L2_1_MCU_DM6_BK5 0x3000134440 | |
| 119 | #define L2_1_MCU_DM6_BK7 0x3000134640 | |
| 120 | ||
| 121 | #define L2_1_MCU_DM7_BK1 0x3800134040 | |
| 122 | #define L2_1_MCU_DM7_BK3 0x3800134240 | |
| 123 | #define L2_1_MCU_DM7_BK5 0x3800134440 | |
| 124 | #define L2_1_MCU_DM7_BK7 0x3800134640 | |
| 125 | #endif | |
| 126 | ||
| 127 | #ifdef PM_4BANK | |
| 128 | #define L20_MCU_DM0_BK0 0x0000134000 | |
| 129 | #define L20_MCU_DM0_BK2 0x0000134100 | |
| 130 | #define L20_MCU_DM0_BK4 0x0000134200 | |
| 131 | #define L20_MCU_DM0_BK6 0x0000134300 | |
| 132 | ||
| 133 | #define L20_MCU_DM1_BK0 0x0400134000 | |
| 134 | #define L20_MCU_DM1_BK2 0x0400134100 | |
| 135 | #define L20_MCU_DM1_BK4 0x0400134200 | |
| 136 | #define L20_MCU_DM1_BK6 0x0400134300 | |
| 137 | ||
| 138 | #define L20_MCU_DM2_BK0 0x0800134000 | |
| 139 | #define L20_MCU_DM2_BK2 0x0800134100 | |
| 140 | #define L20_MCU_DM2_BK4 0x0800134200 | |
| 141 | #define L20_MCU_DM2_BK6 0x0800134300 | |
| 142 | ||
| 143 | #define L20_MCU_DM3_BK0 0x0c00134000 | |
| 144 | #define L20_MCU_DM3_BK2 0x0c00134100 | |
| 145 | #define L20_MCU_DM3_BK4 0x0c00134200 | |
| 146 | #define L20_MCU_DM3_BK6 0x0c00134300 | |
| 147 | ||
| 148 | #define L20_MCU_DM4_BK0 0x1000134000 | |
| 149 | #define L20_MCU_DM4_BK2 0x1000134100 | |
| 150 | #define L20_MCU_DM4_BK4 0x1000134200 | |
| 151 | #define L20_MCU_DM4_BK6 0x1000134300 | |
| 152 | ||
| 153 | #define L20_MCU_DM5_BK0 0x1400134000 | |
| 154 | #define L20_MCU_DM5_BK2 0x1400134100 | |
| 155 | #define L20_MCU_DM5_BK4 0x1400134200 | |
| 156 | #define L20_MCU_DM5_BK6 0x1400134300 | |
| 157 | ||
| 158 | #define L20_MCU_DM6_BK0 0x1800134000 | |
| 159 | #define L20_MCU_DM6_BK2 0x1800134100 | |
| 160 | #define L20_MCU_DM6_BK4 0x1800134200 | |
| 161 | #define L20_MCU_DM6_BK6 0x1800134300 | |
| 162 | ||
| 163 | #define L20_MCU_DM7_BK0 0x1c00134000 | |
| 164 | #define L20_MCU_DM7_BK2 0x1c00134100 | |
| 165 | #define L20_MCU_DM7_BK4 0x1c00134200 | |
| 166 | #define L20_MCU_DM7_BK6 0x1c00134300 | |
| 167 | ||
| 168 | #define L2_1_MCU_DM0_BK1 0x0000134040 | |
| 169 | #define L2_1_MCU_DM0_BK3 0x0000134140 | |
| 170 | #define L2_1_MCU_DM0_BK5 0x0000134240 | |
| 171 | #define L2_1_MCU_DM0_BK7 0x0000134340 | |
| 172 | ||
| 173 | #define L2_1_MCU_DM1_BK1 0x0400134040 | |
| 174 | #define L2_1_MCU_DM1_BK3 0x0400134140 | |
| 175 | #define L2_1_MCU_DM1_BK5 0x0400134240 | |
| 176 | #define L2_1_MCU_DM1_BK7 0x0400134340 | |
| 177 | ||
| 178 | #define L2_1_MCU_DM2_BK1 0x0800134040 | |
| 179 | #define L2_1_MCU_DM2_BK3 0x0800134140 | |
| 180 | #define L2_1_MCU_DM2_BK5 0x0800134240 | |
| 181 | #define L2_1_MCU_DM2_BK7 0x0800134340 | |
| 182 | ||
| 183 | #define L2_1_MCU_DM3_BK1 0x0c00134040 | |
| 184 | #define L2_1_MCU_DM3_BK3 0x0c00134140 | |
| 185 | #define L2_1_MCU_DM3_BK5 0x0c00134240 | |
| 186 | #define L2_1_MCU_DM3_BK7 0x0c00134340 | |
| 187 | ||
| 188 | #define L2_1_MCU_DM4_BK1 0x1000134040 | |
| 189 | #define L2_1_MCU_DM4_BK3 0x1000134140 | |
| 190 | #define L2_1_MCU_DM4_BK5 0x1000134240 | |
| 191 | #define L2_1_MCU_DM4_BK7 0x1000134340 | |
| 192 | ||
| 193 | #define L2_1_MCU_DM5_BK1 0x1400134040 | |
| 194 | #define L2_1_MCU_DM5_BK3 0x1400134140 | |
| 195 | #define L2_1_MCU_DM5_BK5 0x1400134240 | |
| 196 | #define L2_1_MCU_DM5_BK7 0x1400134340 | |
| 197 | ||
| 198 | #define L2_1_MCU_DM6_BK1 0x1800134040 | |
| 199 | #define L2_1_MCU_DM6_BK3 0x1800134140 | |
| 200 | #define L2_1_MCU_DM6_BK5 0x1800134240 | |
| 201 | #define L2_1_MCU_DM6_BK7 0x1800134340 | |
| 202 | ||
| 203 | #define L2_1_MCU_DM7_BK1 0x1c00134040 | |
| 204 | #define L2_1_MCU_DM7_BK3 0x1c00134140 | |
| 205 | #define L2_1_MCU_DM7_BK5 0x1c00134240 | |
| 206 | #define L2_1_MCU_DM7_BK7 0x1c00134340 | |
| 207 | #endif | |
| 208 | ||
| 209 | ||
| 210 | ||
| 211 | #ifdef PM_2BANK | |
| 212 | #define L20_MCU_DM0_BK0 0x0000134000 | |
| 213 | #define L20_MCU_DM0_BK2 0x0000134080 | |
| 214 | #define L20_MCU_DM0_BK4 0x0000134100 | |
| 215 | #define L20_MCU_DM0_BK6 0x0000134180 | |
| 216 | ||
| 217 | #define L20_MCU_DM1_BK0 0x0200134000 | |
| 218 | #define L20_MCU_DM1_BK2 0x0200134080 | |
| 219 | #define L20_MCU_DM1_BK4 0x0200134100 | |
| 220 | #define L20_MCU_DM1_BK6 0x0200134180 | |
| 221 | ||
| 222 | #define L20_MCU_DM2_BK0 0x0400134000 | |
| 223 | #define L20_MCU_DM2_BK2 0x0400134080 | |
| 224 | #define L20_MCU_DM2_BK4 0x0400134100 | |
| 225 | #define L20_MCU_DM2_BK6 0x0400134180 | |
| 226 | ||
| 227 | #define L20_MCU_DM3_BK0 0x0600134000 | |
| 228 | #define L20_MCU_DM3_BK2 0x0600134080 | |
| 229 | #define L20_MCU_DM3_BK4 0x0600134100 | |
| 230 | #define L20_MCU_DM3_BK6 0x0600134180 | |
| 231 | ||
| 232 | #define L20_MCU_DM4_BK0 0x0800134000 | |
| 233 | #define L20_MCU_DM4_BK2 0x0800134080 | |
| 234 | #define L20_MCU_DM4_BK4 0x0800134100 | |
| 235 | #define L20_MCU_DM4_BK6 0x0800134180 | |
| 236 | ||
| 237 | #define L20_MCU_DM5_BK0 0x0a00134000 | |
| 238 | #define L20_MCU_DM5_BK2 0x0a00134080 | |
| 239 | #define L20_MCU_DM5_BK4 0x0a00134100 | |
| 240 | #define L20_MCU_DM5_BK6 0x0a00134180 | |
| 241 | ||
| 242 | #define L20_MCU_DM6_BK0 0x0c00134000 | |
| 243 | #define L20_MCU_DM6_BK2 0x0c00134080 | |
| 244 | #define L20_MCU_DM6_BK4 0x0c00134100 | |
| 245 | #define L20_MCU_DM6_BK6 0x0c00134180 | |
| 246 | ||
| 247 | #define L20_MCU_DM7_BK0 0x0e00134000 | |
| 248 | #define L20_MCU_DM7_BK2 0x0e00134080 | |
| 249 | #define L20_MCU_DM7_BK4 0x0e00134100 | |
| 250 | #define L20_MCU_DM7_BK6 0x0e00134180 | |
| 251 | ||
| 252 | ||
| 253 | #define L2_1_MCU_DM0_BK1 0x0000134040 | |
| 254 | #define L2_1_MCU_DM0_BK3 0x00001340c0 | |
| 255 | #define L2_1_MCU_DM0_BK5 0x0000134140 | |
| 256 | #define L2_1_MCU_DM0_BK7 0x00001341c0 | |
| 257 | ||
| 258 | #define L2_1_MCU_DM1_BK1 0x0200134040 | |
| 259 | #define L2_1_MCU_DM1_BK3 0x02001340c0 | |
| 260 | #define L2_1_MCU_DM1_BK5 0x0200134140 | |
| 261 | #define L2_1_MCU_DM1_BK7 0x02001341c0 | |
| 262 | ||
| 263 | #define L2_1_MCU_DM2_BK1 0x0400134040 | |
| 264 | #define L2_1_MCU_DM2_BK3 0x04001340c0 | |
| 265 | #define L2_1_MCU_DM2_BK5 0x0400134140 | |
| 266 | #define L2_1_MCU_DM2_BK7 0x04001341c0 | |
| 267 | ||
| 268 | #define L2_1_MCU_DM3_BK1 0x0600134040 | |
| 269 | #define L2_1_MCU_DM3_BK3 0x06001340c0 | |
| 270 | #define L2_1_MCU_DM3_BK5 0x0600134140 | |
| 271 | #define L2_1_MCU_DM3_BK7 0x06001341c0 | |
| 272 | ||
| 273 | #define L2_1_MCU_DM4_BK1 0x0800134040 | |
| 274 | #define L2_1_MCU_DM4_BK3 0x08001340c0 | |
| 275 | #define L2_1_MCU_DM4_BK5 0x0800134140 | |
| 276 | #define L2_1_MCU_DM4_BK7 0x08001341c0 | |
| 277 | ||
| 278 | #define L2_1_MCU_DM5_BK1 0x0a00134040 | |
| 279 | #define L2_1_MCU_DM5_BK3 0x0a001340c0 | |
| 280 | #define L2_1_MCU_DM5_BK5 0x0a00134140 | |
| 281 | #define L2_1_MCU_DM5_BK7 0x0a001341c0 | |
| 282 | ||
| 283 | #define L2_1_MCU_DM6_BK1 0x0c00134040 | |
| 284 | #define L2_1_MCU_DM6_BK3 0x0c001340c0 | |
| 285 | #define L2_1_MCU_DM6_BK5 0x0c00134140 | |
| 286 | #define L2_1_MCU_DM6_BK7 0x0c001341c0 | |
| 287 | ||
| 288 | #define L2_1_MCU_DM7_BK1 0x0e00134040 | |
| 289 | #define L2_1_MCU_DM7_BK3 0x0e001340c0 | |
| 290 | #define L2_1_MCU_DM7_BK5 0x0e00134140 | |
| 291 | #define L2_1_MCU_DM7_BK7 0x0e001341c0 | |
| 292 | #endif | |
| 293 | ||
| 294 | #ifdef L2_OFF | |
| 295 | #define L2_ON_OFF_DM 0x1 | |
| 296 | #else | |
| 297 | #define L2_ON_OFF_DM 0x0 | |
| 298 | #endif | |
| 299 | ||
| 300 | ||
| 301 | .text | |
| 302 | .global main | |
| 303 | ||
| 304 | ||
| 305 | main: | |
| 306 | ta T_CHANGE_HPRIV | |
| 307 | nop | |
| 308 | ||
| 309 | membar #Sync | |
| 310 | ||
| 311 | ta T_RD_THID | |
| 312 | ||
| 313 | ! Preserve Thread id in %g4 left shifted 28 bits | |
| 314 | sllx %o1, 24, %g4 | |
| 315 | nop | |
| 316 | ||
| 317 | branch_th: | |
| 318 | ! Core0 | |
| 319 | cmp %o1, 0x0 | |
| 320 | be main_bank0 | |
| 321 | nop | |
| 322 | ||
| 323 | cmp %o1, 0x1 | |
| 324 | be main_bank1 | |
| 325 | nop | |
| 326 | ||
| 327 | cmp %o1, 0x2 | |
| 328 | be main_bank0 | |
| 329 | nop | |
| 330 | ||
| 331 | cmp %o1, 0x3 | |
| 332 | be main_bank1 | |
| 333 | nop | |
| 334 | ||
| 335 | cmp %o1, 0x4 | |
| 336 | be main_bank0 | |
| 337 | nop | |
| 338 | ||
| 339 | cmp %o1, 0x5 | |
| 340 | be main_bank1 | |
| 341 | nop | |
| 342 | ||
| 343 | cmp %o1, 0x6 | |
| 344 | be main_bank0 | |
| 345 | nop | |
| 346 | ||
| 347 | cmp %o1, 0x7 | |
| 348 | be main_bank1 | |
| 349 | nop | |
| 350 | ||
| 351 | ! Core1 | |
| 352 | cmp %o1, 0x8 | |
| 353 | be main_bank0 | |
| 354 | nop | |
| 355 | ||
| 356 | cmp %o1, 0x9 | |
| 357 | be main_bank1 | |
| 358 | nop | |
| 359 | ||
| 360 | cmp %o1, 0xa | |
| 361 | be main_bank0 | |
| 362 | nop | |
| 363 | ||
| 364 | cmp %o1, 0xb | |
| 365 | be main_bank1 | |
| 366 | nop | |
| 367 | ||
| 368 | cmp %o1, 0xc | |
| 369 | be main_bank0 | |
| 370 | nop | |
| 371 | ||
| 372 | cmp %o1, 0xd | |
| 373 | be main_bank1 | |
| 374 | nop | |
| 375 | ||
| 376 | cmp %o1, 0xe | |
| 377 | be main_bank0 | |
| 378 | nop | |
| 379 | ||
| 380 | cmp %o1, 0xf | |
| 381 | be main_bank1 | |
| 382 | nop | |
| 383 | ||
| 384 | ! Core2 | |
| 385 | cmp %o1, 0x10 | |
| 386 | be main_bank0 | |
| 387 | nop | |
| 388 | ||
| 389 | cmp %o1, 0x11 | |
| 390 | be main_bank1 | |
| 391 | nop | |
| 392 | ||
| 393 | cmp %o1, 0x12 | |
| 394 | be main_bank0 | |
| 395 | nop | |
| 396 | ||
| 397 | cmp %o1, 0x13 | |
| 398 | be main_bank1 | |
| 399 | nop | |
| 400 | ||
| 401 | cmp %o1, 0x14 | |
| 402 | be main_bank0 | |
| 403 | nop | |
| 404 | ||
| 405 | cmp %o1, 0x15 | |
| 406 | be main_bank1 | |
| 407 | nop | |
| 408 | ||
| 409 | cmp %o1, 0x16 | |
| 410 | be main_bank0 | |
| 411 | nop | |
| 412 | ||
| 413 | cmp %o1, 0x17 | |
| 414 | be main_bank1 | |
| 415 | nop | |
| 416 | ||
| 417 | ||
| 418 | ! Core3 | |
| 419 | cmp %o1, 0x18 | |
| 420 | be main_bank0 | |
| 421 | nop | |
| 422 | ||
| 423 | cmp %o1, 0x19 | |
| 424 | be main_bank1 | |
| 425 | nop | |
| 426 | ||
| 427 | cmp %o1, 0x1a | |
| 428 | be main_bank0 | |
| 429 | nop | |
| 430 | ||
| 431 | cmp %o1, 0x1b | |
| 432 | be main_bank1 | |
| 433 | nop | |
| 434 | ||
| 435 | cmp %o1, 0x1c | |
| 436 | be main_bank0 | |
| 437 | nop | |
| 438 | ||
| 439 | cmp %o1, 0x1d | |
| 440 | be main_bank1 | |
| 441 | nop | |
| 442 | ||
| 443 | cmp %o1, 0x1e | |
| 444 | be main_bank0 | |
| 445 | nop | |
| 446 | ||
| 447 | cmp %o1, 0x1f | |
| 448 | be main_bank1 | |
| 449 | nop | |
| 450 | ||
| 451 | ! Core4 | |
| 452 | cmp %o1, 0x20 | |
| 453 | be main_bank0 | |
| 454 | nop | |
| 455 | ||
| 456 | cmp %o1, 0x21 | |
| 457 | be main_bank1 | |
| 458 | nop | |
| 459 | ||
| 460 | cmp %o1, 0x22 | |
| 461 | be main_bank0 | |
| 462 | nop | |
| 463 | ||
| 464 | cmp %o1, 0x23 | |
| 465 | be main_bank1 | |
| 466 | nop | |
| 467 | ||
| 468 | cmp %o1, 0x24 | |
| 469 | be main_bank0 | |
| 470 | nop | |
| 471 | ||
| 472 | cmp %o1, 0x25 | |
| 473 | be main_bank1 | |
| 474 | nop | |
| 475 | ||
| 476 | cmp %o1, 0x26 | |
| 477 | be main_bank0 | |
| 478 | nop | |
| 479 | ||
| 480 | cmp %o1, 0x27 | |
| 481 | be main_bank1 | |
| 482 | nop | |
| 483 | ||
| 484 | ! Core5 | |
| 485 | cmp %o1, 0x28 | |
| 486 | be main_bank0 | |
| 487 | nop | |
| 488 | ||
| 489 | cmp %o1, 0x29 | |
| 490 | be main_bank1 | |
| 491 | nop | |
| 492 | ||
| 493 | cmp %o1, 0x2a | |
| 494 | be main_bank0 | |
| 495 | nop | |
| 496 | ||
| 497 | cmp %o1, 0x2b | |
| 498 | be main_bank1 | |
| 499 | nop | |
| 500 | ||
| 501 | cmp %o1, 0x2c | |
| 502 | be main_bank0 | |
| 503 | nop | |
| 504 | ||
| 505 | cmp %o1, 0x2d | |
| 506 | be main_bank1 | |
| 507 | nop | |
| 508 | ||
| 509 | cmp %o1, 0x2e | |
| 510 | be main_bank0 | |
| 511 | nop | |
| 512 | ||
| 513 | cmp %o1, 0x2f | |
| 514 | be main_bank1 | |
| 515 | nop | |
| 516 | ||
| 517 | ! Core6 | |
| 518 | cmp %o1, 0x30 | |
| 519 | be main_bank0 | |
| 520 | nop | |
| 521 | ||
| 522 | cmp %o1, 0x31 | |
| 523 | be main_bank1 | |
| 524 | nop | |
| 525 | ||
| 526 | cmp %o1, 0x32 | |
| 527 | be main_bank0 | |
| 528 | nop | |
| 529 | ||
| 530 | cmp %o1, 0x33 | |
| 531 | be main_bank1 | |
| 532 | nop | |
| 533 | ||
| 534 | cmp %o1, 0x34 | |
| 535 | be main_bank0 | |
| 536 | nop | |
| 537 | ||
| 538 | cmp %o1, 0x35 | |
| 539 | be main_bank1 | |
| 540 | nop | |
| 541 | ||
| 542 | cmp %o1, 0x36 | |
| 543 | be main_bank0 | |
| 544 | nop | |
| 545 | ||
| 546 | cmp %o1, 0x37 | |
| 547 | be main_bank1 | |
| 548 | nop | |
| 549 | ||
| 550 | ! Core7 | |
| 551 | cmp %o1, 0x38 | |
| 552 | be main_bank0 | |
| 553 | nop | |
| 554 | ||
| 555 | cmp %o1, 0x39 | |
| 556 | be main_bank1 | |
| 557 | nop | |
| 558 | ||
| 559 | cmp %o1, 0x3a | |
| 560 | be main_bank0 | |
| 561 | nop | |
| 562 | ||
| 563 | cmp %o1, 0x3b | |
| 564 | be main_bank1 | |
| 565 | nop | |
| 566 | ||
| 567 | cmp %o1, 0x3c | |
| 568 | be main_bank0 | |
| 569 | nop | |
| 570 | ||
| 571 | cmp %o1, 0x3d | |
| 572 | be main_bank1 | |
| 573 | nop | |
| 574 | ||
| 575 | cmp %o1, 0x3e | |
| 576 | be main_bank0 | |
| 577 | nop | |
| 578 | ||
| 579 | cmp %o1, 0x3f | |
| 580 | be main_bank1 | |
| 581 | nop | |
| 582 | ||
| 583 | ||
| 584 | ba test_failed | |
| 585 | nop | |
| 586 | ||
| 587 | /********************** | |
| 588 | L2 Bank 0 | |
| 589 | **********************/ | |
| 590 | main_bank0: | |
| 591 | nop | |
| 592 | nop | |
| 593 | /******************* | |
| 594 | DIMM 0,1 | |
| 595 | *******************/ | |
| 596 | L20_dimm01_init: | |
| 597 | setx 0x1111111111110000, %g7, %g5 | |
| 598 | ||
| 599 | setx L20_MCU_DM0_BK0, %g7, %o0 | |
| 600 | setx L20_MCU_DM0_BK2, %g7, %o1 | |
| 601 | setx L20_MCU_DM0_BK4, %g7, %o2 | |
| 602 | setx L20_MCU_DM0_BK6, %g7, %o3 | |
| 603 | ||
| 604 | setx L20_MCU_DM1_BK0, %g7, %o4 | |
| 605 | setx L20_MCU_DM1_BK2, %g7, %o5 | |
| 606 | setx L20_MCU_DM1_BK4, %g7, %o6 | |
| 607 | setx L20_MCU_DM1_BK6, %g7, %o7 | |
| 608 | ||
| 609 | ! to make the addr unique for each thread in PA[28] and up | |
| 610 | add %o0, %g4, %l0 | |
| 611 | add %o1, %g4, %l1 | |
| 612 | add %o2, %g4, %l2 | |
| 613 | add %o3, %g4, %l3 | |
| 614 | add %o4, %g4, %l4 | |
| 615 | add %o5, %g4, %l5 | |
| 616 | add %o6, %g4, %l6 | |
| 617 | add %o7, %g4, %l7 | |
| 618 | ||
| 619 | setx 0xabcdef1234, %g7, %g2 | |
| 620 | mov 0x1, %g1 | |
| 621 | sllx %g1, 22, %g6 | |
| 622 | ||
| 623 | mov 0x1, %g7 | |
| 624 | sllx %g7, 12, %g1 | |
| 625 | set 0x2, %g3 | |
| 626 | L20_dimm01_rd_wr: | |
| 627 | !DIMM0,1 | |
| 628 | stx %g5, [%l0] | |
| 629 | stx %g5, [%l1] | |
| 630 | stx %g5, [%l2] | |
| 631 | stx %g5, [%l3] | |
| 632 | stx %g5, [%l4] | |
| 633 | stx %g5, [%l5] | |
| 634 | stx %g5, [%l6] | |
| 635 | stx %g5, [%l7] | |
| 636 | ||
| 637 | add %l0, %g6, %o0 | |
| 638 | add %l1, %g6, %o1 | |
| 639 | add %l2, %g6, %o2 | |
| 640 | add %l3, %g6, %o3 | |
| 641 | add %l4, %g6, %o4 | |
| 642 | add %l5, %g6, %o5 | |
| 643 | add %l6, %g6, %o6 | |
| 644 | add %l7, %g6, %o7 | |
| 645 | ||
| 646 | ! cause wrb | |
| 647 | stx %g2, [%o0] | |
| 648 | stx %g2, [%o1] | |
| 649 | stx %g2, [%o2] | |
| 650 | stx %g2, [%o3] | |
| 651 | stx %g2, [%o4] | |
| 652 | stx %g2, [%o5] | |
| 653 | stx %g2, [%o6] | |
| 654 | stx %g2, [%o7] | |
| 655 | ||
| 656 | ldx [%l0], %g7 | |
| 657 | ldx [%l1], %g7 | |
| 658 | ldx [%l2], %g7 | |
| 659 | ldx [%l3], %g7 | |
| 660 | ldx [%l4], %g7 | |
| 661 | ldx [%l5], %g7 | |
| 662 | ldx [%l6], %g7 | |
| 663 | ldx [%l7], %g7 | |
| 664 | ||
| 665 | ldx [%o0], %g7 | |
| 666 | ldx [%o1], %g7 | |
| 667 | ldx [%o2], %g7 | |
| 668 | ldx [%o3], %g7 | |
| 669 | ldx [%o4], %g7 | |
| 670 | ldx [%o5], %g7 | |
| 671 | ldx [%o6], %g7 | |
| 672 | ldx [%o7], %g7 | |
| 673 | ||
| 674 | add %l0, %g1, %l0 | |
| 675 | add %l1, %g1, %l1 | |
| 676 | add %l2, %g1, %l2 | |
| 677 | add %l3, %g1, %l3 | |
| 678 | add %l4, %g1, %l4 | |
| 679 | add %l5, %g1, %l5 | |
| 680 | add %l6, %g1, %l6 | |
| 681 | add %l7, %g1, %l7 | |
| 682 | ||
| 683 | add %o0, %g1, %o0 | |
| 684 | add %o1, %g1, %o1 | |
| 685 | add %o2, %g1, %o2 | |
| 686 | add %o3, %g1, %o3 | |
| 687 | add %o4, %g1, %o4 | |
| 688 | add %o5, %g1, %o5 | |
| 689 | add %o6, %g1, %o6 | |
| 690 | add %o7, %g1, %o7 | |
| 691 | ||
| 692 | dec %g3 | |
| 693 | brnz %g3, L20_dimm01_rd_wr | |
| 694 | nop | |
| 695 | ||
| 696 | /******************* | |
| 697 | DIMM2,3 | |
| 698 | *******************/ | |
| 699 | L20_dimm23_init: | |
| 700 | setx 0x1111111111110000, %g7, %g5 | |
| 701 | ||
| 702 | setx L20_MCU_DM2_BK0, %g7, %o0 | |
| 703 | setx L20_MCU_DM2_BK2, %g7, %o1 | |
| 704 | setx L20_MCU_DM2_BK4, %g7, %o2 | |
| 705 | setx L20_MCU_DM2_BK6, %g7, %o3 | |
| 706 | ||
| 707 | setx L20_MCU_DM3_BK0, %g7, %o4 | |
| 708 | setx L20_MCU_DM3_BK2, %g7, %o5 | |
| 709 | setx L20_MCU_DM3_BK4, %g7, %o6 | |
| 710 | setx L20_MCU_DM3_BK6, %g7, %o7 | |
| 711 | ||
| 712 | ! to make the addr unique for each thread in PA[28] and up | |
| 713 | add %o0, %g4, %l0 | |
| 714 | add %o1, %g4, %l1 | |
| 715 | add %o2, %g4, %l2 | |
| 716 | add %o3, %g4, %l3 | |
| 717 | add %o4, %g4, %l4 | |
| 718 | add %o5, %g4, %l5 | |
| 719 | add %o6, %g4, %l6 | |
| 720 | add %o7, %g4, %l7 | |
| 721 | ||
| 722 | setx 0xabcdef1234, %g7, %g2 | |
| 723 | mov 0x1, %g1 | |
| 724 | sllx %g1, 22, %g6 | |
| 725 | ||
| 726 | mov 0x1, %g7 | |
| 727 | sllx %g7, 12, %g1 | |
| 728 | set 0x2, %g3 | |
| 729 | ||
| 730 | mov 0x1, %g7 | |
| 731 | sllx %g7, 12, %g1 | |
| 732 | set 0x2, %g3 | |
| 733 | ||
| 734 | L20_dimm23_rd_wr: | |
| 735 | stx %g5, [%l0] | |
| 736 | stx %g5, [%l1] | |
| 737 | stx %g5, [%l2] | |
| 738 | stx %g5, [%l3] | |
| 739 | stx %g5, [%l4] | |
| 740 | stx %g5, [%l5] | |
| 741 | stx %g5, [%l6] | |
| 742 | stx %g5, [%l7] | |
| 743 | ||
| 744 | add %l0, %g6, %o0 | |
| 745 | add %l1, %g6, %o1 | |
| 746 | add %l2, %g6, %o2 | |
| 747 | add %l3, %g6, %o3 | |
| 748 | add %l4, %g6, %o4 | |
| 749 | add %l5, %g6, %o5 | |
| 750 | add %l6, %g6, %o6 | |
| 751 | add %l7, %g6, %o7 | |
| 752 | ||
| 753 | ! cause wrb | |
| 754 | stx %g2, [%o0] | |
| 755 | stx %g2, [%o1] | |
| 756 | stx %g2, [%o2] | |
| 757 | stx %g2, [%o3] | |
| 758 | stx %g2, [%o4] | |
| 759 | stx %g2, [%o5] | |
| 760 | stx %g2, [%o6] | |
| 761 | stx %g2, [%o7] | |
| 762 | ||
| 763 | ||
| 764 | ||
| 765 | ldx [%l0], %g7 | |
| 766 | ldx [%l1], %g7 | |
| 767 | ldx [%l2], %g7 | |
| 768 | ldx [%l3], %g7 | |
| 769 | ldx [%l4], %g7 | |
| 770 | ldx [%l5], %g7 | |
| 771 | ldx [%l6], %g7 | |
| 772 | ldx [%l7], %g7 | |
| 773 | ||
| 774 | ldx [%o0], %g7 | |
| 775 | ldx [%o1], %g7 | |
| 776 | ldx [%o2], %g7 | |
| 777 | ldx [%o3], %g7 | |
| 778 | ldx [%o4], %g7 | |
| 779 | ldx [%o5], %g7 | |
| 780 | ldx [%o6], %g7 | |
| 781 | ldx [%o7], %g7 | |
| 782 | ||
| 783 | ||
| 784 | add %l0, %g1, %l0 | |
| 785 | add %l1, %g1, %l1 | |
| 786 | add %l2, %g1, %l2 | |
| 787 | add %l3, %g1, %l3 | |
| 788 | add %l4, %g1, %l4 | |
| 789 | add %l5, %g1, %l5 | |
| 790 | add %l6, %g1, %l6 | |
| 791 | add %l7, %g1, %l7 | |
| 792 | ||
| 793 | add %o0, %g1, %o0 | |
| 794 | add %o1, %g1, %o1 | |
| 795 | add %o2, %g1, %o2 | |
| 796 | add %o3, %g1, %o3 | |
| 797 | add %o4, %g1, %o4 | |
| 798 | add %o5, %g1, %o5 | |
| 799 | add %o6, %g1, %o6 | |
| 800 | add %o7, %g1, %o7 | |
| 801 | ||
| 802 | dec %g3 | |
| 803 | brnz %g3, L20_dimm23_rd_wr | |
| 804 | nop | |
| 805 | ||
| 806 | /******************************** | |
| 807 | * DIMM 4, 5 | |
| 808 | *********************************/ | |
| 809 | L20_dimm45_init: | |
| 810 | setx 0x1111111111110000, %g7, %g5 | |
| 811 | ||
| 812 | setx L20_MCU_DM4_BK0, %g7, %o0 | |
| 813 | setx L20_MCU_DM4_BK2, %g7, %o1 | |
| 814 | setx L20_MCU_DM4_BK4, %g7, %o2 | |
| 815 | setx L20_MCU_DM4_BK6, %g7, %o3 | |
| 816 | ||
| 817 | setx L20_MCU_DM5_BK0, %g7, %o4 | |
| 818 | setx L20_MCU_DM5_BK2, %g7, %o5 | |
| 819 | setx L20_MCU_DM5_BK4, %g7, %o6 | |
| 820 | setx L20_MCU_DM5_BK6, %g7, %o7 | |
| 821 | ||
| 822 | ! to make the addr unique for each thread in PA[28] and up | |
| 823 | add %o0, %g4, %l0 | |
| 824 | add %o1, %g4, %l1 | |
| 825 | add %o2, %g4, %l2 | |
| 826 | add %o3, %g4, %l3 | |
| 827 | add %o4, %g4, %l4 | |
| 828 | add %o5, %g4, %l5 | |
| 829 | add %o6, %g4, %l6 | |
| 830 | add %o7, %g4, %l7 | |
| 831 | ||
| 832 | setx 0xabcdef1234, %g7, %g2 | |
| 833 | mov 0x1, %g1 | |
| 834 | sllx %g1, 22, %g6 | |
| 835 | ||
| 836 | mov 0x1, %g7 | |
| 837 | sllx %g7, 12, %g1 | |
| 838 | set 0x2, %g3 | |
| 839 | ||
| 840 | L20_dimm45_rd_wr: | |
| 841 | stx %g5, [%l0] | |
| 842 | stx %g5, [%l1] | |
| 843 | stx %g5, [%l2] | |
| 844 | stx %g5, [%l3] | |
| 845 | stx %g5, [%l4] | |
| 846 | stx %g5, [%l5] | |
| 847 | stx %g5, [%l6] | |
| 848 | stx %g5, [%l7] | |
| 849 | ||
| 850 | add %l0, %g6, %o0 | |
| 851 | add %l1, %g6, %o1 | |
| 852 | add %l2, %g6, %o2 | |
| 853 | add %l3, %g6, %o3 | |
| 854 | add %l4, %g6, %o4 | |
| 855 | add %l5, %g6, %o5 | |
| 856 | add %l6, %g6, %o6 | |
| 857 | add %l7, %g6, %o7 | |
| 858 | ||
| 859 | ! cause wrb | |
| 860 | stx %g2, [%o0] | |
| 861 | stx %g2, [%o1] | |
| 862 | stx %g2, [%o2] | |
| 863 | stx %g2, [%o3] | |
| 864 | stx %g2, [%o4] | |
| 865 | stx %g2, [%o5] | |
| 866 | stx %g2, [%o6] | |
| 867 | stx %g2, [%o7] | |
| 868 | ||
| 869 | ||
| 870 | ||
| 871 | ldx [%l0], %g7 | |
| 872 | ldx [%l1], %g7 | |
| 873 | ldx [%l2], %g7 | |
| 874 | ldx [%l3], %g7 | |
| 875 | ldx [%l4], %g7 | |
| 876 | ldx [%l5], %g7 | |
| 877 | ldx [%l6], %g7 | |
| 878 | ldx [%l7], %g7 | |
| 879 | ||
| 880 | ldx [%o0], %g7 | |
| 881 | ldx [%o1], %g7 | |
| 882 | ldx [%o2], %g7 | |
| 883 | ldx [%o3], %g7 | |
| 884 | ldx [%o4], %g7 | |
| 885 | ldx [%o5], %g7 | |
| 886 | ldx [%o6], %g7 | |
| 887 | ldx [%o7], %g7 | |
| 888 | ||
| 889 | ||
| 890 | add %l0, %g1, %l0 | |
| 891 | add %l1, %g1, %l1 | |
| 892 | add %l2, %g1, %l2 | |
| 893 | add %l3, %g1, %l3 | |
| 894 | add %l4, %g1, %l4 | |
| 895 | add %l5, %g1, %l5 | |
| 896 | add %l6, %g1, %l6 | |
| 897 | add %l7, %g1, %l7 | |
| 898 | ||
| 899 | add %o0, %g1, %o0 | |
| 900 | add %o1, %g1, %o1 | |
| 901 | add %o2, %g1, %o2 | |
| 902 | add %o3, %g1, %o3 | |
| 903 | add %o4, %g1, %o4 | |
| 904 | add %o5, %g1, %o5 | |
| 905 | add %o6, %g1, %o6 | |
| 906 | add %o7, %g1, %o7 | |
| 907 | ||
| 908 | dec %g3 | |
| 909 | brnz %g3, L20_dimm45_rd_wr | |
| 910 | nop | |
| 911 | ||
| 912 | /******************************** | |
| 913 | * DIMM 6, 7 | |
| 914 | *********************************/ | |
| 915 | L20_dimm67_init: | |
| 916 | setx 0x1111111111110000, %g7, %g5 | |
| 917 | ||
| 918 | setx L20_MCU_DM6_BK0, %g7, %o0 | |
| 919 | setx L20_MCU_DM6_BK2, %g7, %o1 | |
| 920 | setx L20_MCU_DM6_BK4, %g7, %o2 | |
| 921 | setx L20_MCU_DM6_BK6, %g7, %o3 | |
| 922 | ||
| 923 | setx L20_MCU_DM7_BK0, %g7, %o4 | |
| 924 | setx L20_MCU_DM7_BK2, %g7, %o5 | |
| 925 | setx L20_MCU_DM7_BK4, %g7, %o6 | |
| 926 | setx L20_MCU_DM7_BK6, %g7, %o7 | |
| 927 | ||
| 928 | ! to make the addr unique for each thread in PA[28] and up | |
| 929 | add %o0, %g4, %l0 | |
| 930 | add %o1, %g4, %l1 | |
| 931 | add %o2, %g4, %l2 | |
| 932 | add %o3, %g4, %l3 | |
| 933 | add %o4, %g4, %l4 | |
| 934 | add %o5, %g4, %l5 | |
| 935 | add %o6, %g4, %l6 | |
| 936 | add %o7, %g4, %l7 | |
| 937 | ||
| 938 | setx 0xabcdef1234, %g7, %g2 | |
| 939 | mov 0x1, %g1 | |
| 940 | sllx %g1, 22, %g6 | |
| 941 | ||
| 942 | mov 0x1, %g7 | |
| 943 | sllx %g7, 12, %g1 | |
| 944 | set 0x2, %g3 | |
| 945 | ||
| 946 | L20_dimm67_rd_wr: | |
| 947 | stx %g5, [%l0] | |
| 948 | stx %g5, [%l1] | |
| 949 | stx %g5, [%l2] | |
| 950 | stx %g5, [%l3] | |
| 951 | stx %g5, [%l4] | |
| 952 | stx %g5, [%l5] | |
| 953 | stx %g5, [%l6] | |
| 954 | stx %g5, [%l7] | |
| 955 | ||
| 956 | add %l0, %g6, %o0 | |
| 957 | add %l1, %g6, %o1 | |
| 958 | add %l2, %g6, %o2 | |
| 959 | add %l3, %g6, %o3 | |
| 960 | add %l4, %g6, %o4 | |
| 961 | add %l5, %g6, %o5 | |
| 962 | add %l6, %g6, %o6 | |
| 963 | add %l7, %g6, %o7 | |
| 964 | ||
| 965 | ! cause wrb | |
| 966 | stx %g2, [%o0] | |
| 967 | stx %g2, [%o1] | |
| 968 | stx %g2, [%o2] | |
| 969 | stx %g2, [%o3] | |
| 970 | stx %g2, [%o4] | |
| 971 | stx %g2, [%o5] | |
| 972 | stx %g2, [%o6] | |
| 973 | stx %g2, [%o7] | |
| 974 | ||
| 975 | ldx [%l0], %g7 | |
| 976 | ldx [%l1], %g7 | |
| 977 | ldx [%l2], %g7 | |
| 978 | ldx [%l3], %g7 | |
| 979 | ldx [%l4], %g7 | |
| 980 | ldx [%l5], %g7 | |
| 981 | ldx [%l6], %g7 | |
| 982 | ldx [%l7], %g7 | |
| 983 | ||
| 984 | ldx [%o0], %g7 | |
| 985 | ldx [%o1], %g7 | |
| 986 | ldx [%o2], %g7 | |
| 987 | ldx [%o3], %g7 | |
| 988 | ldx [%o4], %g7 | |
| 989 | ldx [%o5], %g7 | |
| 990 | ldx [%o6], %g7 | |
| 991 | ldx [%o7], %g7 | |
| 992 | ||
| 993 | ||
| 994 | add %l0, %g1, %l0 | |
| 995 | add %l1, %g1, %l1 | |
| 996 | add %l2, %g1, %l2 | |
| 997 | add %l3, %g1, %l3 | |
| 998 | add %l4, %g1, %l4 | |
| 999 | add %l5, %g1, %l5 | |
| 1000 | add %l6, %g1, %l6 | |
| 1001 | add %l7, %g1, %l7 | |
| 1002 | ||
| 1003 | add %o0, %g1, %o0 | |
| 1004 | add %o1, %g1, %o1 | |
| 1005 | add %o2, %g1, %o2 | |
| 1006 | add %o3, %g1, %o3 | |
| 1007 | add %o4, %g1, %o4 | |
| 1008 | add %o5, %g1, %o5 | |
| 1009 | add %o6, %g1, %o6 | |
| 1010 | add %o7, %g1, %o7 | |
| 1011 | ||
| 1012 | dec %g3 | |
| 1013 | brnz %g3, L20_dimm67_rd_wr | |
| 1014 | nop | |
| 1015 | ||
| 1016 | /*********************************** | |
| 1017 | L2 Bank 1 | |
| 1018 | ***********************************/ | |
| 1019 | main_bank1: | |
| 1020 | nop | |
| 1021 | nop | |
| 1022 | ||
| 1023 | /******************************** | |
| 1024 | * DIMM 0, 1 | |
| 1025 | *********************************/ | |
| 1026 | L2_1_dimm01_init: | |
| 1027 | setx 0x1111111111110000, %g7, %g5 | |
| 1028 | ||
| 1029 | setx L2_1_MCU_DM0_BK1, %g7, %o0 | |
| 1030 | setx L2_1_MCU_DM0_BK3, %g7, %o1 | |
| 1031 | setx L2_1_MCU_DM0_BK5, %g7, %o2 | |
| 1032 | setx L2_1_MCU_DM0_BK7, %g7, %o3 | |
| 1033 | ||
| 1034 | setx L2_1_MCU_DM1_BK1, %g7, %o4 | |
| 1035 | setx L2_1_MCU_DM1_BK3, %g7, %o5 | |
| 1036 | setx L2_1_MCU_DM1_BK5, %g7, %o6 | |
| 1037 | setx L2_1_MCU_DM1_BK7, %g7, %o7 | |
| 1038 | ||
| 1039 | ! to make the addr unique for each thread in PA[28] and up | |
| 1040 | add %o0, %g4, %l0 | |
| 1041 | add %o1, %g4, %l1 | |
| 1042 | add %o2, %g4, %l2 | |
| 1043 | add %o3, %g4, %l3 | |
| 1044 | add %o4, %g4, %l4 | |
| 1045 | add %o5, %g4, %l5 | |
| 1046 | add %o6, %g4, %l6 | |
| 1047 | add %o7, %g4, %l7 | |
| 1048 | ||
| 1049 | setx 0xabcdef1234, %g7, %g2 | |
| 1050 | mov 0x1, %g1 | |
| 1051 | sllx %g1, 22, %g6 | |
| 1052 | ||
| 1053 | mov 0x1, %g7 | |
| 1054 | sllx %g7, 12, %g1 | |
| 1055 | set 0x2, %g3 | |
| 1056 | ||
| 1057 | L2_1_dimm01_rd_wr: | |
| 1058 | stx %g5, [%l0] | |
| 1059 | stx %g5, [%l1] | |
| 1060 | stx %g5, [%l2] | |
| 1061 | stx %g5, [%l3] | |
| 1062 | stx %g5, [%l4] | |
| 1063 | stx %g5, [%l5] | |
| 1064 | stx %g5, [%l6] | |
| 1065 | stx %g5, [%l7] | |
| 1066 | ||
| 1067 | add %l0, %g6, %o0 | |
| 1068 | add %l1, %g6, %o1 | |
| 1069 | add %l2, %g6, %o2 | |
| 1070 | add %l3, %g6, %o3 | |
| 1071 | add %l4, %g6, %o4 | |
| 1072 | add %l5, %g6, %o5 | |
| 1073 | add %l6, %g6, %o6 | |
| 1074 | add %l7, %g6, %o7 | |
| 1075 | ||
| 1076 | ! cause wrb | |
| 1077 | stx %g2, [%o0] | |
| 1078 | stx %g2, [%o1] | |
| 1079 | stx %g2, [%o2] | |
| 1080 | stx %g2, [%o3] | |
| 1081 | stx %g2, [%o4] | |
| 1082 | stx %g2, [%o5] | |
| 1083 | stx %g2, [%o6] | |
| 1084 | stx %g2, [%o7] | |
| 1085 | ||
| 1086 | ||
| 1087 | ||
| 1088 | ldx [%l0], %g7 | |
| 1089 | ldx [%l1], %g7 | |
| 1090 | ldx [%l2], %g7 | |
| 1091 | ldx [%l3], %g7 | |
| 1092 | ldx [%l4], %g7 | |
| 1093 | ldx [%l5], %g7 | |
| 1094 | ldx [%l6], %g7 | |
| 1095 | ldx [%l7], %g7 | |
| 1096 | ||
| 1097 | ldx [%o0], %g7 | |
| 1098 | ldx [%o1], %g7 | |
| 1099 | ldx [%o2], %g7 | |
| 1100 | ldx [%o3], %g7 | |
| 1101 | ldx [%o4], %g7 | |
| 1102 | ldx [%o5], %g7 | |
| 1103 | ldx [%o6], %g7 | |
| 1104 | ldx [%o7], %g7 | |
| 1105 | ||
| 1106 | ||
| 1107 | add %l0, %g1, %l0 | |
| 1108 | add %l1, %g1, %l1 | |
| 1109 | add %l2, %g1, %l2 | |
| 1110 | add %l3, %g1, %l3 | |
| 1111 | add %l4, %g1, %l4 | |
| 1112 | add %l5, %g1, %l5 | |
| 1113 | add %l6, %g1, %l6 | |
| 1114 | add %l7, %g1, %l7 | |
| 1115 | ||
| 1116 | add %o0, %g1, %o0 | |
| 1117 | add %o1, %g1, %o1 | |
| 1118 | add %o2, %g1, %o2 | |
| 1119 | add %o3, %g1, %o3 | |
| 1120 | add %o4, %g1, %o4 | |
| 1121 | add %o5, %g1, %o5 | |
| 1122 | add %o6, %g1, %o6 | |
| 1123 | add %o7, %g1, %o7 | |
| 1124 | ||
| 1125 | dec %g3 | |
| 1126 | brnz %g3, L2_1_dimm01_rd_wr | |
| 1127 | nop | |
| 1128 | ||
| 1129 | /******************************** | |
| 1130 | * DIMM 2, 3 | |
| 1131 | *********************************/ | |
| 1132 | L2_1_dimm23_init: | |
| 1133 | setx 0x1111111111110000, %g7, %g5 | |
| 1134 | ||
| 1135 | setx L2_1_MCU_DM0_BK1, %g7, %o0 | |
| 1136 | setx L2_1_MCU_DM0_BK3, %g7, %o1 | |
| 1137 | setx L2_1_MCU_DM0_BK5, %g7, %o2 | |
| 1138 | setx L2_1_MCU_DM0_BK7, %g7, %o3 | |
| 1139 | ||
| 1140 | setx L2_1_MCU_DM1_BK1, %g7, %o4 | |
| 1141 | setx L2_1_MCU_DM1_BK3, %g7, %o5 | |
| 1142 | setx L2_1_MCU_DM1_BK5, %g7, %o6 | |
| 1143 | setx L2_1_MCU_DM1_BK7, %g7, %o7 | |
| 1144 | ||
| 1145 | ! to make the addr unique for each thread in PA[28] and up | |
| 1146 | add %o0, %g4, %l0 | |
| 1147 | add %o1, %g4, %l1 | |
| 1148 | add %o2, %g4, %l2 | |
| 1149 | add %o3, %g4, %l3 | |
| 1150 | add %o4, %g4, %l4 | |
| 1151 | add %o5, %g4, %l5 | |
| 1152 | add %o6, %g4, %l6 | |
| 1153 | add %o7, %g4, %l7 | |
| 1154 | ||
| 1155 | setx 0xabcdef1234, %g7, %g2 | |
| 1156 | mov 0x1, %g1 | |
| 1157 | sllx %g1, 22, %g6 | |
| 1158 | ||
| 1159 | mov 0x1, %g7 | |
| 1160 | sllx %g7, 12, %g1 | |
| 1161 | set 0x2, %g3 | |
| 1162 | ||
| 1163 | L2_1_dimm23_rd_wr: | |
| 1164 | stx %g5, [%l0] | |
| 1165 | stx %g5, [%l1] | |
| 1166 | stx %g5, [%l2] | |
| 1167 | stx %g5, [%l3] | |
| 1168 | stx %g5, [%l4] | |
| 1169 | stx %g5, [%l5] | |
| 1170 | stx %g5, [%l6] | |
| 1171 | stx %g5, [%l7] | |
| 1172 | ||
| 1173 | add %l0, %g6, %o0 | |
| 1174 | add %l1, %g6, %o1 | |
| 1175 | add %l2, %g6, %o2 | |
| 1176 | add %l3, %g6, %o3 | |
| 1177 | add %l4, %g6, %o4 | |
| 1178 | add %l5, %g6, %o5 | |
| 1179 | add %l6, %g6, %o6 | |
| 1180 | add %l7, %g6, %o7 | |
| 1181 | ||
| 1182 | ! cause wrb | |
| 1183 | stx %g2, [%o0] | |
| 1184 | stx %g2, [%o1] | |
| 1185 | stx %g2, [%o2] | |
| 1186 | stx %g2, [%o3] | |
| 1187 | stx %g2, [%o4] | |
| 1188 | stx %g2, [%o5] | |
| 1189 | stx %g2, [%o6] | |
| 1190 | stx %g2, [%o7] | |
| 1191 | ||
| 1192 | ||
| 1193 | ||
| 1194 | ldx [%l0], %g7 | |
| 1195 | ldx [%l1], %g7 | |
| 1196 | ldx [%l2], %g7 | |
| 1197 | ldx [%l3], %g7 | |
| 1198 | ldx [%l4], %g7 | |
| 1199 | ldx [%l5], %g7 | |
| 1200 | ldx [%l6], %g7 | |
| 1201 | ldx [%l7], %g7 | |
| 1202 | ||
| 1203 | ldx [%o0], %g7 | |
| 1204 | ldx [%o1], %g7 | |
| 1205 | ldx [%o2], %g7 | |
| 1206 | ldx [%o3], %g7 | |
| 1207 | ldx [%o4], %g7 | |
| 1208 | ldx [%o5], %g7 | |
| 1209 | ldx [%o6], %g7 | |
| 1210 | ldx [%o7], %g7 | |
| 1211 | ||
| 1212 | ||
| 1213 | add %l0, %g1, %l0 | |
| 1214 | add %l1, %g1, %l1 | |
| 1215 | add %l2, %g1, %l2 | |
| 1216 | add %l3, %g1, %l3 | |
| 1217 | add %l4, %g1, %l4 | |
| 1218 | add %l5, %g1, %l5 | |
| 1219 | add %l6, %g1, %l6 | |
| 1220 | add %l7, %g1, %l7 | |
| 1221 | ||
| 1222 | add %o0, %g1, %o0 | |
| 1223 | add %o1, %g1, %o1 | |
| 1224 | add %o2, %g1, %o2 | |
| 1225 | add %o3, %g1, %o3 | |
| 1226 | add %o4, %g1, %o4 | |
| 1227 | add %o5, %g1, %o5 | |
| 1228 | add %o6, %g1, %o6 | |
| 1229 | add %o7, %g1, %o7 | |
| 1230 | ||
| 1231 | dec %g3 | |
| 1232 | brnz %g3, L2_1_dimm23_rd_wr | |
| 1233 | nop | |
| 1234 | ||
| 1235 | /******************************** | |
| 1236 | * DIMM4, 5 | |
| 1237 | *********************************/ | |
| 1238 | L2_1_dimm45_init: | |
| 1239 | setx 0x1111111111110000, %g7, %g5 | |
| 1240 | ||
| 1241 | setx L2_1_MCU_DM0_BK1, %g7, %o0 | |
| 1242 | setx L2_1_MCU_DM0_BK3, %g7, %o1 | |
| 1243 | setx L2_1_MCU_DM0_BK5, %g7, %o2 | |
| 1244 | setx L2_1_MCU_DM0_BK7, %g7, %o3 | |
| 1245 | ||
| 1246 | setx L2_1_MCU_DM1_BK1, %g7, %o4 | |
| 1247 | setx L2_1_MCU_DM1_BK3, %g7, %o5 | |
| 1248 | setx L2_1_MCU_DM1_BK5, %g7, %o6 | |
| 1249 | setx L2_1_MCU_DM1_BK7, %g7, %o7 | |
| 1250 | ||
| 1251 | ! to make the addr unique for each thread in PA[28] and up | |
| 1252 | add %o0, %g4, %l0 | |
| 1253 | add %o1, %g4, %l1 | |
| 1254 | add %o2, %g4, %l2 | |
| 1255 | add %o3, %g4, %l3 | |
| 1256 | add %o4, %g4, %l4 | |
| 1257 | add %o5, %g4, %l5 | |
| 1258 | add %o6, %g4, %l6 | |
| 1259 | add %o7, %g4, %l7 | |
| 1260 | ||
| 1261 | setx 0xabcdef1234, %g7, %g2 | |
| 1262 | mov 0x1, %g1 | |
| 1263 | sllx %g1, 22, %g6 | |
| 1264 | ||
| 1265 | mov 0x1, %g7 | |
| 1266 | sllx %g7, 12, %g1 | |
| 1267 | set 0x2, %g3 | |
| 1268 | ||
| 1269 | L2_1_dimm45_rd_wr: | |
| 1270 | stx %g5, [%l0] | |
| 1271 | stx %g5, [%l1] | |
| 1272 | stx %g5, [%l2] | |
| 1273 | stx %g5, [%l3] | |
| 1274 | stx %g5, [%l4] | |
| 1275 | stx %g5, [%l5] | |
| 1276 | stx %g5, [%l6] | |
| 1277 | stx %g5, [%l7] | |
| 1278 | ||
| 1279 | add %l0, %g6, %o0 | |
| 1280 | add %l1, %g6, %o1 | |
| 1281 | add %l2, %g6, %o2 | |
| 1282 | add %l3, %g6, %o3 | |
| 1283 | add %l4, %g6, %o4 | |
| 1284 | add %l5, %g6, %o5 | |
| 1285 | add %l6, %g6, %o6 | |
| 1286 | add %l7, %g6, %o7 | |
| 1287 | ||
| 1288 | ! cause wrb | |
| 1289 | stx %g2, [%o0] | |
| 1290 | stx %g2, [%o1] | |
| 1291 | stx %g2, [%o2] | |
| 1292 | stx %g2, [%o3] | |
| 1293 | stx %g2, [%o4] | |
| 1294 | stx %g2, [%o5] | |
| 1295 | stx %g2, [%o6] | |
| 1296 | stx %g2, [%o7] | |
| 1297 | ||
| 1298 | ||
| 1299 | ||
| 1300 | ldx [%l0], %g7 | |
| 1301 | ldx [%l1], %g7 | |
| 1302 | ldx [%l2], %g7 | |
| 1303 | ldx [%l3], %g7 | |
| 1304 | ldx [%l4], %g7 | |
| 1305 | ldx [%l5], %g7 | |
| 1306 | ldx [%l6], %g7 | |
| 1307 | ldx [%l7], %g7 | |
| 1308 | ||
| 1309 | ldx [%o0], %g7 | |
| 1310 | ldx [%o1], %g7 | |
| 1311 | ldx [%o2], %g7 | |
| 1312 | ldx [%o3], %g7 | |
| 1313 | ldx [%o4], %g7 | |
| 1314 | ldx [%o5], %g7 | |
| 1315 | ldx [%o6], %g7 | |
| 1316 | ldx [%o7], %g7 | |
| 1317 | ||
| 1318 | ||
| 1319 | add %l0, %g1, %l0 | |
| 1320 | add %l1, %g1, %l1 | |
| 1321 | add %l2, %g1, %l2 | |
| 1322 | add %l3, %g1, %l3 | |
| 1323 | add %l4, %g1, %l4 | |
| 1324 | add %l5, %g1, %l5 | |
| 1325 | add %l6, %g1, %l6 | |
| 1326 | add %l7, %g1, %l7 | |
| 1327 | ||
| 1328 | add %o0, %g1, %o0 | |
| 1329 | add %o1, %g1, %o1 | |
| 1330 | add %o2, %g1, %o2 | |
| 1331 | add %o3, %g1, %o3 | |
| 1332 | add %o4, %g1, %o4 | |
| 1333 | add %o5, %g1, %o5 | |
| 1334 | add %o6, %g1, %o6 | |
| 1335 | add %o7, %g1, %o7 | |
| 1336 | ||
| 1337 | dec %g3 | |
| 1338 | brnz %g3, L2_1_dimm45_rd_wr | |
| 1339 | nop | |
| 1340 | ||
| 1341 | /******************************** | |
| 1342 | * DIMM 6, 7 | |
| 1343 | *********************************/ | |
| 1344 | L2_1_dimm67_init: | |
| 1345 | setx 0x1111111111110000, %g7, %g5 | |
| 1346 | ||
| 1347 | setx L2_1_MCU_DM0_BK1, %g7, %o0 | |
| 1348 | setx L2_1_MCU_DM0_BK3, %g7, %o1 | |
| 1349 | setx L2_1_MCU_DM0_BK5, %g7, %o2 | |
| 1350 | setx L2_1_MCU_DM0_BK7, %g7, %o3 | |
| 1351 | ||
| 1352 | setx L2_1_MCU_DM1_BK1, %g7, %o4 | |
| 1353 | setx L2_1_MCU_DM1_BK3, %g7, %o5 | |
| 1354 | setx L2_1_MCU_DM1_BK5, %g7, %o6 | |
| 1355 | setx L2_1_MCU_DM1_BK7, %g7, %o7 | |
| 1356 | ||
| 1357 | ! to make the addr unique for each thread in PA[28] and up | |
| 1358 | add %o0, %g4, %l0 | |
| 1359 | add %o1, %g4, %l1 | |
| 1360 | add %o2, %g4, %l2 | |
| 1361 | add %o3, %g4, %l3 | |
| 1362 | add %o4, %g4, %l4 | |
| 1363 | add %o5, %g4, %l5 | |
| 1364 | add %o6, %g4, %l6 | |
| 1365 | add %o7, %g4, %l7 | |
| 1366 | ||
| 1367 | setx 0xabcdef1234, %g7, %g2 | |
| 1368 | mov 0x1, %g1 | |
| 1369 | sllx %g1, 22, %g6 | |
| 1370 | ||
| 1371 | mov 0x1, %g7 | |
| 1372 | sllx %g7, 12, %g1 | |
| 1373 | set 0x2, %g3 | |
| 1374 | ||
| 1375 | L2_1_dimm67_rd_wr: | |
| 1376 | stx %g5, [%l0] | |
| 1377 | stx %g5, [%l1] | |
| 1378 | stx %g5, [%l2] | |
| 1379 | stx %g5, [%l3] | |
| 1380 | stx %g5, [%l4] | |
| 1381 | stx %g5, [%l5] | |
| 1382 | stx %g5, [%l6] | |
| 1383 | stx %g5, [%l7] | |
| 1384 | ||
| 1385 | add %l0, %g6, %o0 | |
| 1386 | add %l1, %g6, %o1 | |
| 1387 | add %l2, %g6, %o2 | |
| 1388 | add %l3, %g6, %o3 | |
| 1389 | add %l4, %g6, %o4 | |
| 1390 | add %l5, %g6, %o5 | |
| 1391 | add %l6, %g6, %o6 | |
| 1392 | add %l7, %g6, %o7 | |
| 1393 | ||
| 1394 | ! cause wrb | |
| 1395 | stx %g2, [%o0] | |
| 1396 | stx %g2, [%o1] | |
| 1397 | stx %g2, [%o2] | |
| 1398 | stx %g2, [%o3] | |
| 1399 | stx %g2, [%o4] | |
| 1400 | stx %g2, [%o5] | |
| 1401 | stx %g2, [%o6] | |
| 1402 | stx %g2, [%o7] | |
| 1403 | ||
| 1404 | ||
| 1405 | ldx [%l0], %g7 | |
| 1406 | ldx [%l1], %g7 | |
| 1407 | ldx [%l2], %g7 | |
| 1408 | ldx [%l3], %g7 | |
| 1409 | ldx [%l4], %g7 | |
| 1410 | ldx [%l5], %g7 | |
| 1411 | ldx [%l6], %g7 | |
| 1412 | ldx [%l7], %g7 | |
| 1413 | ||
| 1414 | ldx [%o0], %g7 | |
| 1415 | ldx [%o1], %g7 | |
| 1416 | ldx [%o2], %g7 | |
| 1417 | ldx [%o3], %g7 | |
| 1418 | ldx [%o4], %g7 | |
| 1419 | ldx [%o5], %g7 | |
| 1420 | ldx [%o6], %g7 | |
| 1421 | ldx [%o7], %g7 | |
| 1422 | ||
| 1423 | ||
| 1424 | ||
| 1425 | add %l0, %g1, %l0 | |
| 1426 | add %l1, %g1, %l1 | |
| 1427 | add %l2, %g1, %l2 | |
| 1428 | add %l3, %g1, %l3 | |
| 1429 | add %l4, %g1, %l4 | |
| 1430 | add %l5, %g1, %l5 | |
| 1431 | add %l6, %g1, %l6 | |
| 1432 | add %l7, %g1, %l7 | |
| 1433 | ||
| 1434 | add %o0, %g1, %o0 | |
| 1435 | add %o1, %g1, %o1 | |
| 1436 | add %o2, %g1, %o2 | |
| 1437 | add %o3, %g1, %o3 | |
| 1438 | add %o4, %g1, %o4 | |
| 1439 | add %o5, %g1, %o5 | |
| 1440 | add %o6, %g1, %o6 | |
| 1441 | add %o7, %g1, %o7 | |
| 1442 | ||
| 1443 | dec %g3 | |
| 1444 | brnz %g3, L2_1_dimm67_rd_wr | |
| 1445 | nop | |
| 1446 | ||
| 1447 | /****************************************************** | |
| 1448 | * Exit code | |
| 1449 | *******************************************************/ | |
| 1450 | ||
| 1451 | test_passed: | |
| 1452 | EXIT_GOOD | |
| 1453 | ||
| 1454 | test_failed: | |
| 1455 | EXIT_BAD | |
| 1456 |