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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / mcu / n2_pm_mcu_diff_th_wr_rd.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_pm_mcu_diff_th_wr_rd.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41
42#include "hboot.s"
43#include "asi_s.h"
44
45
46#ifdef BANK0
47#define L2_0_ADDR0 0x220000000
48#endif
49
50#ifdef BANK1
51#define L2_0_ADDR0 0x220000040
52#endif
53
54#define L2_0_ADDR1 0x440000000
55
56#define TAG_SHIFT 22
57
58#ifdef L2_OFF
59#define L2_ON_OFF_DM 0x1
60#else
61#define L2_ON_OFF_DM 0x0
62#endif
63
64
65.text
66.global main
67
68
69main:
70 ta T_CHANGE_HPRIV
71 nop
72
73get_th_id_o0:
74 ta T_RD_THID
75
76 ! Core0
77 cmp %o1, 0x0
78 be main_th_wr
79 nop
80
81 cmp %o1, 0x1
82 be main_th_rd
83 nop
84
85 cmp %o1, 0x2
86 be main_th_wr
87 nop
88
89 cmp %o1, 0x3
90 be main_th_rd
91 nop
92
93 cmp %o1, 0x4
94 be main_th_wr
95 nop
96
97 cmp %o1, 0x5
98 be main_th_rd
99 nop
100
101 cmp %o1, 0x6
102 be main_th_wr
103 nop
104
105 cmp %o1, 0x7
106 be main_th_rd
107 nop
108
109 ! Core1
110 cmp %o1, 0x8
111 be main_th_wr
112 nop
113
114 cmp %o1, 0x9
115 be main_th_rd
116 nop
117
118 cmp %o1, 0xa
119 be main_th_wr
120 nop
121
122 cmp %o1, 0xb
123 be main_th_rd
124 nop
125
126 cmp %o1, 0xc
127 be main_th_wr
128 nop
129
130 cmp %o1, 0xd
131 be main_th_rd
132 nop
133
134 cmp %o1, 0xe
135 be main_th_wr
136 nop
137
138 cmp %o1, 0xf
139 be main_th_rd
140 nop
141
142
143 ! Core2
144 cmp %o1, 0x10
145 be main_th_wr
146 nop
147
148 cmp %o1, 0x11
149 be main_th_rd
150 nop
151
152 cmp %o1, 0x12
153 be main_th_wr
154 nop
155
156 cmp %o1, 0x13
157 be main_th_rd
158 nop
159
160 cmp %o1, 0x14
161 be main_th_wr
162 nop
163
164 cmp %o1, 0x15
165 be main_th_rd
166 nop
167
168 cmp %o1, 0x16
169 be main_th_wr
170 nop
171
172 cmp %o1, 0x17
173 be main_th_rd
174 nop
175
176
177 ! Core3
178 cmp %o1, 0x18
179 be main_th_wr
180 nop
181
182 cmp %o1, 0x19
183 be main_th_rd
184 nop
185
186 cmp %o1, 0x1a
187 be main_th_wr
188 nop
189
190 cmp %o1, 0x1b
191 be main_th_rd
192 nop
193
194 cmp %o1, 0x1c
195 be main_th_wr
196 nop
197
198 cmp %o1, 0x1d
199 be main_th_rd
200 nop
201
202 cmp %o1, 0x1e
203 be main_th_wr
204 nop
205
206 cmp %o1, 0x1f
207 be main_th_rd
208 nop
209
210
211 ! Core4
212 cmp %o1, 0x20
213 be main_th_wr
214 nop
215
216 cmp %o1, 0x21
217 be main_th_rd
218 nop
219
220 cmp %o1, 0x22
221 be main_th_wr
222 nop
223
224 cmp %o1, 0x23
225 be main_th_rd
226 nop
227
228 cmp %o1, 0x24
229 be main_th_wr
230 nop
231
232 cmp %o1, 0x25
233 be main_th_rd
234 nop
235
236 cmp %o1, 0x26
237 be main_th_wr
238 nop
239
240 cmp %o1, 0x27
241 be main_th_rd
242 nop
243
244
245 ! Core5
246 cmp %o1, 0x28
247 be main_th_wr
248 nop
249
250 cmp %o1, 0x29
251 be main_th_rd
252 nop
253
254 cmp %o1, 0x2a
255 be main_th_wr
256 nop
257
258 cmp %o1, 0x2b
259 be main_th_rd
260 nop
261
262 cmp %o1, 0x2c
263 be main_th_wr
264 nop
265
266 cmp %o1, 0x2d
267 be main_th_rd
268 nop
269
270 cmp %o1, 0x2e
271 be main_th_wr
272 nop
273
274 cmp %o1, 0x2f
275 be main_th_rd
276 nop
277
278
279 ! Core6
280 cmp %o1, 0x30
281 be main_th_wr
282 nop
283
284 cmp %o1, 0x31
285 be main_th_rd
286 nop
287
288 cmp %o1, 0x32
289 be main_th_wr
290 nop
291
292 cmp %o1, 0x33
293 be main_th_rd
294 nop
295
296 cmp %o1, 0x34
297 be main_th_wr
298 nop
299
300 cmp %o1, 0x35
301 be main_th_rd
302 nop
303
304 cmp %o1, 0x36
305 be main_th_wr
306 nop
307
308 cmp %o1, 0x37
309 be main_th_rd
310 nop
311
312
313 ! Core7
314 cmp %o1, 0x38
315 be main_th_wr
316 nop
317
318 cmp %o1, 0x39
319 be main_th_rd
320 nop
321
322 cmp %o1, 0x3a
323 be main_th_wr
324 nop
325
326 cmp %o1, 0x3b
327 be main_th_rd
328 nop
329
330 cmp %o1, 0x3c
331 be main_th_wr
332 nop
333
334 cmp %o1, 0x3d
335 be main_th_rd
336 nop
337
338 cmp %o1, 0x3e
339 be main_th_wr
340 nop
341
342 cmp %o1, 0x3f
343 be main_th_rd
344 nop
345
346
347 ba test_failed
348 nop
349
350 /*****************************************
351 All Memory Write
352 ******************************************/
353main_th_wr:
354 setx 0x1111111111110000, %g7, %g1
355 setx 0x2222222222220000, %g7, %g2
356 mov 0x1, %l2
357 sllx %l2, 22, %g6
358
359 setx L2_0_ADDR0, %g7, %g3
360 setx 0x40, %g7, %g5
361st_loop_1:
362 stx %g1, [%g3]
363 add %g3, %g6, %g4
364 stx %g2, [%g4]
365
366 add %g3, 0x200, %g3
367
368 dec %g5
369
370 inc %g1
371 inc %g2
372
373 cmp %g5, %g0
374 bne st_loop_1
375 nop
376
377 /*****************************************
378 All Memory Read
379 ******************************************/
380main_th_rd:
381 setx L2_0_ADDR1, %g7, %g3
382 setx 0x40, %g7, %g5
383ld_loop_1:
384 ldx [%g3], %o1
385 add %g3, %g6, %g4
386 ldx [%g4], %o2
387
388 add %g3, 0x200, %g3
389
390 dec %g5
391
392 cmp %g5, %g0
393 bne ld_loop_1
394 nop
395
396
397/******************************************************
398 * Exit code
399 *******************************************************/
400
401test_passed:
402EXIT_GOOD
403
404test_failed:
405EXIT_BAD
406
Full OpenSPARC design & verification tarball including full HDL.