[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / memory / memop_all_mcu.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: memop_all_mcu.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "asi_s.h"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:
	ta      T_CHANGE_HPRIV

	setx	data1, %g1, %g2
	setx	scratch, %g1, %g3

	! Load data for 1st block store/load

	ldd	[%g2], %f0
	ldd	[%g2+0x8], %f2
	ldd	[%g2+0x10], %f4
	ldd	[%g2+0x18], %f6
	ldd	[%g2+0x20], %f8
	ldd	[%g2+0x28], %f10
	ldd	[%g2+0x30], %f12
	ldd	[%g2+0x38], %f14

	! Do block store commit using 1st MCU

	stda	%f0, [%g3]ASI_BLK_COMMIT_PRIMARY
	membar	#Sync

	! Do block load using 1st MCU

	ldda	[%g3]ASI_BLOCK_PRIMARY, %f16

	! Test the data read

	fcmpd	%fcc0, %f0, %f16
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f2, %f18
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f4, %f20
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f6, %f22
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f8, %f24
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f10, %f26
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f12, %f28
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f14, %f30
	fbnz	%fcc0, test_failed
	nop

	! Load data for 2nd block store/load

	add	%g2, 64, %g2
	or	%g3, 0x80, %g3

	ldd	[%g2], %f0
	ldd	[%g2+0x8], %f2
	ldd	[%g2+0x10], %f4
	ldd	[%g2+0x18], %f6
	ldd	[%g2+0x20], %f8
	ldd	[%g2+0x28], %f10
	ldd	[%g2+0x30], %f12
	ldd	[%g2+0x38], %f14

	! Do block store commit using 2nd MCU

	stda	%f0, [%g3]ASI_BLK_COMMIT_PRIMARY
	membar	#Sync

	! Do block load using 2nd MCU

	ldda	[%g3]ASI_BLOCK_PRIMARY, %f16

	! Test the data read

	fcmpd	%fcc0, %f0, %f16
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f2, %f18
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f4, %f20
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f6, %f22
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f8, %f24
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f10, %f26
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f12, %f28
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f14, %f30
	fbnz	%fcc0, test_failed
	nop

	! Load data for 3rd block store/load

	add	%g2, 64, %g2
	or	%g3, 0x100, %g3

	ldd	[%g2], %f0
	ldd	[%g2+0x8], %f2
	ldd	[%g2+0x10], %f4
	ldd	[%g2+0x18], %f6
	ldd	[%g2+0x20], %f8
	ldd	[%g2+0x28], %f10
	ldd	[%g2+0x30], %f12
	ldd	[%g2+0x38], %f14

	! Do block store commit using 3rd MCU

	stda	%f0, [%g3]ASI_BLK_COMMIT_PRIMARY
	membar	#Sync

	! Do block load using 3rd MCU

	ldda	[%g3]ASI_BLOCK_PRIMARY, %f16

	! Test the data read

	fcmpd	%fcc0, %f0, %f16
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f2, %f18
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f4, %f20
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f6, %f22
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f8, %f24
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f10, %f26
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f12, %f28
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f14, %f30
	fbnz	%fcc0, test_failed
	nop

	! Load data for 4th block store/load

	add	%g2, 64, %g2
	or	%g3, 0x180, %g3

	ldd	[%g2], %f0
	ldd	[%g2+0x8], %f2
	ldd	[%g2+0x10], %f4
	ldd	[%g2+0x18], %f6
	ldd	[%g2+0x20], %f8
	ldd	[%g2+0x28], %f10
	ldd	[%g2+0x30], %f12
	ldd	[%g2+0x38], %f14

	! Do block store commit using 4th MCU

	stda	%f0, [%g3]ASI_BLK_COMMIT_PRIMARY
	membar	#Sync

	! Do block load using 4th MCU

	ldda	[%g3]ASI_BLOCK_PRIMARY, %f16

	! Test the data read

	fcmpd	%fcc0, %f0, %f16
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f2, %f18
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f4, %f20
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f6, %f22
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f8, %f24
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f10, %f26
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f12, %f28
	fbnz	%fcc0, test_failed
	nop
	fcmpd	%fcc0, %f14, %f30
	fbnz	%fcc0, test_failed
	nop

	! DONE

	ba	test_passed
	nop


/**********************************************************************
 *  Common code.
 *********************************************************************/
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
	.align	64
data1:
	.xword	0x0000000000000000
	.xword	0x0001000100010001
	.xword	0x0002000200020002
	.xword	0x0003000300030003
	.xword	0x0004000400040004
	.xword	0x0005000500050005
	.xword	0x0006000600060006
	.xword	0x0007000700070007
data2:
	.xword	0x0008000800080008
	.xword	0x0009000900000009
	.xword	0x000a000a000a000a
	.xword	0x000b000b000b000b
	.xword	0x000c000c000c000c
	.xword	0x000d000d000d000d
	.xword	0x000e000e000e000e
	.xword	0x000f000f000f000f
data3:
	.xword	0x0010001000100010
	.xword	0x0011001100110011
	.xword	0x0012001200120012
	.xword	0x0013001300130013
	.xword	0x0014001400140014
	.xword	0x0015001500150015
	.xword	0x0016001600160016
	.xword	0x0017001700170017
data4:
	.xword	0x0018001800180018
	.xword	0x0019001900100019
	.xword	0x001a001a001a001a
	.xword	0x001b001b001b001b
	.xword	0x001c001c001c001c
	.xword	0x001d001d001d001d
	.xword	0x001e001e001e001e
	.xword	0x001f001f001f001f

	.align	0x200			! addr [8:6] = 0
scratch:
	.skip	0x200

user_data_end:

.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: memop_all_mcu.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#include "hboot.s"
	42	#include "asi_s.h"
	43
	44	/************************************************************************
	45	Test case code start
	46	************************************************************************/
	47
	48	.text
	49	.global main
	50
	51	main:
	52	ta T_CHANGE_HPRIV
	53
	54	setx data1, %g1, %g2
	55	setx scratch, %g1, %g3
	56
	57	! Load data for 1st block store/load
	58
	59	ldd [%g2], %f0
	60	ldd [%g2+0x8], %f2
	61	ldd [%g2+0x10], %f4
	62	ldd [%g2+0x18], %f6
	63	ldd [%g2+0x20], %f8
	64	ldd [%g2+0x28], %f10
65	ldd [%g2+0x30], %f12
66	ldd [%g2+0x38], %f14
67
68	! Do block store commit using 1st MCU
69
70	stda %f0, [%g3]ASI_BLK_COMMIT_PRIMARY
71	membar #Sync
72
73	! Do block load using 1st MCU
74
75	ldda [%g3]ASI_BLOCK_PRIMARY, %f16
76
77	! Test the data read
78
79	fcmpd %fcc0, %f0, %f16
80	fbnz %fcc0, test_failed
81	nop
82	fcmpd %fcc0, %f2, %f18
83	fbnz %fcc0, test_failed
84	nop
85	fcmpd %fcc0, %f4, %f20
86	fbnz %fcc0, test_failed
87	nop
88	fcmpd %fcc0, %f6, %f22
89	fbnz %fcc0, test_failed
90	nop
91	fcmpd %fcc0, %f8, %f24
92	fbnz %fcc0, test_failed
93	nop
94	fcmpd %fcc0, %f10, %f26
95	fbnz %fcc0, test_failed
96	nop
97	fcmpd %fcc0, %f12, %f28
98	fbnz %fcc0, test_failed
99	nop
100	fcmpd %fcc0, %f14, %f30
101	fbnz %fcc0, test_failed
102	nop
103
104	! Load data for 2nd block store/load
105
106	add %g2, 64, %g2
107	or %g3, 0x80, %g3
108
109	ldd [%g2], %f0
110	ldd [%g2+0x8], %f2
111	ldd [%g2+0x10], %f4
112	ldd [%g2+0x18], %f6
113	ldd [%g2+0x20], %f8
114	ldd [%g2+0x28], %f10
115	ldd [%g2+0x30], %f12
116	ldd [%g2+0x38], %f14
117
118	! Do block store commit using 2nd MCU
119
120	stda %f0, [%g3]ASI_BLK_COMMIT_PRIMARY
121	membar #Sync
122
123	! Do block load using 2nd MCU
124
125	ldda [%g3]ASI_BLOCK_PRIMARY, %f16
126
127	! Test the data read
128
129	fcmpd %fcc0, %f0, %f16
130	fbnz %fcc0, test_failed
131	nop
132	fcmpd %fcc0, %f2, %f18
133	fbnz %fcc0, test_failed
134	nop
135	fcmpd %fcc0, %f4, %f20
136	fbnz %fcc0, test_failed
137	nop
138	fcmpd %fcc0, %f6, %f22
139	fbnz %fcc0, test_failed
140	nop
141	fcmpd %fcc0, %f8, %f24
142	fbnz %fcc0, test_failed
143	nop
144	fcmpd %fcc0, %f10, %f26
145	fbnz %fcc0, test_failed
146	nop
147	fcmpd %fcc0, %f12, %f28
148	fbnz %fcc0, test_failed
149	nop
150	fcmpd %fcc0, %f14, %f30
151	fbnz %fcc0, test_failed
152	nop
153
154	! Load data for 3rd block store/load
155
156	add %g2, 64, %g2
157	or %g3, 0x100, %g3
158
159	ldd [%g2], %f0
160	ldd [%g2+0x8], %f2
161	ldd [%g2+0x10], %f4
162	ldd [%g2+0x18], %f6
163	ldd [%g2+0x20], %f8
164	ldd [%g2+0x28], %f10
165	ldd [%g2+0x30], %f12
166	ldd [%g2+0x38], %f14
167
168	! Do block store commit using 3rd MCU
169
170	stda %f0, [%g3]ASI_BLK_COMMIT_PRIMARY
171	membar #Sync
172
173	! Do block load using 3rd MCU
174
175	ldda [%g3]ASI_BLOCK_PRIMARY, %f16
176
177	! Test the data read
178
179	fcmpd %fcc0, %f0, %f16
180	fbnz %fcc0, test_failed
181	nop
182	fcmpd %fcc0, %f2, %f18
183	fbnz %fcc0, test_failed
184	nop
185	fcmpd %fcc0, %f4, %f20
186	fbnz %fcc0, test_failed
187	nop
188	fcmpd %fcc0, %f6, %f22
189	fbnz %fcc0, test_failed
190	nop
191	fcmpd %fcc0, %f8, %f24
192	fbnz %fcc0, test_failed
193	nop
194	fcmpd %fcc0, %f10, %f26
195	fbnz %fcc0, test_failed
196	nop
197	fcmpd %fcc0, %f12, %f28
198	fbnz %fcc0, test_failed
199	nop
200	fcmpd %fcc0, %f14, %f30
201	fbnz %fcc0, test_failed
202	nop
203
204	! Load data for 4th block store/load
205
206	add %g2, 64, %g2
207	or %g3, 0x180, %g3
208
209	ldd [%g2], %f0
210	ldd [%g2+0x8], %f2
211	ldd [%g2+0x10], %f4
212	ldd [%g2+0x18], %f6
213	ldd [%g2+0x20], %f8
214	ldd [%g2+0x28], %f10
215	ldd [%g2+0x30], %f12
216	ldd [%g2+0x38], %f14
217
218	! Do block store commit using 4th MCU
219
220	stda %f0, [%g3]ASI_BLK_COMMIT_PRIMARY
221	membar #Sync
222
223	! Do block load using 4th MCU
224
225	ldda [%g3]ASI_BLOCK_PRIMARY, %f16
226
227	! Test the data read
228
229	fcmpd %fcc0, %f0, %f16
230	fbnz %fcc0, test_failed
231	nop
232	fcmpd %fcc0, %f2, %f18
233	fbnz %fcc0, test_failed
234	nop
235	fcmpd %fcc0, %f4, %f20
236	fbnz %fcc0, test_failed
237	nop
238	fcmpd %fcc0, %f6, %f22
239	fbnz %fcc0, test_failed
240	nop
241	fcmpd %fcc0, %f8, %f24
242	fbnz %fcc0, test_failed
243	nop
244	fcmpd %fcc0, %f10, %f26
245	fbnz %fcc0, test_failed
246	nop
247	fcmpd %fcc0, %f12, %f28
248	fbnz %fcc0, test_failed
249	nop
250	fcmpd %fcc0, %f14, %f30
251	fbnz %fcc0, test_failed
252	nop
253
254	! DONE
255
256	ba test_passed
257	nop
258
259
260	/**********************************************************************
261	* Common code.
262	*********************************************************************/
263
264	test_passed:
265	EXIT_GOOD
266
267	test_failed:
268	EXIT_BAD
269
270
271	/************************************************************************
272	Test case data start
273	************************************************************************/
274	.data
275	user_data_start:
276	.align 64
277	data1:
278	.xword 0x0000000000000000
279	.xword 0x0001000100010001
280	.xword 0x0002000200020002
281	.xword 0x0003000300030003
282	.xword 0x0004000400040004
283	.xword 0x0005000500050005
284	.xword 0x0006000600060006
285	.xword 0x0007000700070007
286	data2:
287	.xword 0x0008000800080008
288	.xword 0x0009000900000009
289	.xword 0x000a000a000a000a
290	.xword 0x000b000b000b000b
291	.xword 0x000c000c000c000c
292	.xword 0x000d000d000d000d
293	.xword 0x000e000e000e000e
294	.xword 0x000f000f000f000f
295	data3:
296	.xword 0x0010001000100010
297	.xword 0x0011001100110011
298	.xword 0x0012001200120012
299	.xword 0x0013001300130013
300	.xword 0x0014001400140014
301	.xword 0x0015001500150015
302	.xword 0x0016001600160016
303	.xword 0x0017001700170017
304	data4:
305	.xword 0x0018001800180018
306	.xword 0x0019001900100019
307	.xword 0x001a001a001a001a
308	.xword 0x001b001b001b001b
309	.xword 0x001c001c001c001c
310	.xword 0x001d001d001d001d
311	.xword 0x001e001e001e001e
312	.xword 0x001f001f001f001f
313
314	.align 0x200 ! addr [8:6] = 0
315	scratch:
316	.skip 0x200
317
318	user_data_end:
319
320	.end
321
322