[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / memory / memop_all_packet.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: memop_all_packet.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define SPU_TIMEOUT 0x100

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
	call	my_trap_code; \
	nop; \
	retry; \
	nop; 

#include "hboot.s"
#include "asi_s.h"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:
	ta	T_CHANGE_HPRIV

!
! Thread 0 Start
!
thread_0:

	!  PCX Load, CPX Load Return

	setx	user_data_start, %g1, %g2
load:
	setx	0x1111111111111111, %g1, %g7
	ldx	[%g2 + 0x8], %l6
	cmp	%l6, %g7
	bne	test_failed
	nop


	! PCX Prefetch, CPX Prefetch Return
prefetch:
	prefetch [%g2 + 0x10], 0x0
	membar	#Sync
	setx	0x22222222, %g1, %g3
	ld	[%g2 + 0x10], %l6
	cmp	%l6, %g3
	bne	test_failed
	nop


	! PCX Diagnostic Load, CPX Diagnostic Load Return
diagload:
	setx	0xaa00000000, %g1, %g7		! L2$ Error Enable Reg.
	ldx	[%g7], %g6


	! PCX Diagnostic Store, CPX Diagnostic Store Ack
diagstore:
	stx	%g6, [%g7]			! Store back to same reg.


	! PCX Dcache Invalidate, CPX, Dcache Invalidate Ack
dcache:
	! Not enough infomation available to know how to generate


	! PCX Instruction Fill, CPX IFill Return (1) & (2)
	! These occur all the time as code is fetched.

	
	! PCX Icache Invalidate, CPX Icache Invalidate Ack
icache:
	! Not enough infomation available to know how to generate

	
	! PCX Store, CPX Store Ack
store:	
	setx	0xa5a5a5a5, %g1, %g3
	setx	temp, %g1, %g4
	st	%g3, [%g4]
	ld	[%g4], %g5
	cmp	%g3, %g5
	bne	test_failed
	nop


	! PCX CAS (1) & (2), CPX CAS Return & Ack
cas:
        setx    0xffffffffffffffff, %g1, %l0
        casa    [%g2]ASI_PRIMARY, %g0, %l0
        cmp     %l0, 0
        bne     test_failed
        nop
        setx    0xffffffff, %g1, %g4
        ld      [%g2], %l1
        cmp     %g4, %l1
        bne     test_failed
        nop


	! PCX Swap/Ldstub, CPX Swap/Ldstub Return & Ack
swap:
        setx    0xa5a5a5a5a5a5a5a5, %g1, %g5
        swap    [%g2+0x18], %g5
        setx    0x33333333, %g1, %6
        cmp     %g5, %g6
        bne     test_failed
        nop
        ld      [%g2+0x18], %l6
        setx    0xa5a5a5a5, %g1, %g7
        cmp     %l6, %g7
        bne     test_failed
        nop


	! PCX MMU Load, CPX MMU Load Return
mmuload:
        add     %g2, 0x20, %g7
        ldda    [%g7]ASI_NUCLEUS_QUAD_LDD, %l0
        setx    0x4444444444444444, %g1, %g4
        setx    0x5555555555555555, %g1, %g3
        cmp     %l0, %g4
        bne     test_failed
        nop
        cmp     %l1, %g3
        bne     test_failed
        nop


	! PCX Interrupt, CPX Interrupt Return
interrupt:
	stxa	%g0, [%g0]ASI_SWVR_INTR_RECEIVE		! enable interrupts
	membar	#Sync
	set	0x3f, %g1
	stxa	%g1, [%g0]ASI_SWVR_INTR_W	! Send interrupt to myself
	membar	#Sync

	mov	%g1, %g3			! %g3, timeout count
	setx	my_trap_count, %g1, %g4
intr_loop:
	cmp	%g3, 0
	be	test_failed
	dec	%g3

	ld	[%g4], %g1
	cmp	%g1, 1
	bne	intr_loop
	nop

	! PCX Flush, CPX Flush Return
flush:
	setx	mmuload, %g1, %g3
	flush	%g3


	! CPX Eviction Invalidation
exiction:
	ldx	[%g2], %l1		! Bring data into a D$ line.
	mov	%g2, %o0
	call	flush_l2_line		! Causing the corresponding L2$
					! line to be replaced causes the
					! Dcache line to be invalidated.
	nop


	! CPX Error Indication
error:
	! Currently not able to induce an error on a load,
	! such as an L2$ ECC error.


	! PCX Stream Load, CPX Stream Load Return
	! PCX Stream Store, CPX Stream Store Ack
	! This code was modified from isa3_spu_cwq_tcp.s diag
stream:
        wr	%g0, 0x40, %asi		! setup ASI register to point to SPU
	
	! Make sure CWQ is currently disabled, not busy,
	! not terminated, no protocol error; else fail

	ldxa	[%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
	and	%l1, 0xf, %l2
	cmp	%g0, %l2
	bne,pn	%xcc, test_failed
	nop

	
	! Allocate control word queue
	! (e.g., setup head/tail/first/last registers)

	setx CWQ_BASE, %g1, %l6

	! First pointer

	stxa	%l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
	setx	0x0000ffffffffffff, %l5, %l0	! Mask off upper 16 bits
	and	%l0, %l6, %l2
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop

	! Head Pointer

	stxa	%l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Tail pointer

	stxa	%l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Last pointer

	setx	CWQ_LAST, %g1, %l5
	stxa	%l5, [%g0 + ASI_SPU_CWQ_LAST] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
	and	%l0, %l5, %l2		!# Mask off upper 16 bits
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Build the first control word, for the first RC4 vector.
	! First build up word 0
	! For RC4, set op = 65, Enc=1, SOB=EOB=1, SFAS=0, Int=CoreID=0,
	! AuthType=8, EncType=00, status=0, Len=30

	setx	0xc1E001080000001D, %l1, %l2

	! %l6 points to CWQ_BASE
	! Note:	All CWQ entry addresses must be physical!

	stx	%l2, [%l6 + 0x0]
	
	! Write source address to next CW field

	setx	cleartext_1, %g1, %l2
	stx	%l2, [%l6+0x8]

	! Write 0's to the next 5 CW fields as they are not used

	stx	%g0, [%l6+0x10]
	stx	%g0, [%l6+0x18]
	stx	%g0, [%l6+0x20]
	stx	%g0, [%l6+0x28] 
	stx	%g0, [%l6+0x30]

	! Finally write destination address to last CW field

	setx result_1, %g1, %o3
	stx	%o3, [%l6 + 0x38] 
	
	! Make sure all these stores get to memory before we start

	membar #Sync

	! Now add 1 (actually 8*8B) to tail pointer 

        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
	add	%l2, 0x40, %l2
	stxa	%l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi 
        ldxa	[%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
	cmp	%l1, %l2
	bne,pn	%xcc, test_failed
	nop
	
	! Kick off the CWQ operation by writing to the CWQ_CSR
	! Set the enabled bit and reset the other bits 

	or	%g0, 0x1, %g1
	stxa	%g1,	[%g0 + ASI_SPU_CWQ_CSR] %asi	

	! set maximum wait loop count, setup mask for busy bit
	! This timeout may need adjustment

	setx	SPU_TIMEOUT, %o3, %l3
	or	%g0, 0x4, %l2		! mask out the busy bit

	! loop on busy to fall through when done or loop count exceeded
spu_wait1:
	ldxa	[%g0 + ASI_SPU_CWQ_CSR] %asi,	%l1
	andcc	%l1, %l2, %l1
	be	test_passed
	addcc	%l3, -1, %l3
	bgt	spu_wait1
	nop
	ba	test_failed
	nop


/**********************************************************************
 *  Common code.
 *********************************************************************/

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD

	! Assumes that %o0 contains VA that maps to L2$ line to be flushed,
	! and %o7 contains the return address.  The flush is done by
	! doing 16 loads from different addresses that alias to that line.
	! Note that this will cause a writeback if the L2$ line is dirty.
	! The registers %o1, %o2, %o3, %o4 and %o5 are used.
	
flush_l2_line:
	setx	0x3ffff, %o1, %o2
	and	%o0, %o2, %o3
	setx	0x40000, %o1, %o2
	setx	alias1, %o1, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	add	%o4, %o2, %o4
	ld	[%o3+%o4], %o5
	jmpl	%o7+0x8, %g0
	nop


/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global	my_trap_code

my_trap_code:
	! Increment the count
	
	setx	my_trap_count, %g6, %g7
	ld	[%g7], %g5
	add	%g5, 1, %g5
	st	%g5, [%g7]
	membar	#Sync

	! Clear the interrupt

	ldxa	[%g0]ASI_SWVR_INTR_R, %g3

	jmpl	%o7+0x8, %g0
	nop

	
/************************************************************************
   Test case data start
 ************************************************************************/
.data
user_data_start:
	.xword 0x0000000000000000
	.xword 0x1111111111111111
	.xword 0x2222222222222222
	.xword 0x3333333333333333
	.xword 0x4444444444444444
	.xword 0x5555555555555555
	.xword 0x6666666666666666
	.xword 0x7777777777777777
	.xword 0x8888888888888888
	.xword 0x9999999999999999
	.xword 0xaaaaaaaaaaaaaaaa
	.xword 0xbbbbbbbbbbbbbbbb
	.xword 0xcccccccccccccccc
	.xword 0xdddddddddddddddd
	.xword 0xeeeeeeeeeeeeeeee
	.xword 0xffffffffffffffff
temp:
	.xword 0xffffffffaaaaaaaa
	.xword 0xffffffffaaaaaaaa
	.xword 0xffffffffaaaaaaaa
	.xword 0xffffffffaaaaaaaa

my_trap_count:
	.xword 0x0

	! Data used for steam (SPU) load/store testing

	! input data
	.align 16
cleartext_1:		
	.xword	0xDEECA425C5AF7185
	.xword	0xB128069258CF5271
	.xword	0xF2D9FC0493661FF4
	.xword	0x4C6DC5810067DEAD	
	 
	! expected ciphertext
	.align 16
ciphertext_1:	
	.xword	0x2e2dBEEFDEADBEEF

	.align 16
result_1:	
	.xword	0xDEADBEEFDEADBEEF			
	
	! CWQ data area, set aside 512 CW's worth
	! 512*8*8 = 32K

	.align 32*1024
CWQ_BASE:		
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.xword	0xAAAAAAAAAAAAAAA
	.align 32*1024
CWQ_LAST:	
					
user_data_end:


	.align	0x40000		! each 246kb, 0x40000, aliases to same L2$ line
alias1:
	.skip	1024

.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: memop_all_packet.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40	#define SPU_TIMEOUT 0x100
	41
	42	#define H_HT0_Interrupt_0x60
	43	#define My_HT0_Interrupt_0x60 \
	44	call my_trap_code; \
	45	nop; \
	46	retry; \
	47	nop;
	48
	49	#include "hboot.s"
	50	#include "asi_s.h"
	51
	52	/************************************************************************
	53	Test case code start
	54	************************************************************************/
	55
	56	.text
	57	.global main
	58
	59	main:
	60	ta T_CHANGE_HPRIV
	61
	62	!
	63	! Thread 0 Start
	64	!
65	thread_0:
66
67	! PCX Load, CPX Load Return
68
69	setx user_data_start, %g1, %g2
70	load:
71	setx 0x1111111111111111, %g1, %g7
72	ldx [%g2 + 0x8], %l6
73	cmp %l6, %g7
74	bne test_failed
75	nop
76
77
78	! PCX Prefetch, CPX Prefetch Return
79	prefetch:
80	prefetch [%g2 + 0x10], 0x0
81	membar #Sync
82	setx 0x22222222, %g1, %g3
83	ld [%g2 + 0x10], %l6
84	cmp %l6, %g3
85	bne test_failed
86	nop
87
88
89	! PCX Diagnostic Load, CPX Diagnostic Load Return
90	diagload:
91	setx 0xaa00000000, %g1, %g7 ! L2$ Error Enable Reg.
92	ldx [%g7], %g6
93
94
95	! PCX Diagnostic Store, CPX Diagnostic Store Ack
96	diagstore:
97	stx %g6, [%g7] ! Store back to same reg.
98
99
100	! PCX Dcache Invalidate, CPX, Dcache Invalidate Ack
101	dcache:
102	! Not enough infomation available to know how to generate
103
104
105	! PCX Instruction Fill, CPX IFill Return (1) & (2)
106	! These occur all the time as code is fetched.
107
108
109	! PCX Icache Invalidate, CPX Icache Invalidate Ack
110	icache:
111	! Not enough infomation available to know how to generate
112
113
114	! PCX Store, CPX Store Ack
115	store:
116	setx 0xa5a5a5a5, %g1, %g3
117	setx temp, %g1, %g4
118	st %g3, [%g4]
119	ld [%g4], %g5
120	cmp %g3, %g5
121	bne test_failed
122	nop
123
124
125	! PCX CAS (1) & (2), CPX CAS Return & Ack
126	cas:
127	setx 0xffffffffffffffff, %g1, %l0
128	casa [%g2]ASI_PRIMARY, %g0, %l0
129	cmp %l0, 0
130	bne test_failed
131	nop
132	setx 0xffffffff, %g1, %g4
133	ld [%g2], %l1
134	cmp %g4, %l1
135	bne test_failed
136	nop
137
138
139	! PCX Swap/Ldstub, CPX Swap/Ldstub Return & Ack
140	swap:
141	setx 0xa5a5a5a5a5a5a5a5, %g1, %g5
142	swap [%g2+0x18], %g5
143	setx 0x33333333, %g1, %6
144	cmp %g5, %g6
145	bne test_failed
146	nop
147	ld [%g2+0x18], %l6
148	setx 0xa5a5a5a5, %g1, %g7
149	cmp %l6, %g7
150	bne test_failed
151	nop
152
153
154	! PCX MMU Load, CPX MMU Load Return
155	mmuload:
156	add %g2, 0x20, %g7
157	ldda [%g7]ASI_NUCLEUS_QUAD_LDD, %l0
158	setx 0x4444444444444444, %g1, %g4
159	setx 0x5555555555555555, %g1, %g3
160	cmp %l0, %g4
161	bne test_failed
162	nop
163	cmp %l1, %g3
164	bne test_failed
165	nop
166
167
168	! PCX Interrupt, CPX Interrupt Return
169	interrupt:
170	stxa %g0, [%g0]ASI_SWVR_INTR_RECEIVE ! enable interrupts
171	membar #Sync
172	set 0x3f, %g1
173	stxa %g1, [%g0]ASI_SWVR_INTR_W ! Send interrupt to myself
174	membar #Sync
175
176	mov %g1, %g3 ! %g3, timeout count
177	setx my_trap_count, %g1, %g4
178	intr_loop:
179	cmp %g3, 0
180	be test_failed
181	dec %g3
182
183	ld [%g4], %g1
184	cmp %g1, 1
185	bne intr_loop
186	nop
187
188	! PCX Flush, CPX Flush Return
189	flush:
190	setx mmuload, %g1, %g3
191	flush %g3
192
193
194	! CPX Eviction Invalidation
195	exiction:
196	ldx [%g2], %l1 ! Bring data into a D$ line.
197	mov %g2, %o0
198	call flush_l2_line ! Causing the corresponding L2$
199	! line to be replaced causes the
200	! Dcache line to be invalidated.
201	nop
202
203
204	! CPX Error Indication
205	error:
206	! Currently not able to induce an error on a load,
207	! such as an L2$ ECC error.
208
209
210	! PCX Stream Load, CPX Stream Load Return
211	! PCX Stream Store, CPX Stream Store Ack
212	! This code was modified from isa3_spu_cwq_tcp.s diag
213	stream:
214	wr %g0, 0x40, %asi ! setup ASI register to point to SPU
215
216	! Make sure CWQ is currently disabled, not busy,
217	! not terminated, no protocol error; else fail
218
219	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
220	and %l1, 0xf, %l2
221	cmp %g0, %l2
222	bne,pn %xcc, test_failed
223	nop
224
225
226	! Allocate control word queue
227	! (e.g., setup head/tail/first/last registers)
228
229	setx CWQ_BASE, %g1, %l6
230
231	! First pointer
232
233	stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
234	ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
235	setx 0x0000ffffffffffff, %l5, %l0 ! Mask off upper 16 bits
236	and %l0, %l6, %l2
237	cmp %l1, %l2
238	bne,pn %xcc, test_failed
239	nop
240
241	! Head Pointer
242
243	stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
244	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
245	cmp %l1, %l2
246	bne,pn %xcc, test_failed
247	nop
248
249	! Tail pointer
250
251	stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
252	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
253	cmp %l1, %l2
254	bne,pn %xcc, test_failed
255	nop
256
257	! Last pointer
258
259	setx CWQ_LAST, %g1, %l5
260	stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
261	ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
262	and %l0, %l5, %l2 !# Mask off upper 16 bits
263	cmp %l1, %l2
264	bne,pn %xcc, test_failed
265	nop
266
267	! Build the first control word, for the first RC4 vector.
268	! First build up word 0
269	! For RC4, set op = 65, Enc=1, SOB=EOB=1, SFAS=0, Int=CoreID=0,
270	! AuthType=8, EncType=00, status=0, Len=30
271
272	setx 0xc1E001080000001D, %l1, %l2
273
274	! %l6 points to CWQ_BASE
275	! Note: All CWQ entry addresses must be physical!
276
277	stx %l2, [%l6 + 0x0]
278
279	! Write source address to next CW field
280
281	setx cleartext_1, %g1, %l2
282	stx %l2, [%l6+0x8]
283
284	! Write 0's to the next 5 CW fields as they are not used
285
286	stx %g0, [%l6+0x10]
287	stx %g0, [%l6+0x18]
288	stx %g0, [%l6+0x20]
289	stx %g0, [%l6+0x28]
290	stx %g0, [%l6+0x30]
291
292	! Finally write destination address to last CW field
293
294	setx result_1, %g1, %o3
295	stx %o3, [%l6 + 0x38]
296
297	! Make sure all these stores get to memory before we start
298
299	membar #Sync
300
301	! Now add 1 (actually 8*8B) to tail pointer
302
303	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
304	add %l2, 0x40, %l2
305	stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
306	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
307	cmp %l1, %l2
308	bne,pn %xcc, test_failed
309	nop
310
311	! Kick off the CWQ operation by writing to the CWQ_CSR
312	! Set the enabled bit and reset the other bits
313
314	or %g0, 0x1, %g1
315	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
316
317	! set maximum wait loop count, setup mask for busy bit
318	! This timeout may need adjustment
319
320	setx SPU_TIMEOUT, %o3, %l3
321	or %g0, 0x4, %l2 ! mask out the busy bit
322
323	! loop on busy to fall through when done or loop count exceeded
324	spu_wait1:
325	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
326	andcc %l1, %l2, %l1
327	be test_passed
328	addcc %l3, -1, %l3
329	bgt spu_wait1
330	nop
331	ba test_failed
332	nop
333
334
335	/**********************************************************************
336	* Common code.
337	*********************************************************************/
338
339	test_passed:
340	EXIT_GOOD
341
342	test_failed:
343	EXIT_BAD
344
345	! Assumes that %o0 contains VA that maps to L2$ line to be flushed,
346	! and %o7 contains the return address. The flush is done by
347	! doing 16 loads from different addresses that alias to that line.
348	! Note that this will cause a writeback if the L2$ line is dirty.
349	! The registers %o1, %o2, %o3, %o4 and %o5 are used.
350
351	flush_l2_line:
352	setx 0x3ffff, %o1, %o2
353	and %o0, %o2, %o3
354	setx 0x40000, %o1, %o2
355	setx alias1, %o1, %o4
356	ld [%o3+%o4], %o5
357	add %o4, %o2, %o4
358	ld [%o3+%o4], %o5
359	add %o4, %o2, %o4
360	ld [%o3+%o4], %o5
361	add %o4, %o2, %o4
362	ld [%o3+%o4], %o5
363	add %o4, %o2, %o4
364	ld [%o3+%o4], %o5
365	add %o4, %o2, %o4
366	ld [%o3+%o4], %o5
367	add %o4, %o2, %o4
368	ld [%o3+%o4], %o5
369	add %o4, %o2, %o4
370	ld [%o3+%o4], %o5
371	add %o4, %o2, %o4
372	ld [%o3+%o4], %o5
373	add %o4, %o2, %o4
374	ld [%o3+%o4], %o5
375	add %o4, %o2, %o4
376	ld [%o3+%o4], %o5
377	add %o4, %o2, %o4
378	ld [%o3+%o4], %o5
379	add %o4, %o2, %o4
380	ld [%o3+%o4], %o5
381	add %o4, %o2, %o4
382	ld [%o3+%o4], %o5
383	add %o4, %o2, %o4
384	ld [%o3+%o4], %o5
385	add %o4, %o2, %o4
386	ld [%o3+%o4], %o5
387	jmpl %o7+0x8, %g0
388	nop
389
390
391	/**********************************************************************
392	Interrupt trap handler.
393	**********************************************************************/
394
395	.global my_trap_code
396
397	my_trap_code:
398	! Increment the count
399
400	setx my_trap_count, %g6, %g7
401	ld [%g7], %g5
402	add %g5, 1, %g5
403	st %g5, [%g7]
404	membar #Sync
405
406	! Clear the interrupt
407
408	ldxa [%g0]ASI_SWVR_INTR_R, %g3
409
410	jmpl %o7+0x8, %g0
411	nop
412
413
414	/************************************************************************
415	Test case data start
416	************************************************************************/
417	.data
418	user_data_start:
419	.xword 0x0000000000000000
420	.xword 0x1111111111111111
421	.xword 0x2222222222222222
422	.xword 0x3333333333333333
423	.xword 0x4444444444444444
424	.xword 0x5555555555555555
425	.xword 0x6666666666666666
426	.xword 0x7777777777777777
427	.xword 0x8888888888888888
428	.xword 0x9999999999999999
429	.xword 0xaaaaaaaaaaaaaaaa
430	.xword 0xbbbbbbbbbbbbbbbb
431	.xword 0xcccccccccccccccc
432	.xword 0xdddddddddddddddd
433	.xword 0xeeeeeeeeeeeeeeee
434	.xword 0xffffffffffffffff
435	temp:
436	.xword 0xffffffffaaaaaaaa
437	.xword 0xffffffffaaaaaaaa
438	.xword 0xffffffffaaaaaaaa
439	.xword 0xffffffffaaaaaaaa
440
441	my_trap_count:
442	.xword 0x0
443
444	! Data used for steam (SPU) load/store testing
445
446	! input data
447	.align 16
448	cleartext_1:
449	.xword 0xDEECA425C5AF7185
450	.xword 0xB128069258CF5271
451	.xword 0xF2D9FC0493661FF4
452	.xword 0x4C6DC5810067DEAD
453
454	! expected ciphertext
455	.align 16
456	ciphertext_1:
457	.xword 0x2e2dBEEFDEADBEEF
458
459	.align 16
460	result_1:
461	.xword 0xDEADBEEFDEADBEEF
462
463	! CWQ data area, set aside 512 CW's worth
464	! 51288 = 32K
465
466	.align 32*1024
467	CWQ_BASE:
468	.xword 0xAAAAAAAAAAAAAAA
469	.xword 0xAAAAAAAAAAAAAAA
470	.xword 0xAAAAAAAAAAAAAAA
471	.xword 0xAAAAAAAAAAAAAAA
472	.xword 0xAAAAAAAAAAAAAAA
473	.xword 0xAAAAAAAAAAAAAAA
474	.xword 0xAAAAAAAAAAAAAAA
475	.xword 0xAAAAAAAAAAAAAAA
476	.align 32*1024
477	CWQ_LAST:
478
479	user_data_end:
480
481
482
483	.align 0x40000 ! each 246kb, 0x40000, aliases to same L2$ line
484	alias1:
485	.skip 1024
486
487	.end
488
489