Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / memory / memop_mcu_regs_ro.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: memop_mcu_regs_ro.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
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14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
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19* You should have received a copy of the GNU General Public License
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21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
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36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#define DRAM_MODE_WRITE_STATUS_REG 0x8400000208
42#define DRAM_INIT_STATUS_REG 0x8400000210
43
44#include "hboot.s"
45#include "asi_s.h"
46
47/************************************************************************
48 Test case code start
49 ************************************************************************/
50
51.text
52.global main
53
54main:
55 ta T_CHANGE_HPRIV
56
57 ! Let's look at what is in CETER first.
58
59 set 0x18, %g6
60 ldxa [%g6]0x4c, %g5
61 membar #Sync
62
63 ! DRAM Mode Reg Write Status Register, in each bank
64
65 setx DRAM_MODE_WRITE_STATUS_REG, %g1, %g2
66 setx 4096, %g1, %g3
67 ldx [%g2], %g7
68 andn %g7, 1, %g7
69 cmp %g7, %g0
70 bne test_failed
71 nop
72
73 add %g2, %g3, %g2
74 ldx [%g2], %g7
75 andn %g7, 1, %g7
76 cmp %g7, %g0
77 bne test_failed
78 nop
79
80 add %g2, %g3, %g2
81 ldx [%g2], %g7
82 andn %g7, 1, %g7
83 cmp %g7, %g0
84 bne test_failed
85 nop
86
87 add %g2, %g3, %g2
88 ldx [%g2], %g7
89 andn %g7, 1, %g7
90 cmp %g7, %g0
91 bne test_failed
92 nop
93
94 ! DRAM Initialization Status Register, in each bank
95
96 setx DRAM_INIT_STATUS_REG, %g1, %g2
97 setx 4096, %g1, %g3
98 ldx [%g2], %g7
99 andn %g7, 1, %g7
100 cmp %g7, %g0
101 bne test_failed
102 nop
103
104 add %g2, %g3, %g2
105 ldx [%g2], %g7
106 andn %g7, 1, %g7
107 cmp %g7, %g0
108 bne test_failed
109 nop
110
111 add %g2, %g3, %g2
112 ldx [%g2], %g7
113 andn %g7, 1, %g7
114 cmp %g7, %g0
115 bne test_failed
116 nop
117
118 add %g2, %g3, %g2
119 ldx [%g2], %g7
120 andn %g7, 1, %g7
121 cmp %g7, %g0
122 bne test_failed
123 nop
124
125test_passed:
126 EXIT_GOOD
127
128test_failed:
129 EXIT_BAD
130
131
132/************************************************************************
133 Test case data start
134 ************************************************************************/
135.data
136user_data_start:
137.end
138
139
140