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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / power / n2_noIo_noSpu_64_thread_active.s
CommitLineData
86530b38
AT		 1/*
2! $id: tpccsyn4.s 1.7 2003/08/15 17:52:25 ms144771 Exp $
3!
4! Copyright (C) 2005 by Sun Microsystems, Inc.
5!
6! All rights reserved. No part of this design may be reproduced,
7! stored in a retrieval system, or transmitted, in any form or by
8! any means, electronic, mechanical, photocopying, recording, or
9! otherwise, without prior written permission of Sun Microsystems,
10! Inc.
11!
12! Sun Proprietary/Confidential
13!
14! Created: 09/02/03
15! Author: Manish Shah (manish.shah@sun.com)
16! Heavily modified by Greg Grohoski from highfp1.s
17! Description: Power virus diag
18!
19! Primary Contact: Greg Grohoski
20*/
21
22/* Initialization */
23#define MAIN_PAGE_HV_ALSO
24#include "hboot.s"
25#define PORTABLE_CORE
26
27!SIMS+ARGS: -midas_args=-allow_tsb_conflicts
28
29#include "asi_s.h"
30#define N_TIMES 0x1
31!#define N_SPU_TIMES 0x1fffff
32!#define N_SPU_TIMES 0x4ff
33!#define EXIT_GOOD rdpr %cwp,%g1;sub %g1,1,%g1;wrpr %g1,0,%cwp;done;nop;
34!#define EXIT_BAD rdpr %cwp,%g1;sub %g1,1,%g1;wrpr %g1,0,%cwp;done;nop;
35/*#define TEST add %g0,0x5a5,%g1;stx %g0,[%g0];done;nop;*/
36!#define TEST rdpr %cwp,%g1;add %g1,1,%g1;wrpr %g1,0,%cwp;wr %g0,0x4,%fprs
37#define TEST
38
39!#define loop_cnt 0x2ffff
40!#define loop_cnt_2 0x4ffff
41!#define loop_cnt_3 0x3fff
42
43!SIMS+ARGS: -midas_args=-allow_tsb_conflicts
44
45/************************************************************************
46 Test case code start
47 ************************************************************************/
48
49
50.global main
51
52main: /* test begin */
53
54!# setx 0x9a00000000, %g1, %g2
55!# lduw [%g2], %l6
56!# umul %l6, 2048, %l7
57!# setx DIAG_DATA_AREA, %g1, %g3
58!# setx user_data_start, %g1, %g3
59
60!# add %l7, %g3, %l7
61
62 !# Switch to hpriv mode
63 ta T_CHANGE_HPRIV
64
65 !# Turn off power management! (set by boot code)
66 wr %g0, 0x4e, %asi
67 stxa %g0, [%g0] %asi
68
69/* setx 0xffffffffffffffff,%g1,%g2;
70 setx t0_blk_area,%g1,%g3;
71 stxa %g2,[%g3] 0xe2
72 setx t1_blk_area,%g1,%g3;
73 stxa %g0,[%g3] 0xe2
74 setx t2_blk_area,%g1,%g3;
75 stxa %g2,[%g3] 0xe2
76 setx t3_blk_area,%g1,%g3;
77 stxa %g0,[%g3] 0xe2
78 setx t3_blk_area,%g1,%g3;
79 stxa %g2,[%g3] 0xe2
80 setx t4_blk_area,%g1,%g3;
81 stxa %g0,[%g3] 0xe2
82 setx t5_blk_area,%g1,%g3;
83 stxa %g2,[%g3] 0xe2
84 setx t6_blk_area,%g1,%g3;
85 stxa %g0,[%g3] 0xe2
86 setx t7_blk_area,%g1,%g3;
87 stxa %g2,[%g3] 0xe2
88 setx t8_blk_area,%g1,%g3;
89 stxa %g0,[%g3] 0xe2
90 setx t9_blk_area,%g1,%g3;
91 stxa %g2,[%g3] 0xe2
92 setx t10_blk_area,%g1,%g3;
93 stxa %g0,[%g3] 0xe2
94 setx t11_blk_area,%g1,%g3;
95 stxa %g2,[%g3] 0xe2
96 setx t12_blk_area,%g1,%g3;
97 stxa %g0,[%g3] 0xe2
98 setx t13_blk_area,%g1,%g3;
99 stxa %g2,[%g3] 0xe2
100 setx t14_blk_area,%g1,%g3;
101 stxa %g0,[%g3] 0xe2
102 setx t15_blk_area,%g1,%g3;
103 stxa %g2,[%g3] 0xe2
104 setx t16_blk_area,%g1,%g3;
105 stxa %g0,[%g3] 0xe2
106 setx t17_blk_area,%g1,%g3;
107 stxa %g2,[%g3] 0xe2
108 setx t18_blk_area,%g1,%g3;
109 stxa %g0,[%g3] 0xe2
110 setx t19_blk_area,%g1,%g3;
111 stxa %g2,[%g3] 0xe2
112 setx t20_blk_area,%g1,%g3;
113 stxa %g0,[%g3] 0xe2
114 setx t21_blk_area,%g1,%g3;
115 stxa %g2,[%g3] 0xe2
116 setx t22_blk_area,%g1,%g3;
117 stxa %g0,[%g3] 0xe2
118 setx t23_blk_area,%g1,%g3;
119 stxa %g2,[%g3] 0xe2
120 setx t24_blk_area,%g1,%g3;
121 stxa %g0,[%g3] 0xe2
122 setx t25_blk_area,%g1,%g3;
123 stxa %g2,[%g3] 0xe2
124 setx t26_blk_area,%g1,%g3;
125 stxa %g0,[%g3] 0xe2
126 setx t27_blk_area,%g1,%g3;
127 stxa %g2,[%g3] 0xe2
128 setx t28_blk_area,%g1,%g3;
129 stxa %g0,[%g3] 0xe2
130 setx t29_blk_area,%g1,%g3;
131 stxa %g2,[%g3] 0xe2
132 setx t30_blk_area,%g1,%g3;
133 stxa %g0,[%g3] 0xe2
134 setx t31_blk_area,%g1,%g3;
135 stxa %g2,[%g3] 0xe2
136 setx t32_blk_area,%g1,%g3;
137 stxa %g0,[%g3] 0xe2
138 setx t33_blk_area,%g1,%g3;
139 stxa %g2,[%g3] 0xe2
140 setx t33_blk_area,%g1,%g3;
141 stxa %g0,[%g3] 0xe2
142 setx t34_blk_area,%g1,%g3;
143 stxa %g2,[%g3] 0xe2
144 setx t35_blk_area,%g1,%g3;
145 stxa %g0,[%g3] 0xe2
146 setx t36_blk_area,%g1,%g3;
147 stxa %g2,[%g3] 0xe2
148 setx t37_blk_area,%g1,%g3;
149 stxa %g0,[%g3] 0xe2
150 setx t38_blk_area,%g1,%g3;
151 stxa %g2,[%g3] 0xe2
152 setx t39_blk_area,%g1,%g3;
153 stxa %g0,[%g3] 0xe2
154 setx t40_blk_area,%g1,%g3;
155 stxa %g2,[%g3] 0xe2
156 setx t41_blk_area,%g1,%g3;
157 stxa %g0,[%g3] 0xe2
158 setx t42_blk_area,%g1,%g3;
159 stxa %g2,[%g3] 0xe2
160 setx t43_blk_area,%g1,%g3;
161 stxa %g0,[%g3] 0xe2
162 setx t44_blk_area,%g1,%g3;
163 stxa %g2,[%g3] 0xe2
164 setx t45_blk_area,%g1,%g3;
165 stxa %g0,[%g3] 0xe2
166 setx t46_blk_area,%g1,%g3;
167 stxa %g2,[%g3] 0xe2
168 setx t47_blk_area,%g1,%g3;
169 stxa %g0,[%g3] 0xe2
170 setx t48_blk_area,%g1,%g3;
171 stxa %g2,[%g3] 0xe2
172 setx t49_blk_area,%g1,%g3;
173 stxa %g0,[%g3] 0xe2
174 setx t50_blk_area,%g1,%g3;
175 stxa %g2,[%g3] 0xe2
176 setx t51_blk_area,%g1,%g3;
177 stxa %g0,[%g3] 0xe2
178 setx t52_blk_area,%g1,%g3;
179 stxa %g2,[%g3] 0xe2
180 setx t53_blk_area,%g1,%g3;
181 stxa %g0,[%g3] 0xe2
182 setx t54_blk_area,%g1,%g3;
183 stxa %g2,[%g3] 0xe2
184 setx t55_blk_area,%g1,%g3;
185 stxa %g0,[%g3] 0xe2
186 setx t56_blk_area,%g1,%g3;
187 stxa %g2,[%g3] 0xe2
188 setx t57_blk_area,%g1,%g3;
189 stxa %g0,[%g3] 0xe2
190 setx t58_blk_area,%g1,%g3;
191 stxa %g2,[%g3] 0xe2
192 setx t59_blk_area,%g1,%g3;
193 stxa %g0,[%g3] 0xe2
194 setx t60_blk_area,%g1,%g3;
195 stxa %g2,[%g3] 0xe2
196 setx t61_blk_area,%g1,%g3;
197 stxa %g0,[%g3] 0xe2
198 setx t62_blk_area,%g1,%g3;
199 stxa %g2,[%g3] 0xe2
200 setx t63_blk_area,%g1,%g3;
201 stxa %g0,[%g3] 0xe2
202*/
203
204 th_fork(main_th,%l0);
205#include "n0_c0_test4_noSpu.s"
206#include "n0_c1_test4_noSpu.s"
207#include "n0_c2_test4_noSpu.s"
208#include "n0_c3_test4_noSpu.s"
209#include "n0_c4_test4_noSpu.s"
210#include "n0_c5_test4_noSpu.s"
211#include "n0_c6_test4_noSpu.s"
212#include "n0_c7_test4_noSpu.s"
213
Full OpenSPARC design & verification tarball including full HDL.