[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tcu / clock_test_for_si.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: clock_test_for_si.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define PLL_CTL__PA                     0x8300000000
#define PLL_CTL__PLL_CHAR_IN__POS       33
#define DBG_CONFIG__PA                  0x8600000000
#define DBG_CONFIG__PEU_DBG_CLK         0x800000000000000b
#define DBG_CONFIG__NIU_DBG_CLK__TXC    0x8000000000000229
#define DBG_CONFIG__NIU_DBG_CLK__TDMC   0x8000000000000249
#define DBG_CONFIG__NIU_DBG_CLK__RDMC   0x8000000000000269
#define DBG_CONFIG__NIU_DBG_CLK__ZCP    0x8000000000000289
#define DBG_CONFIG__NIU_DBG_CLK__IPP    0x80000000000002a9
#define DBG_CONFIG__NIU_DBG_CLK__FFLP   0x80000000000002c9
#define DBG_CONFIG__NIU_DBG_CLK__PIO    0x80000000000002e9
#define DBG_CONFIG__NIU_DBG_CLK__MAC    0x8000000000000309
#define DBG_CONFIG__NIU_DBG_CLK__META   0x8000000000000349
#define DBG_CONFIG__NIU_DBG_CLK__SMX    0x8000000000000369
#-------------

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "asi_s.h"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:
	ta      T_CHANGE_HPRIV

test_pll_char_out:        !!! pulse PLL_CTL.PLL_CHAR_IN bit
	setx PLL_CTL__PA, %g1, %g2
	ldx [%g2], %g3
	setx 1, %g1, %g4
	sllx %g4, PLL_CTL__PLL_CHAR_IN__POS, %g4
	or %g3, %g4, %g5
	stx %g5, [%g2]      !!! PLL_CTL.set PLL_CHAR_IN bit to 1
	membar #Sync
	setx 5, %g1, %g6    !!! run some cycles
1:
	add %g0, %g0, %g0
	dec %g6
	brnz %g6, 1b
	nop
	stx %g3, [%g2]      !!! set PLL_CTL.PLL_CHAR_IN bit to 0
	membar #Sync

test_peu_debug_clk:    !!! test PEU debug clock which is pkg pin DBG_DQ[91]
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__PEU_DBG_CLK, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_TXC:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__TXC, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_TDMC:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__TDMC, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_RDMC:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__RDMC, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_ZCP:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__ZCP, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_IPP:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__IPP, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_FFLP:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__FFLP, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_PIO:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__PIO, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_MAC:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__MAC, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_META:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__META, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

test_niu_debug_clk_SMX:    !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
	setx DBG_CONFIG__PA, %g1, %g2
	setx DBG_CONFIG__NIU_DBG_CLK__SMX, %g3, %g4
	stx %g4,[%g2]
	membar #Sync
	setx 100, %g1, %g2  !!! run some cycles
1:
	add %g0, %g0, %g3
	dec  %g2
	brnz %g2, 1b
	nop

diag_dummy_code:
	nop
	nop
	nop
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/
.data
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: clock_test_for_si.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define PLL_CTL__PA 0x8300000000
	39	#define PLL_CTL__PLL_CHAR_IN__POS 33
	40	#define DBG_CONFIG__PA 0x8600000000
	41	#define DBG_CONFIG__PEU_DBG_CLK 0x800000000000000b
	42	#define DBG_CONFIG__NIU_DBG_CLK__TXC 0x8000000000000229
	43	#define DBG_CONFIG__NIU_DBG_CLK__TDMC 0x8000000000000249
	44	#define DBG_CONFIG__NIU_DBG_CLK__RDMC 0x8000000000000269
	45	#define DBG_CONFIG__NIU_DBG_CLK__ZCP 0x8000000000000289
	46	#define DBG_CONFIG__NIU_DBG_CLK__IPP 0x80000000000002a9
	47	#define DBG_CONFIG__NIU_DBG_CLK__FFLP 0x80000000000002c9
	48	#define DBG_CONFIG__NIU_DBG_CLK__PIO 0x80000000000002e9
	49	#define DBG_CONFIG__NIU_DBG_CLK__MAC 0x8000000000000309
	50	#define DBG_CONFIG__NIU_DBG_CLK__META 0x8000000000000349
	51	#define DBG_CONFIG__NIU_DBG_CLK__SMX 0x8000000000000369
	52	#-------------
	53
	54	#define MAIN_PAGE_NUCLEUS_ALSO
	55	#define MAIN_PAGE_HV_ALSO
	56
	57	#include "hboot.s"
	58	#include "asi_s.h"
	59
	60	/************************************************************************
	61	Test case code start
	62	************************************************************************/
	63
	64	.text
65	.global main
66
67	main:
68	ta T_CHANGE_HPRIV
69
70	test_pll_char_out: !!! pulse PLL_CTL.PLL_CHAR_IN bit
71	setx PLL_CTL__PA, %g1, %g2
72	ldx [%g2], %g3
73	setx 1, %g1, %g4
74	sllx %g4, PLL_CTL__PLL_CHAR_IN__POS, %g4
75	or %g3, %g4, %g5
76	stx %g5, [%g2] !!! PLL_CTL.set PLL_CHAR_IN bit to 1
77	membar #Sync
78	setx 5, %g1, %g6 !!! run some cycles
79	1:
80	add %g0, %g0, %g0
81	dec %g6
82	brnz %g6, 1b
83	nop
84	stx %g3, [%g2] !!! set PLL_CTL.PLL_CHAR_IN bit to 0
85	membar #Sync
86
87	test_peu_debug_clk: !!! test PEU debug clock which is pkg pin DBG_DQ[91]
88	setx DBG_CONFIG__PA, %g1, %g2
89	setx DBG_CONFIG__PEU_DBG_CLK, %g3, %g4
90	stx %g4,[%g2]
91	membar #Sync
92	setx 100, %g1, %g2 !!! run some cycles
93	1:
94	add %g0, %g0, %g3
95	dec %g2
96	brnz %g2, 1b
97	nop
98
99	test_niu_debug_clk_TXC: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
100	setx DBG_CONFIG__PA, %g1, %g2
101	setx DBG_CONFIG__NIU_DBG_CLK__TXC, %g3, %g4
102	stx %g4,[%g2]
103	membar #Sync
104	setx 100, %g1, %g2 !!! run some cycles
105	1:
106	add %g0, %g0, %g3
107	dec %g2
108	brnz %g2, 1b
109	nop
110
111	test_niu_debug_clk_TDMC: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
112	setx DBG_CONFIG__PA, %g1, %g2
113	setx DBG_CONFIG__NIU_DBG_CLK__TDMC, %g3, %g4
114	stx %g4,[%g2]
115	membar #Sync
116	setx 100, %g1, %g2 !!! run some cycles
117	1:
118	add %g0, %g0, %g3
119	dec %g2
120	brnz %g2, 1b
121	nop
122
123	test_niu_debug_clk_RDMC: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
124	setx DBG_CONFIG__PA, %g1, %g2
125	setx DBG_CONFIG__NIU_DBG_CLK__RDMC, %g3, %g4
126	stx %g4,[%g2]
127	membar #Sync
128	setx 100, %g1, %g2 !!! run some cycles
129	1:
130	add %g0, %g0, %g3
131	dec %g2
132	brnz %g2, 1b
133	nop
134
135	test_niu_debug_clk_ZCP: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
136	setx DBG_CONFIG__PA, %g1, %g2
137	setx DBG_CONFIG__NIU_DBG_CLK__ZCP, %g3, %g4
138	stx %g4,[%g2]
139	membar #Sync
140	setx 100, %g1, %g2 !!! run some cycles
141	1:
142	add %g0, %g0, %g3
143	dec %g2
144	brnz %g2, 1b
145	nop
146
147	test_niu_debug_clk_IPP: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
148	setx DBG_CONFIG__PA, %g1, %g2
149	setx DBG_CONFIG__NIU_DBG_CLK__IPP, %g3, %g4
150	stx %g4,[%g2]
151	membar #Sync
152	setx 100, %g1, %g2 !!! run some cycles
153	1:
154	add %g0, %g0, %g3
155	dec %g2
156	brnz %g2, 1b
157	nop
158
159	test_niu_debug_clk_FFLP: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
160	setx DBG_CONFIG__PA, %g1, %g2
161	setx DBG_CONFIG__NIU_DBG_CLK__FFLP, %g3, %g4
162	stx %g4,[%g2]
163	membar #Sync
164	setx 100, %g1, %g2 !!! run some cycles
165	1:
166	add %g0, %g0, %g3
167	dec %g2
168	brnz %g2, 1b
169	nop
170
171	test_niu_debug_clk_PIO: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
172	setx DBG_CONFIG__PA, %g1, %g2
173	setx DBG_CONFIG__NIU_DBG_CLK__PIO, %g3, %g4
174	stx %g4,[%g2]
175	membar #Sync
176	setx 100, %g1, %g2 !!! run some cycles
177	1:
178	add %g0, %g0, %g3
179	dec %g2
180	brnz %g2, 1b
181	nop
182
183	test_niu_debug_clk_MAC: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
184	setx DBG_CONFIG__PA, %g1, %g2
185	setx DBG_CONFIG__NIU_DBG_CLK__MAC, %g3, %g4
186	stx %g4,[%g2]
187	membar #Sync
188	setx 100, %g1, %g2 !!! run some cycles
189	1:
190	add %g0, %g0, %g3
191	dec %g2
192	brnz %g2, 1b
193	nop
194
195	test_niu_debug_clk_META: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
196	setx DBG_CONFIG__PA, %g1, %g2
197	setx DBG_CONFIG__NIU_DBG_CLK__META, %g3, %g4
198	stx %g4,[%g2]
199	membar #Sync
200	setx 100, %g1, %g2 !!! run some cycles
201	1:
202	add %g0, %g0, %g3
203	dec %g2
204	brnz %g2, 1b
205	nop
206
207	test_niu_debug_clk_SMX: !!! test NIU debug clocks which are DBG_DQ[125:124 pkg pins
208	setx DBG_CONFIG__PA, %g1, %g2
209	setx DBG_CONFIG__NIU_DBG_CLK__SMX, %g3, %g4
210	stx %g4,[%g2]
211	membar #Sync
212	setx 100, %g1, %g2 !!! run some cycles
213	1:
214	add %g0, %g0, %g3
215	dec %g2
216	brnz %g2, 1b
217	nop
218
219	diag_dummy_code:
220	nop
221	nop
222	nop
223	nop
224
225	test_passed:
226	EXIT_GOOD
227
228	test_failed:
229	EXIT_BAD
230
231
232	/************************************************************************
233	Test case data start
234	************************************************************************/
235	.data
236	.end
237
238
239