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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: tcu_clkstp_spcdbgevent.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Control_Transfer_Instr_0x74 My_Control_Transfer_Instr_trap_hdler | |
39 | ||
40 | #define MAIN_PAGE_HV_ALSO | |
41 | #define MAIN_PAGE_NUCLEUS_ALSO | |
42 | ||
43 | ||
44 | #include "hboot.s" | |
45 | ||
46 | /************************************************************************ | |
47 | Test case code start | |
48 | ************************************************************************/ | |
49 | ||
50 | .text | |
51 | .global main | |
52 | .global My_Control_Transfer_Instr_trap_hdler | |
53 | ||
54 | main: /* test begin */ | |
55 | ||
56 | ta T_CHANGE_HPRIV | |
57 | ||
58 | !------- delay loop for vera program ------ | |
59 | #ifdef VERA_PROG_DEL | |
60 | setx VERA_PROG_DEL, %g6, %g7 | |
61 | 1: | |
62 | dec %g7 | |
63 | brnz %g7, 1b | |
64 | nop | |
65 | #endif | |
66 | ||
67 | !--- set the pstate.tct bit --- | |
68 | rdpr %pstate, %g1 ! pstate: Processor State Reg (see 3.2.2 of PRM) | |
69 | or %g1, 0x1000, %g1 ! bit 12 or Trap on Control Transfer (ie. branching) bit of pstate Reg | |
70 | wrpr %g1, %pstate | |
71 | ||
72 | !--- program core DECR (Debug Event Control Reg). core DECR is one per core----- | |
73 | #ifdef SPC_HARDSTOP | |
74 | write_DECR_to_enable_hardstop: | |
75 | setx 0xaaaa800000000000, %g1, %g3 ! hard stop: 2'b10. Core DECR: [63:46]: debug event enable, [45:0]: reserved | |
76 | setx 0x8, %g1, %g2 ! core DECR: VA address is 0x8 | |
77 | stxa %g3, [%g2]0x45 ! core DECR: ASI is 0x45 | |
78 | nop | |
79 | membar #Sync | |
80 | nop | |
81 | ba jump1 !!! branch will generate a spc debug event | |
82 | nop | |
83 | #endif | |
84 | ||
85 | #ifdef SPC_SOFTSTOP | |
86 | write_DECR_to_enable_softstop: | |
87 | setx 0x5555400000000000, %g1, %g3 ! soft stop: 2'b01. Core DECR: [63:46]: debug event enable, [45:0]: reserved | |
88 | setx 0x8, %g1, %g2 ! core DECR: VA address is 0x8 | |
89 | stxa %g3, [%g2]0x45 ! core DECR: ASI is 0x45 | |
90 | nop | |
91 | membar #Sync | |
92 | nop | |
93 | ba jump1 !!! branch will generate a spc debug event | |
94 | nop | |
95 | #endif | |
96 | ||
97 | #ifdef SPC_TRIGOUT | |
98 | write_DECR_to_enable_trigout: | |
99 | setx 0xffffc00000000000, %g1, %g3 ! trigout: 2'b11. Core DECR: [63:46]: debug event enable, [45:0]: reserved | |
100 | setx 0x8, %g1, %g2 ! core DECR: VA address is 0x8 | |
101 | stxa %g3, [%g2]0x45 ! core DECR: ASI is 0x45 | |
102 | nop | |
103 | membar #Sync | |
104 | nop | |
105 | ba jump1 !!! branch will generate a spc debug event | |
106 | nop | |
107 | #endif | |
108 | ||
109 | jump1: | |
110 | nop | |
111 | nop | |
112 | nop | |
113 | !--- clear the pstate.tct bit --- | |
114 | rdpr %pstate, %g1 ! pstate: Processor State Reg (see 3.2.2 of PRM) | |
115 | and %g1, 0xffffffffffffefff, %g1 ! clear bit 12 or Trap on Control Transfer (ie. branching) bit of pstate Reg | |
116 | wrpr %g1, %pstate | |
117 | nop | |
118 | nop | |
119 | ||
120 | jump2: | |
121 | nop | |
122 | nop | |
123 | nop | |
124 | nop | |
125 | ||
126 | !------- delay loop for vera program ------ | |
127 | #ifdef VERA_PROG_DEL2 | |
128 | setx VERA_PROG_DEL2, %g6, %g7 | |
129 | 1: | |
130 | dec %g7 | |
131 | brnz %g7, 1b | |
132 | nop | |
133 | #endif | |
134 | ||
135 | diag_pass: | |
136 | EXIT_GOOD | |
137 | ||
138 | diag_fail: | |
139 | EXIT_BAD | |
140 | ||
141 | /************************************************************************ | |
142 | * Trap handlers | |
143 | ************************************************************************/ | |
144 | ||
145 | My_Control_Transfer_Instr_trap_hdler: | |
146 | nop | |
147 | done | |
148 | nop | |
149 | ||
150 | ||
151 | /************************************************************************ | |
152 | Test case data start | |
153 | ************************************************************************/ | |
154 | .data | |
155 | ||
156 | user_data_start: | |
157 | .xword 0xFFFFFFFFFFFFFFFF | |
158 | .end |