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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tcu / tcu_regs_asi.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tcu_regs_asi.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#define TEST_DATA0 0x4c3fdead4c3fbeef
42#define tmp1 %l2
43#define tmp2 %l3
44
45#include "asi_s.h"
46#include "mcu_defines.h"
47#include "tcu_defines.h"
48
49/************************************************************************
50 Test case code start
51 ************************************************************************/
52
53#ifdef FAST_BOOT
54#define RESET_VEC 0x0000000000000000
55#else
56#define RESET_VEC 0xfffffffff0000000
57#endif
58
59SECTION .RED_SEC TEXT_VA = RESET_VEC
60attr_text {
61 Name=.RED_SEC,
62 hypervisor
63}
64
65.text
66 nop
67 nop
68 nop
69 nop
70 nop
71 nop
72 nop
73 nop
74
75.global main
76
77main:
78
79 ! ASI_INST_MASK_REG
80L1:
81 wr %g0, 0x42, %asi
82 ldxa [%g0 + ASI_INST_MASK] %asi, %g7
83 cmp %g7 , %g0
84 bne bad_trap
85 membar #Sync
86
87 ! ASI_LSU_DIAG_REG
88L2:
89 wr %g0, 0x42, %asi
90 ldxa [%g0 + ASI_LSU_DIAG] %asi, %g7
91 cmp %g7 , %g0
92 bne bad_trap
93 membar #Sync
94
95 ! ASI_ERROR_INJECT_REG (ASI_ERROR_INJECT)
96L3:
97 wr %g0, 0x43, %asi
98 ldxa [%g0 ] %asi, %g7
99 cmp %g7 , %g0
100 bne bad_trap
101 membar #Sync
102
103 ! ASI_LSU_CONTROL_REG
104L4:
105 wr %g0, 0x45, %asi
106 ldxa [%g0 ] %asi, %g7
107 cmp %g7 , %g0
108 bne bad_trap
109 membar #Sync
110
111 ! ASI_DECR
112L5:
113 wr %g0, 0x45, %asi
114 ldxa [%g0 + 0x8] %asi, %g7
115 cmp %g7 , %g0
116 bne bad_trap
117 membar #Sync
118
119 ! ASI_RST_VEC_MASK
120L6:
121 set 0x1, %i3
122 wr %g0, 0x45, %asi
123 ldxa [%g0 + 0x18] %asi, %g7
124 cmp %g7 , %i3
125 bne bad_trap
126 membar #Sync
127
128 ! ASI_DESR
129L7:
130 wr %g0, 0x4c, %asi
131 ldxa [%g0 ] %asi, %g7
132 cmp %g7 , %g0
133 bne bad_trap
134 membar #Sync
135
136 ! ASI_DFESR
137L8:
138 wr %g0, 0x4c, %asi
139 ldxa [%g0 + 0x8] %asi, %g7
140 cmp %g7 , %g0
141 bne bad_trap
142 membar #Sync
143
144 ! ASI_CERER
145L9:
146 wr %g0, 0x4c, %asi
147 ldxa [%g0 + 0x10] %asi, %g7
148 cmp %g7 , %g0
149 bne bad_trap
150 membar #Sync
151
152 ! ASI_CETER
153L10:
154 wr %g0, 0x4c, %asi
155 ldxa [%g0 + 0x18] %asi, %g7
156 cmp %g7 , %g0
157 bne bad_trap
158 membar #Sync
159
160 ! ASI_CLESR
161L11:
162 wr %g0, 0x4c, %asi
163 ldxa [%g0 + 0x20] %asi, %g7
164 cmp %g7 , %g0
165 bne bad_trap
166 membar #Sync
167
168 ! ASI_CLFESR
169L12:
170 wr %g0, 0x4c, %asi
171 ldxa [%g0 + 0x28] %asi, %g7
172 cmp %g7 , %g0
173 bne bad_trap
174 membar #Sync
175
176 ! ASI_SPARC_PWR_MGMT
177L13:
178 wr %g0, 0x4e, %asi
179 ldxa [%g0 ] %asi, %g7
180 cmp %g7 , %g0
181 bne bad_trap
182 membar #Sync
183
184 ! ASI_HYP_SCRATCHPAD_0
185L14:
186 wr %g0, 0x4f, %asi
187 ldxa [%g0 ] %asi, %g7
188 cmp %g7 , %g0
189 bne bad_trap
190 membar #Sync
191
192 ! ASI_CMP_TICK_ENABLE
193L15:
194 wr %g0, 0x41, %asi
195 ldxa [%g0 + ASI_CMP_TICK_ENABLE] %asi, %g7
196 cmp %g7 , %g0
197 bne bad_trap
198 membar #Sync
199
200 ! ASI_CORE_AVAILABLE (0x41)
201L16:
202 set 0xff, tmp2
203 wr %g0, 0x41, %asi
204 ldxa [%g0 ] %asi, %g7
205 cmp tmp2, %g7
206 bne bad_trap
207 membar #Sync
208
209 ! ASI_CORE_ENABLE_STATUS (0x41)
210L17:
211 set 0xff, tmp2
212 wr %g0, 0x41, %asi
213 ldxa [%g0 + ASI_CMP_CORE_ENABLED] %asi, %g7
214 cmp tmp2, %g7
215 bne bad_trap
216 membar #Sync
217
218 ! ASI_CORE_ENABLE (0x41)
219L18:
220 set 0xff, tmp2
221 wr %g0, 0x41, %asi
222 ldxa [%g0 + ASI_CMP_CORE_ENABLE] %asi, %g7
223 cmp tmp2, %g7
224 bne bad_trap
225 membar #Sync
226
227 ! ASI_XIR_STEERING (0x41)
228L19:
229 set 0xff, tmp2
230 wr %g0, 0x41, %asi
231 ldxa [%g0 + ASI_CMP_XIR_STEERING] %asi, %g7
232 cmp tmp2, %g7
233 bne bad_trap
234 membar #Sync
235
236 ! ASI_CORE_RUNNING_RW (0x41)
237L20:
238 set 0x1, tmp2
239 wr %g0, 0x41, %asi
240 ldxa [%g0 + ASI_CMP_CORE_RUNNING_RW] %asi, %g7
241 cmp tmp2, %g7
242 bne bad_trap
243 membar #Sync
244
245 ! ASI_CORE_RUNNING_STATUS (0x41)
246L21:
247 set 0x1, tmp2
248 wr %g0, 0x41, %asi
249 ldxa [%g0 + ASI_CMP_CORE_RUNNING_STATUS] %asi, %g7
250 cmp tmp2, %g7
251 bne bad_trap
252 membar #Sync
253
254 ! ASI_HYP_SCRATCHPAD_1
255L22:
256 wr %g0, 0x4f, %asi
257 ldxa [%g0 + ASI_HYP_SCRATCHPAD_1] %asi, %g7
258 cmp %g7 , %g0
259 bne bad_trap
260 membar #Sync
261
262 ! ASI_HYP_SCRATCHPAD_2
263L23:
264 wr %g0, 0x4f, %asi
265 ldxa [%g0 + ASI_HYP_SCRATCHPAD_2] %asi, %g7
266 cmp %g7 , %g0
267 bne bad_trap
268 membar #Sync
269
270 ! ASI_HYP_SCRATCHPAD_3
271L24:
272 wr %g0, 0x4f, %asi
273 ldxa [%g0 + ASI_HYP_SCRATCHPAD_3] %asi, %g7
274 cmp %g7 , %g0
275 bne bad_trap
276 membar #Sync
277
278 ! ASI_HYP_SCRATCHPAD_4
279L25:
280 wr %g0, 0x4f, %asi
281 ldxa [%g0 + ASI_HYP_SCRATCHPAD_4] %asi, %g7
282 cmp %g7 , %g0
283 bne bad_trap
284 membar #Sync
285 ! ASI_HYP_SCRATCHPAD_5
286L26:
287 wr %g0, 0x4f, %asi
288 ldxa [%g0 + ASI_HYP_SCRATCHPAD_5] %asi, %g7
289 cmp %g7 , %g0
290 bne bad_trap
291 membar #Sync
292
293 ! ASI_HYP_SCRATCHPAD_6
294L27:
295 wr %g0, 0x4f, %asi
296 ldxa [%g0 + ASI_HYP_SCRATCHPAD_6] %asi, %g7
297 cmp %g7 , %g0
298 bne bad_trap
299 membar #Sync
300
301 ! ASI_HYP_SCRATCHPAD_7
302L28:
303 wr %g0, 0x4f, %asi
304 ldxa [%g0 + ASI_HYP_SCRATCHPAD_7] %asi, %g7
305 cmp %g7 , %g0
306 bne bad_trap
307 membar #Sync
308
309 ! ASI_IMMU_TAG_TARGET
310L29:
311 wr %g0, 0x50, %asi
312 ldxa [%g0 ] %asi, %g7
313 cmp %g7 , %g0
314 bne bad_trap
315 membar #Sync
316
317 ! ASI_IMMU_SFSR
318L30:
319 wr %g0, 0x50, %asi
320 ldxa [%g0 + ASI_IMMU_SFSR_VAL] %asi, %g7
321 cmp %g7 , %g0
322 bne bad_trap
323 membar #Sync
324
325 ! ASI_IMMU_TAG_ACCESS
326L31:
327 wr %g0, 0x50, %asi
328 ldxa [%g0 + ASI_IMMU_TAG_ACCESS_VAL] %asi, %g7
329 cmp %g7 , %g0
330 bne bad_trap
331 membar #Sync
332
333 ! ASI_IMMU_VA_WATCHPOINT
334L32:
335 wr %g0, 0x50, %asi
336 ldxa [%g0 + 0x38] %asi, %g7
337 cmp %g7 , %g0
338 bne bad_trap
339 membar #Sync
340
341 ! ASI_MMU_REAL_RANGE_0
342L33:
343 wr %g0, 0x52, %asi
344 ldxa [%g0 + ASI_MMU_REAL_RANGE_0] %asi, %g7
345 cmp %g7 , %g0
346 bne bad_trap
347 membar #Sync
348
349 ! ASI_MMU_REAL_RANGE_1
350L34:
351 wr %g0, 0x52, %asi
352 ldxa [%g0 + ASI_MMU_REAL_RANGE_1] %asi, %g7
353 cmp %g7 , %g0
354 bne bad_trap
355 membar #Sync
356
357 ! ASI_MMU_REAL_RANGE_2
358L35:
359 wr %g0, 0x52, %asi
360 ldxa [%g0 + ASI_MMU_REAL_RANGE_2] %asi, %g7
361 cmp %g7 , %g0
362 bne bad_trap
363 membar #Sync
364
365 ! ASI_MMU_REAL_RANGE_3
366L36:
367 wr %g0, 0x52, %asi
368 ldxa [%g0 + ASI_MMU_REAL_RANGE_3] %asi, %g7
369 cmp %g7 , %g0
370 bne bad_trap
371 membar #Sync
372
373 ! ASI_MMU_PHYSICAL_OFFSET_0
374L37:
375 wr %g0, 0x52, %asi
376 ldxa [%g0 + ASI_MMU_PHYSICAL_OFFSET_0] %asi, %g7
377 cmp %g7 , %g0
378 bne bad_trap
379 membar #Sync
380 ! ASI_MMU_PHYSICAL_OFFSET_1
381L38:
382 wr %g0, 0x52, %asi
383 ldxa [%g0 + ASI_MMU_PHYSICAL_OFFSET_1] %asi, %g7
384 cmp %g7 , %g0
385 bne bad_trap
386 membar #Sync
387
388 ! ASI_MMU_PHYSICAL_OFFSET_2
389L39:
390 wr %g0, 0x52, %asi
391 ldxa [%g0 + ASI_MMU_PHYSICAL_OFFSET_2] %asi, %g7
392 cmp %g7 , %g0
393 bne bad_trap
394 membar #Sync
395
396 ! ASI_MMU_PHYSICAL_OFFSET_3
397L40:
398 wr %g0, 0x52, %asi
399 ldxa [%g0 + ASI_MMU_PHYSICAL_OFFSET_3] %asi, %g7
400 cmp %g7 , %g0
401 bne bad_trap
402 membar #Sync
403
404 ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0
405L41:
406 wr %g0, 0x54, %asi
407 ldxa [%g0 + ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi, %g7
408 cmp %g7 , %g0
409 bne bad_trap
410 membar #Sync
411
412 ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1
413L42:
414 wr %g0, 0x54, %asi
415 ldxa [%g0 + ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi, %g7
416 cmp %g7 , %g0
417 bne bad_trap
418 membar #Sync
419
420 ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2
421L43:
422 wr %g0, 0x54, %asi
423 ldxa [%g0 + ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi, %g7
424 cmp %g7 , %g0
425 bne bad_trap
426 membar #Sync
427
428 ! ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3
429L44:
430 wr %g0, 0x54, %asi
431 ldxa [%g0 + ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi, %g7
432 cmp %g7 , %g0
433 bne bad_trap
434 membar #Sync
435
436 ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0
437L45:
438 wr %g0, 0x54, %asi
439 ldxa [%g0 + ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi, %g7
440 cmp %g7 , %g0
441 bne bad_trap
442 membar #Sync
443 ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1
444L46:
445 wr %g0, 0x54, %asi
446 ldxa [%g0 + ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi, %g7
447 cmp %g7 , %g0
448 bne bad_trap
449 membar #Sync
450
451 ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2
452L47:
453 wr %g0, 0x54, %asi
454 ldxa [%g0 + ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi, %g7
455 cmp %g7 , %g0
456 bne bad_trap
457 membar #Sync
458
459 ! ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3
460L48:
461 wr %g0, 0x54, %asi
462 ldxa [%g0 + ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi, %g7
463 cmp %g7 , %g0
464 bne bad_trap
465 membar #Sync
466
467 ! ASI_ITSB_PTR_0
468L49:
469 wr %g0, 0x54, %asi
470 ldxa [%g0 + ASI_ITSB_PTR_0] %asi, %g7
471 cmp %g7 , %g0
472 bne bad_trap
473 membar #Sync
474
475 ! ASI_ITSB_PTR_1
476L50:
477 wr %g0, 0x54, %asi
478 ldxa [%g0 + ASI_ITSB_PTR_1] %asi, %g7
479 cmp %g7 , %g0
480 bne bad_trap
481 membar #Sync
482
483 ! ASI_ITSB_PTR_2
484L51:
485 wr %g0, 0x54, %asi
486 ldxa [%g0 + ASI_ITSB_PTR_2] %asi, %g7
487 cmp %g7 , %g0
488 bne bad_trap
489 membar #Sync
490
491 ! ASI_ITSB_PTR_3
492L52:
493 wr %g0, 0x54, %asi
494 ldxa [%g0 + ASI_ITSB_PTR_3] %asi, %g7
495 cmp %g7 , %g0
496 bne bad_trap
497 membar #Sync
498
499 ! ASI_MMU_DTSB_PTR_0
500L53:
501 wr %g0, 0x54, %asi
502 ldxa [%g0 + ASI_DTSB_PTR_0] %asi, %g7
503 cmp %g7 , %g0
504 bne bad_trap
505 membar #Sync
506
507 ! ASI_MMU_DTSB_PTR_1
508L54:
509 wr %g0, 0x54, %asi
510 ldxa [%g0 + ASI_DTSB_PTR_1] %asi, %g7
511 cmp %g7 , %g0
512 bne bad_trap
513 membar #Sync
514
515 ! ASI_MMU_DTSB_PTR_2
516L55:
517 wr %g0, 0x54, %asi
518 ldxa [%g0 + ASI_DTSB_PTR_2] %asi, %g7
519 cmp %g7 , %g0
520 bne bad_trap
521 membar #Sync
522
523 ! ASI_MMU_DTSB_PTR_3
524L56:
525 wr %g0, 0x54, %asi
526 ldxa [%g0 + ASI_DTSB_PTR_3] %asi, %g7
527 cmp %g7 , %g0
528 bne bad_trap
529 membar #Sync
530
531 ! ASI_PENDING_TABLEWALK_CONTROL
532L57:
533 wr %g0, 0x54, %asi
534 ldxa [%g0 + 0x90] %asi, %g7
535 cmp %g7 , %g0
536 bne bad_trap
537 membar #Sync
538
539 ! ASI_PENDING_TABLEWALK_STATUS
540L58:
541 wr %g0, 0x54, %asi
542 ldxa [%g0 + 0x98] %asi, %g7
543 cmp %g7 , %g0
544 bne bad_trap
545 membar #Sync
546
547 ! ASI_DMMU_TAG_TARGET
548L59:
549 wr %g0, 0x58, %asi
550 ldxa [%g0 ] %asi, %g7
551 cmp %g7 , %g0
552 bne bad_trap
553 membar #Sync
554
555 ! ASI_DMMU_SFSR
556L60:
557 wr %g0, 0x58, %asi
558 ldxa [%g0 + ASI_DMMU_SFSR] %asi, %g7
559 cmp %g7 , %g0
560 bne bad_trap
561 membar #Sync
562
563 ! ASI_DMMU_SFAR
564L61:
565 wr %g0, 0x58, %asi
566 ldxa [%g0 + ASI_DMMU_SFAR] %asi, %g7
567 cmp %g7 , %g0
568 bne bad_trap
569 membar #Sync
570
571 ! ASI_DMMU_TAG_ACCESS
572L62:
573 wr %g0, 0x58, %asi
574 ldxa [%g0 + ASI_DMMU_TAG_ACCESS_VAL] %asi, %g7
575 cmp %g7 , %g0
576 bne bad_trap
577 membar #Sync
578
579L63:
580 wr %g0, 0x58, %asi
581 ldxa [%g0 + ASI_DMMU_VA_WATCHPOINT_VAL] %asi, %g7
582 cmp %g7 , %g0
583 bne bad_trap
584 membar #Sync
585
586 ! ASI_HWTW_CONFIG
587L64:
588 wr %g0, 0x58, %asi
589 ldxa [%g0 + 0x40] %asi, %g7
590 cmp %g7 , %g0
591 bne bad_trap
592 membar #Sync
593
594good_trap:
595 ba good_trap
596 nop
597 nop
598bad_trap:
599 ba bad_trap
600 nop
601
602
603
604/************************************************************************
605 Test case data start
606 ************************************************************************/
607.data
608.xword 0x0
609user_data_start:
610.end
611
Full OpenSPARC design & verification tarball including full HDL.