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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tcu / tcu_regs_peu.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tcu_regs_peu.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#define TEST_DATA0 0x4c3fdead4c3fbeef
42#define tmp1 %l2
43#define tmp2 %l3
44#define tmp3 %l4
45#define tmp4 %l5
46
47
48#include "asi_s.h"
49#include "mcu_defines.h"
50#include "tcu_defines.h"
51
52/************************************************************************
53 Test case code start
54 ************************************************************************/
55#ifdef FAST_BOOT
56#define RESET_VEC 0x0000000000000000
57#else
58#define RESET_VEC 0xfffffffff0000000
59#endif
60
61SECTION .RED_SEC TEXT_VA = RESET_VEC
62attr_text {
63 Name=.RED_SEC,
64 hypervisor
65}
66
67.text
68 nop
69 nop
70 nop
71 nop
72 nop
73 nop
74 nop
75 nop
76
77.global main
78
79
80
81 ! PEU Control
82L1:
83 set 0x101, %i3
84 setx 0x8800680000, %l5, %l6
85 ldx [%l6], %g3
86 cmp %g3, %i3
87 bne bad_trap
88 membar #Sync
89
90 ! PEU Ingress Credits Initial
91L2:
92 setx 0x10000200c0, tmp1, tmp2
93 setx 0x8800680000, %l5, %l6
94 add %l6, 0x18, %g7
95 ldx [%g7], %g3
96 cmp %g3, %l3
97 bne bad_trap
98 membar #Sync
99
100 ! PEU Other Event Log Enable
101L3:
102 set 0xffffff, %i3
103 setx 0x8800681000, %l5, %l6
104 ldx [%l6], %g3
105 cmp %g3, %i3
106 bne bad_trap
107 membar #Sync
108
109 ! PEU Other Event Status Clear
110L4:
111 setx 0x8800681000, %l5, %l6
112 add %l6, 0x018, %g7
113 ldx [%g7], %g3
114 cmp %g3, %g0
115 bne bad_trap
116 membar #Sync
117
118
119 ! PEU Other Event Status Set
120L5:
121 setx 0x8800681000, %l5, %l6
122 add %l6, 0x020, %g7
123 ldx [%g7], %g3
124 cmp %g3, %g0
125 bne bad_trap
126 membar #Sync
127
128 ! PEU Uncorrectable Error Log Enable
129L6:
130 set 0x17f011, %i3
131 setx 0x8800691000, %l5, %l6
132 ldx [%l6], %g3
133 cmp %g3, %i3
134 bne bad_trap
135 membar #Sync
136
137
138 ! PEU Uncorrectable Error Status Clear
139L7:
140 setx 0x8800691000, %l5, %l6
141 add %l6, 0x018, %g7
142 ldx [%g7], %g3
143 cmp %g3, %g0
144 bne bad_trap
145 membar #Sync
146
147 ! PEU Uncorrectable Error Status Set
148L8:
149 setx 0x8800691000, %l5, %l6
150 add %l6, 0x020, %g7
151 ldx [%g7], %g3
152 cmp %g3, %g0
153 bne bad_trap
154 membar #Sync
155
156 ! PEU Receive Uncorrectable Error Header1 Log
157L9:
158 setx 0x8800691000, %l5, %l6
159 add %l6, 0x028, %g7
160 ldx [%g7], %g3
161 cmp %g3, %g0
162 bne bad_trap
163 membar #Sync
164
165 ! PEU Receive Uncorrectable Error Header2 Log
166L10:
167 setx 0x8800691000, %l5, %l6
168 add %l6, 0x030, %g7
169 ldx [%g7], %g3
170 cmp %g3, %g0
171 bne bad_trap
172 membar #Sync
173
174 ! PEU Correctable Error Log Enable
175L11:
176 set 0x11c1, %i3
177 setx 0x88006a1000, %l5, %l6
178 ldx [%l6], %g3
179 cmp %g3, %i3
180 bne bad_trap
181 membar #Sync
182
183 ! PEU Correctable Error Status Clear
184L12:
185 setx 0x88006a1000, %l5, %l6
186 add %l6, 0x018, %g7
187 ldx [%g7], %g3
188 cmp %g3, %g0
189 bne bad_trap
190 membar #Sync
191
192 ! PEU Correctable Error Status Set
193L13:
194 setx 0x88006a1000, %l5, %l6
195 add %l6, 0x020, %g7
196 ldx [%g7], %g3
197 cmp %g3, %g0
198 bne bad_trap
199 membar #Sync
200
201 ! PEU DLPL/SERDES Revision
202L14:
203 setx 0x88006e2000, %l5, %l6
204 ldx [%l6], %g3
205 cmp %g3, %g0
206 bne bad_trap
207 membar #Sync
208
209 ! PEU DLPL Event/Errog Log Enable
210L15:
211 set 0xf03ffff, %i3
212 setx 0x88006e2000, %l5, %l6
213 add %l6, 0x108, %g7
214 ldx [%g7], %g3
215 cmp %g3, %i3
216 bne bad_trap
217 membar #Sync
218
219 ! PEU Serdes PLL Control/Status
220L16:
221 set 0x1, %i3
222 setx 0x88006e2000, %l5, %l6
223 add %l6, 0x200, %g7
224 ldx [%g7], %g3
225 cmp %g3, %i3
226 bne bad_trap
227 membar #Sync
228
229 ! PEU Serdes Receiver Lane 0 - 7 Control
230L17:
231 set 0x552, %i3
232 setx 0x88006e2000, %l5, %l6
233 add %l6, 0x338, %g7
234 ldx [%g7], %g3
235 cmp %g3, %i3
236 bne bad_trap
237 membar #Sync
238
239 ! PEU Serdes Transimitter Lane 0 - 7 Status
240L18:
241 set 0x1ec, %i3
242 setx 0x88006e2000, %l5, %l6
243 add %l6, 0x438, %g7
244 ldx [%g7], %g3
245 cmp %g3, %i3
246 bne bad_trap
247 membar #Sync
248
249 ! PEU Serdes Macro 0 - 1 Test Configuration
250L19:
251 set 0x3, %i3
252 setx 0x88006e2000, %l5, %l6
253 add %l6, 0x508, %g7
254 ldx [%g7], %g3
255 cmp %g3, %i3
256 bne bad_trap
257 membar #Sync
258
259
260good_trap:
261 ba good_trap
262 nop
263 nop
264bad_trap:
265 ba bad_trap
266 nop
267
268/************************************************************************
269 Test case data start
270 ************************************************************************/
271.data
272.xword 0x0
273user_data_start:
274.end
275
276
Full OpenSPARC design & verification tarball including full HDL.