[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_dekker2_pio.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tso_n1_dekker2_pio.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO
#define addrA_reg 			%o0
#define addrB_reg 			%o1
#define addrC_reg 			%o2
#define data_base_reg	  		%o3
#define to_reg	  			%o4
#define my_id_reg	  		%o5
#define global_cnt_reg	  		%o6

#define test_reg1	  		%i0
#define test_reg2	  		%i1

#define backoff_cnt	  		%i4
#define backoff_hlp1  			%i5


#define TIMEOUT 	  		0x100
#define ITERATIONS 	  		0x2

#include "hboot.s"

.global main
main:
ta T_CHANGE_HPRIV
nop
th_fork(th_main,%l0)

th_main_0:
	setx    addrA, 	%l0, addrA_reg			! 
	setx    addrB, 	%l0, addrB_reg			! 
	setx    addrC, 	%l0, addrC_reg			! 
        set     TIMEOUT,	to_reg         		! set timeout count 
	inc 	to_reg
	mov	to_reg, backoff_hlp1
	dec 	to_reg
        set     ITERATIONS,	global_cnt_reg 		! 
        mov     %g0, my_id_reg

        add     my_id_reg, 0x20, my_id_reg			! this is my ID address

getlock0:
        set     1, test_reg1       		! load the swap data register
        set     0x20, test_reg2       		! load the swap data register
        st    	test_reg1, [addrA_reg]		! try to acquire lock
        st    	test_reg2, [addrC_reg]		! try to acquire lock
	membar 0x40
        ld    	[addrC_reg], test_reg2
        ld    	[addrB_reg], test_reg1		! try to acquire lock
	tst	test_reg1
	be	gotlock0
        nop

	st	%g0,  [addrA_reg]		! release

        deccc   to_reg         			! dec timeout count
        bne     getlock0               		! branch if no timeout
        nop
        ba,a    bad_end
        nop

gotlock0:

	subcc	test_reg2, 0x20, %g0
	bne	bad_end
	nop

clearlock0:
        st        %g0, [addrA_reg]            	! lock value (0=unlocked)
	nop;nop;nop;nop;			! wait


	mov to_reg, backoff_cnt
backoff_loop01:
	nop;nop;nop;nop;			! backoff
	deccc backoff_cnt			
	bne backoff_loop01
	nop

        set     TIMEOUT, to_reg         		! set timeout count again

check_done0:
	deccc	global_cnt_reg
        be	good_end
	nop
	ba	getlock0
	nop


th_main_1:
         ba dekker_algo
th_main_2:
        ta T_GOOD_TRAP      
th_main_3:
        ta T_GOOD_TRAP      
th_main_4:
        ba  dekker_algo

dekker_algo:
	setx    addrA, 	%l0, addrA_reg			! 
	setx    addrB, 	%l0, addrB_reg			! 
	setx    addrC, 	%l0, addrC_reg			! 
        set     TIMEOUT,	to_reg         		! set timeout count 
	inc 	to_reg
	mov	to_reg, backoff_hlp1
	dec 	to_reg
        set     ITERATIONS,	global_cnt_reg 		! 
        mov     %g0, my_id_reg

        add     my_id_reg, 0x24, my_id_reg

getlock1:
        set     1, test_reg1       		! load the swap data register
        set     0x21, test_reg2       		! load the swap data register
        st    	test_reg1, [addrB_reg]		! try to acquire lock
        st    	test_reg2, [addrC_reg]		! try to acquire lock
	membar 0x40
        ld    	[addrC_reg], test_reg2
        ld    	[addrA_reg], test_reg1		! try to acquire lock
	tst	test_reg1
	be	gotlock1
        nop

	st	%g0,  [addrB_reg]			! release

	sub backoff_hlp1, to_reg, backoff_cnt
backoff_loop10:
	nop;nop;nop;nop;			! wait - quasi exponential backoff
	deccc backoff_cnt			! well, kinda linear.
	bne backoff_loop10
	nop

        deccc   to_reg          			! dec timeout count
        bne     getlock1                 		! branch if no timeout
        nop
        ba,a    bad_end
        nop

gotlock1:
	subcc	test_reg2, 0x21, %g0
	bne	bad_end
	nop

clearlock1:
        st        %g0, [addrB_reg]            		! lock value (0=unlocked)

        set     TIMEOUT, to_reg         		! set timeout count again

check_done1:
	deccc	global_cnt_reg
        be	good_end
	nop
	ba	getlock1
	nop

good_end:
        ta      T_GOOD_TRAP
bad_end:
        ta      T_BAD_TRAP


!==========================


SECTION .MY_DATA0  DATA_VA=0xd0100000
attr_data {
        Name = .MY_DATA0,
        VA= 0x0d0100000
        RA=0xc000000000,
        PA=0xc000000000,
        part_0_ctx_nonzero_tsb_config_0,
        TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
        }

	.data

.global addrA
.align 0x4
addrA:
	.word	0x0

.skip 0x1000


SECTION .MY_DATA1  DATA_VA=0xd1110000
attr_data {
        Name = .MY_DATA1,
        VA= 0x0d1110000,
        RA=0xc200000000,
        PA=0xc200000000,
        part_0_ctx_nonzero_tsb_config_1,
        TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
        }

	.data
.global addrB
.global addrC
.align 0x4
addrB:
	.word	0x0
.skip 0x1000
.align 0x4
addrC:
	.word	0x0

.global protected_area
protected_area:
	.word	0xbeef
	.skip 0x1000
	.word	0xbeef
	
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tso_n1_dekker2_pio.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39	#define addrA_reg %o0
	40	#define addrB_reg %o1
	41	#define addrC_reg %o2
	42	#define data_base_reg %o3
	43	#define to_reg %o4
	44	#define my_id_reg %o5
	45	#define global_cnt_reg %o6
	46
	47	#define test_reg1 %i0
	48	#define test_reg2 %i1
	49
	50	#define backoff_cnt %i4
	51	#define backoff_hlp1 %i5
	52
	53
	54	#define TIMEOUT 0x100
	55	#define ITERATIONS 0x2
	56
	57	#include "hboot.s"
	58
	59	.global main
	60	main:
	61	ta T_CHANGE_HPRIV
	62	nop
	63	th_fork(th_main,%l0)
	64
65	th_main_0:
66	setx addrA, %l0, addrA_reg !
67	setx addrB, %l0, addrB_reg !
68	setx addrC, %l0, addrC_reg !
69	set TIMEOUT, to_reg ! set timeout count
70	inc to_reg
71	mov to_reg, backoff_hlp1
72	dec to_reg
73	set ITERATIONS, global_cnt_reg !
74	mov %g0, my_id_reg
75
76	add my_id_reg, 0x20, my_id_reg ! this is my ID address
77
78	getlock0:
79	set 1, test_reg1 ! load the swap data register
80	set 0x20, test_reg2 ! load the swap data register
81	st test_reg1, [addrA_reg] ! try to acquire lock
82	st test_reg2, [addrC_reg] ! try to acquire lock
83	membar 0x40
84	ld [addrC_reg], test_reg2
85	ld [addrB_reg], test_reg1 ! try to acquire lock
86	tst test_reg1
87	be gotlock0
88	nop
89
90	st %g0, [addrA_reg] ! release
91
92	deccc to_reg ! dec timeout count
93	bne getlock0 ! branch if no timeout
94	nop
95	ba,a bad_end
96	nop
97
98	gotlock0:
99
100	subcc test_reg2, 0x20, %g0
101	bne bad_end
102	nop
103
104	clearlock0:
105	st %g0, [addrA_reg] ! lock value (0=unlocked)
106	nop;nop;nop;nop; ! wait
107
108
109	mov to_reg, backoff_cnt
110	backoff_loop01:
111	nop;nop;nop;nop; ! backoff
112	deccc backoff_cnt
113	bne backoff_loop01
114	nop
115
116	set TIMEOUT, to_reg ! set timeout count again
117
118	check_done0:
119	deccc global_cnt_reg
120	be good_end
121	nop
122	ba getlock0
123	nop
124
125
126	th_main_1:
127	ba dekker_algo
128	th_main_2:
129	ta T_GOOD_TRAP
130	th_main_3:
131	ta T_GOOD_TRAP
132	th_main_4:
133	ba dekker_algo
134
135	dekker_algo:
136	setx addrA, %l0, addrA_reg !
137	setx addrB, %l0, addrB_reg !
138	setx addrC, %l0, addrC_reg !
139	set TIMEOUT, to_reg ! set timeout count
140	inc to_reg
141	mov to_reg, backoff_hlp1
142	dec to_reg
143	set ITERATIONS, global_cnt_reg !
144	mov %g0, my_id_reg
145
146	add my_id_reg, 0x24, my_id_reg
147
148	getlock1:
149	set 1, test_reg1 ! load the swap data register
150	set 0x21, test_reg2 ! load the swap data register
151	st test_reg1, [addrB_reg] ! try to acquire lock
152	st test_reg2, [addrC_reg] ! try to acquire lock
153	membar 0x40
154	ld [addrC_reg], test_reg2
155	ld [addrA_reg], test_reg1 ! try to acquire lock
156	tst test_reg1
157	be gotlock1
158	nop
159
160	st %g0, [addrB_reg] ! release
161
162	sub backoff_hlp1, to_reg, backoff_cnt
163	backoff_loop10:
164	nop;nop;nop;nop; ! wait - quasi exponential backoff
165	deccc backoff_cnt ! well, kinda linear.
166	bne backoff_loop10
167	nop
168
169	deccc to_reg ! dec timeout count
170	bne getlock1 ! branch if no timeout
171	nop
172	ba,a bad_end
173	nop
174
175	gotlock1:
176	subcc test_reg2, 0x21, %g0
177	bne bad_end
178	nop
179
180	clearlock1:
181	st %g0, [addrB_reg] ! lock value (0=unlocked)
182
183	set TIMEOUT, to_reg ! set timeout count again
184
185	check_done1:
186	deccc global_cnt_reg
187	be good_end
188	nop
189	ba getlock1
190	nop
191
192	good_end:
193	ta T_GOOD_TRAP
194	bad_end:
195	ta T_BAD_TRAP
196
197
198	!==========================
199
200
201	SECTION .MY_DATA0 DATA_VA=0xd0100000
202	attr_data {
203	Name = .MY_DATA0,
204	VA= 0x0d0100000
205	RA=0xc000000000,
206	PA=0xc000000000,
207	part_0_ctx_nonzero_tsb_config_0,
208	TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
209	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
210	TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
211	}
212
213	.data
214
215	.global addrA
216	.align 0x4
217	addrA:
218	.word 0x0
219
220	.skip 0x1000
221
222
223	SECTION .MY_DATA1 DATA_VA=0xd1110000
224	attr_data {
225	Name = .MY_DATA1,
226	VA= 0x0d1110000,
227	RA=0xc200000000,
228	PA=0xc200000000,
229	part_0_ctx_nonzero_tsb_config_1,
230	TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
231	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
232	TTE_L=0, TTE_CP=1, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
233	}
234
235	.data
236	.global addrB
237	.global addrC
238	.align 0x4
239	addrB:
240	.word 0x0
241	.skip 0x1000
242	.align 0x4
243	addrC:
244	.word 0x0
245
246	.global protected_area
247	protected_area:
248	.word 0xbeef
249	.skip 0x1000
250	.word 0xbeef
251
252	.end