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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_evict_fanout_dc1_8c.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tso_n1_evict_fanout_dc1_8c.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_BASE_DATA_ADDR 0x160000
39#define MAIN_BASE_TEXT_ADDR 0x150000
40#define MAIN_BASE_DATA_ADDR_RA 0x100160000
41#define MAIN_BASE_TEXT_ADDR_RA 0x100150000
42
43#define DATA2_BASE_DATA_ADDR 0x960000
44#define DATA2_BASE_DATA_ADDR_RA 0x100960000
45
46#define USER_PAGE_CUSTOM_MAP
47
48#define data_base_reg1 %o1
49#define data_base_reg2 %o2
50
51#define my_id_reg %l1
52#define test_reg %l2
53#define counter_reg %l3
54#define tmp1 %l4
55#define tmp2 %l5
56#define tmp3 %l6
57
58#define ITERATIONS 0x1
59
60#include "hboot.s"
61
62SECTION .MAIN TEXT_VA=0x150000, DATA_VA=0x160000
63
64attr_text {
65 Name = .MAIN,
66 VA=MAIN_BASE_TEXT_ADDR,
67 RA=MAIN_BASE_TEXT_ADDR_RA,
68 PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
69part_0_ctx_nonzero_tsb_config_0,
70 TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
71 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
72 TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
73 }
74attr_data {
75 Name = .MAIN,
76 VA=MAIN_BASE_DATA_ADDR,
77 RA=MAIN_BASE_DATA_ADDR_RA,
78 PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
79part_0_ctx_nonzero_tsb_config_0,
80 TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
81 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
82 TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
83 }
84
85.text
86.global main
87main:
88
89 set ITERATIONS, counter_reg
90 add %g0, 0x100, my_id_reg
91
92th_fork(th_main,%l0)
93
94th_main_0:
95 add my_id_reg, 0x00, my_id_reg ! this is my ID address
96 ba go; nop
97th_main_1:
98 add my_id_reg, 0x04, my_id_reg
99 ba go; nop
100th_main_2:
101 add my_id_reg, 0x08, my_id_reg
102 ba go; nop
103th_main_3:
104 add my_id_reg, 0x0c, my_id_reg
105 ba go; nop
106th_main_4:
107 add my_id_reg, 0x10, my_id_reg
108 ba go; nop
109th_main_5:
110 add my_id_reg, 0x14, my_id_reg
111 ba go; nop
112th_main_6:
113 add my_id_reg, 0x18, my_id_reg
114 ba go; nop
115th_main_7:
116 add my_id_reg, 0x1c, my_id_reg
117 ba go; nop
118th_main_8:
119 add my_id_reg, 0x20, my_id_reg
120 ba go; nop
121th_main_9:
122 add my_id_reg, 0x24, my_id_reg
123 ba go; nop
124th_main_10:
125 add my_id_reg, 0x28, my_id_reg
126 ba go; nop
127th_main_11:
128 add my_id_reg, 0x2c, my_id_reg
129 ba go; nop
130th_main_12:
131 add my_id_reg, 0x30, my_id_reg
132 ba go; nop
133th_main_13:
134 add my_id_reg, 0x34, my_id_reg
135 ba go; nop
136th_main_14:
137 add my_id_reg, 0x38, my_id_reg
138 ba go; nop
139th_main_15:
140 add my_id_reg, 0x3c, my_id_reg
141 ba go; nop
142th_main_16:
143 add my_id_reg, 0x40, my_id_reg
144 ba go; nop
145th_main_17:
146 add my_id_reg, 0x44, my_id_reg
147 ba go; nop
148th_main_18:
149 add my_id_reg, 0x48, my_id_reg
150 ba go; nop
151th_main_19:
152 add my_id_reg, 0x4c, my_id_reg
153 ba go; nop
154th_main_20:
155 add my_id_reg, 0x50, my_id_reg
156 ba go; nop
157th_main_21:
158 add my_id_reg, 0x54, my_id_reg
159 ba go; nop
160th_main_22:
161 add my_id_reg, 0x58, my_id_reg
162 ba go; nop
163th_main_23:
164 add my_id_reg, 0x5c, my_id_reg
165 ba go; nop
166th_main_24:
167 add my_id_reg, 0x60, my_id_reg
168 ba go; nop
169th_main_25:
170 add my_id_reg, 0x64, my_id_reg
171 ba go; nop
172th_main_26:
173 add my_id_reg, 0x68, my_id_reg
174 ba go; nop
175th_main_27:
176 add my_id_reg, 0x6c, my_id_reg
177 ba go; nop
178th_main_28:
179 add my_id_reg, 0x70, my_id_reg
180 ba go; nop
181th_main_29:
182 add my_id_reg, 0x74, my_id_reg
183 ba go; nop
184th_main_30:
185 add my_id_reg, 0x78, my_id_reg
186 ba go; nop
187th_main_31:
188 add my_id_reg, 0x7c, my_id_reg
189 ba go; nop
190
191go:
192 setx protected_area, %l0, data_base_reg1 ! the data area
193 setx protected_area2,%l0, data_base_reg2 ! the data area2
194
195loop:
196 ld [data_base_reg1], test_reg ! read the data area
197#ifdef EVICT4
198 ld [data_base_reg1 + 0x10], test_reg ! read the data area
199 ld [data_base_reg1 + 0x20], test_reg ! read the data area
200 ld [data_base_reg1 + 0x30], test_reg ! read the data area
201#endif
202#ifdef EVICT3
203 ld [data_base_reg1 + 0x20], test_reg ! read the data area
204 ld [data_base_reg1 + 0x30], test_reg ! read the data area
205#endif
206#ifdef EVICT2
207 ld [data_base_reg1 + 0x30], test_reg ! read the data area
208#endif
209
210 set barrier_code,%i0 ! all thread meet here
211 jmpl %i0,%o7
212 nop
213
214 sub my_id_reg, 0x100, tmp1 ! thread 0 executes
215 brz tmp1, evict ! an evicting load
216 nop
217goon: ! proceed or end
218 dec counter_reg
219 brz counter_reg, good_end
220 nop
221 ba loop
222 nop
223
224evict: ! this aliases
225 ba goon ! data area and thus
226 ld [data_base_reg2], test_reg ! evicts
227
228!--------------------------------------------------------------------------
229
230barrier_code:
231 setx barrier_data, tmp1, tmp2
232bloop1: ! lock the barrier count
233 mov my_id_reg, tmp1
234 cas [tmp2], %g0, tmp1
235 brnz tmp1, bloop1
236#ifdef PREFETCH
237 prefetch [tmp2], #n_reads
238#else
239 nop
240#endif
241
242 ld [tmp2 + 4], tmp3 ! increment
243 inc tmp3
244 st tmp3, [tmp2 + 4]
245
246 st %g0, [tmp2] ! unlock
247bloop2:
248 ld [tmp2 + 4], tmp3
249 brz tmp3, bout2 ! barrier already reset
250 sub tmp3, THREAD_COUNT, tmp3 ! subtract THREAD_COUNT
251 brnz tmp3, bloop2 ! if 0 we are out.
252#ifdef PREFETCH
253 prefetch [tmp2], #n_reads
254#else
255 nop
256#endif
257
258 st %g0, [tmp2 + 4] ! clear the barrier counter
259bout2:
260 jmpl %o7+8, %g0 ! return
261 nop
262
263good_end:
264 ta T_GOOD_TRAP
265bad_end:
266 ta T_BAD_TRAP
267
268!==========================
269
270 .data
271.global protected_area
272protected_area:
273 .word 0xbee1
274 .skip 0x1000
275 .word 0xbee1
276
277SECTION .DATA2 DATA_VA=0x960000
278
279attr_data {
280 Name = .DATA2,
281 VA=DATA2_BASE_DATA_ADDR,
282 RA=DATA2_BASE_DATA_ADDR_RA,
283 PA=ra2pa(DATA2_BASE_DATA_ADDR_RA,0),
284part_0_ctx_nonzero_tsb_config_0,
285 TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
286 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
287 TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
288 }
289
290.data
291.global protected_area2
292protected_area2:
293 .word 0xbee2
294 .skip 0x400
295.global barrier_data
296barrier_data:
297 .word 0x0
298 .word 0x0
299.end
Full OpenSPARC design & verification tarball including full HDL.