Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_mutex4_casx.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tso_n1_mutex4_casx.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
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* ========== Copyright Header End ============================================
*/
#define spinlock_addr_reg  		%o0
#define data_base_reg	  		%o1
#define to_reg	  			%o2
#define my_id_reg	  		%o3
#define test_reg	  		%o4
#define global_cnt_reg	  		%o5

#define TIMEOUT 	  		0x1000
#define ITERATIONS 	  		0x4

#if defined CREGS_LSU_CTL_REG_DC  && CREGS_LSU_CTL_REG_DC == 0
#define TIMEOUT                         0x2000
#define ITERATIONS                      0x1
#endif

#if defined CREGS_LSU_CTL_REG_IC  && CREGS_LSU_CTL_REG_IC == 0
#define TIMEOUT                         0x2000
#define ITERATIONS                      0x1
#endif

#if defined CREGS_L2_CTL_REG_DIS  && CREGS_L2_CTL_REG_DIS == 1
#define TIMEOUT                         0x2000
#define ITERATIONS                      0x1
#endif

#include "hboot.s"

.global main

main:

	wr %g0, 0x4, %fprs         			! make sure fef is 1
	setx spinlock_address, %l0, spinlock_addr_reg	! spinlock address
        set  TIMEOUT, to_reg         			! set timeout count 
        set  ITERATIONS, global_cnt_reg

        or      spinlock_addr_reg, %g0, my_id_reg

th_fork(th_main,%l0)

th_main_0:
        add     my_id_reg, 0x20, my_id_reg		! my ID address
	stb	my_id_reg, [my_id_reg]			! store my ID there
	ba	getlock
	nop

th_main_1:
        add     my_id_reg, 0x24, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop


th_main_2:
        add     my_id_reg, 0x28, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop

th_main_3:
        add     my_id_reg, 0x2c, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop

th_main_4:
        add     my_id_reg, 0x30, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop

th_main_5:
        add     my_id_reg, 0x34, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop

th_main_6:
        add     my_id_reg, 0x38, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop

th_main_7:
        add     my_id_reg, 0x3c, my_id_reg
	stb	my_id_reg, [my_id_reg]
	ba	getlock
	nop

getlock:
        deccc   to_reg          			! dec timeout count
        be      bad_end                 		! branch if no timeout
        nop
        or      %g0, my_id_reg, test_reg       
        casx    [spinlock_addr_reg], %g0, test_reg	! try to acquire lock
        tst     test_reg                       		! did we get it?
        bne     getlock
        nop

gotlock:						! do something
        set     TIMEOUT, to_reg         		! set to count again
	setx    protected_area,	%l0, data_base_reg	! the data area

	set 	10, %l0
loop1:
	ld 	[my_id_reg], %f16			! read the ID
	st 	%f16, [data_base_reg]  			! store my ID in there
	add	data_base_reg, 8, data_base_reg 	! increment the address
	deccc	%l0
	bne 	loop1					! repeat
	nop

	set 	10, %l0
loop2:
	sub	data_base_reg, 8, data_base_reg 
	ld 	[my_id_reg], %f16			! read the ID
	ld 	[data_base_reg], %f0			! read the data area
	fcmps 	%fcc0, %f0, %f16 			! should be my ID
	fbne	%fcc0, bad_end
	nop
	deccc	%l0					! repeat
	bne 	loop2
	nop

clearlock:
        stx        %g0, [spinlock_addr_reg]		! unlock

check_done:						! finish or iterate
	deccc	global_cnt_reg
        be	good_end
	nop
	ba	getlock
	nop

good_end:
        ta      T_GOOD_TRAP
bad_end:
        ta      T_BAD_TRAP

!==========================
	.data

user_data_start:

spinlock_address:
	.word	0x0
	.skip 0x1000
protected_area:
	.word	0xbeef
	.skip 0x1000
	.word	0xbeef