Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | : |
2 | :#define addrA_reg %l0 | |
3 | :#define turn_reg %l1 | |
4 | :#define data_base_reg %l2 | |
5 | :#define my_id_reg %l4 | |
6 | :#define global_cnt_reg %l5 | |
7 | :#define prot_area_reg %l6 | |
8 | : | |
9 | :#define test_reg1 %i0 | |
10 | :#define test_reg2 %i1 | |
11 | :#define test_reg3 %i3 | |
12 | : | |
13 | :#define TIMEOUT 0x1000 | |
14 | :#define ITERATIONS 0x10 | |
15 | : | |
16 | :#include "hboot.s" | |
17 | : | |
18 | :.global main | |
19 | :main: | |
20 | : | |
21 | :th_fork(th_main,test_reg1) | |
22 | : | |
23 | $proc_num = 8; | |
24 | if(scalar(@ARGV)){ | |
25 | $proc_num = $ARGV[0]; | |
26 | } | |
27 | for ( $c = 0; $c < $proc_num; $c++ ){ | |
28 | $offs = 4 * $c; # threads own address offset | |
29 | ||
30 | :th_main_${c}: | |
31 | : setx addrA, test_reg1, addrA_reg ! | |
32 | : setx turn, test_reg1, turn_reg ! | |
33 | : setx prot_area, test_reg1, prot_area_reg ! | |
34 | : set ITERATIONS, global_cnt_reg | |
35 | : set ${c}, my_id_reg ! store my ID | |
36 | : | |
37 | :claim${c}: | |
38 | : set 1, test_reg1 ! store 1 in lock area | |
39 | : st test_reg1, [addrA_reg + ${offs}] | |
40 | ||
41 | :giveturnaway${c}: ! That's the essence | |
42 | $next = ($c + 1) % ${proc_num}; | |
43 | : set ${next}, test_reg1 ! of Peterson | |
44 | : st test_reg1, [turn_reg] ! to give the turn away | |
45 | : membar 0x40 ! THAT's IMPORTANT! | |
46 | : | |
47 | :getlock${c}: ! try to get lock | |
48 | : ld [turn_reg + 0x8], test_reg1 | |
49 | : sub test_reg1, 0x55, test_reg1 ! check for end of test | |
50 | : brz test_reg1, good_end | |
51 | : nop | |
52 | : | |
53 | : mov %g0, test_reg2 ! while flags are busy | |
54 | : ! AND turn is not mine | |
55 | : ! WAIT! | |
56 | for ( $k = 0; $k < ${proc_num} * 4; $k = $k + 4) { | |
57 | : ld [addrA_reg + ${k}], test_reg1 ! accumulate flags | |
58 | : add test_reg1, test_reg2, test_reg2 ! in test_reg2 | |
59 | } | |
60 | : subcc test_reg2, 0x1, %g0 ! if 1 -> not busy | |
61 | : be gotlock${c} | |
62 | : nop | |
63 | : | |
64 | :wait_turn${c}: | |
65 | : ld [turn_reg], test_reg3 ! read the turn reg. | |
66 | : subcc my_id_reg, test_reg3, %g0 ! and check | |
67 | : bne getlock${c} | |
68 | : nop | |
69 | : | |
70 | :gotlock${c}: ! do something | |
71 | : ld [prot_area_reg], test_reg1 | |
72 | : inc test_reg1 | |
73 | : st test_reg1, [prot_area_reg] | |
74 | : | |
75 | : ld [prot_area_reg + 0xc], test_reg1 | |
76 | : inc test_reg1 | |
77 | : st test_reg1, [prot_area_reg + 0xc] | |
78 | : | |
79 | : ld [prot_area_reg + 0x10], test_reg1 | |
80 | : inc test_reg1 | |
81 | : st test_reg1, [prot_area_reg + 0x10] | |
82 | : | |
83 | : ld [prot_area_reg + 0x1c], test_reg1 | |
84 | : inc test_reg1 | |
85 | : st test_reg1, [prot_area_reg + 0x1c] | |
86 | : | |
87 | : ld [prot_area_reg + 0x20], test_reg1 | |
88 | : inc test_reg1 | |
89 | : st test_reg1, [prot_area_reg + 0x20] | |
90 | : | |
91 | :clearlock${c}: | |
92 | : st %g0, [addrA_reg + ${offs}] ! release... | |
93 | : set ${next}, test_reg1 | |
94 | : st test_reg1, [turn_reg] | |
95 | : | |
96 | if($c == $proc_num -1){ | |
97 | : deccc global_cnt_reg ! iterate | |
98 | : bne claim${c} | |
99 | : nop | |
100 | : set 0x55, test_reg1 | |
101 | : st test_reg1, [turn_reg + 0x8] | |
102 | : ba good_end | |
103 | : nop | |
104 | } | |
105 | else{ | |
106 | : ba claim${c} | |
107 | : nop | |
108 | } | |
109 | } | |
110 | :!--------------------------------------------------------------------- | |
111 | : | |
112 | :good_end: | |
113 | : ta T_GOOD_TRAP | |
114 | :bad_end: | |
115 | : ta T_BAD_TRAP | |
116 | : | |
117 | :!========================== | |
118 | : | |
119 | : | |
120 | :SECTION .MY_DATA0 TEXT_VA=0xf0100000, DATA_VA=0xd0100000 | |
121 | :attr_data { | |
122 | : Name = .MY_DATA0, | |
123 | : VA= 0x0d0100000 | |
124 | : RA= 0x1d0100000 | |
125 | : PA= ra2pa(0x1d0100000,0), | |
126 | : part_0_ctx_nonzero_tsb_config_0, | |
127 | : TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0, | |
128 | : TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, | |
129 | : TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 | |
130 | : } | |
131 | : | |
132 | :attr_text { | |
133 | : Name = .MY_DATA0, | |
134 | : VA= 0x0f0100000 | |
135 | : RA= 0x1f0100000 | |
136 | : PA= ra2pa(0x1f0100000,0), | |
137 | : part_0_ctx_nonzero_tsb_config_0, | |
138 | : TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0, | |
139 | : TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, | |
140 | : TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 | |
141 | : } | |
142 | : | |
143 | : .data | |
144 | : | |
145 | :.global addrA | |
146 | :.global turn | |
147 | :.align 0x4 | |
148 | :addrA: | |
149 | for ( $k = 0; $k < 32; $k++) { | |
150 | : .word 0x0 | |
151 | : .word 0x0 | |
152 | } | |
153 | : | |
154 | :.skip 0x1000 | |
155 | :.align 0x4 | |
156 | :turn: | |
157 | : .word 0x0 | |
158 | : .word 0x0 | |
159 | : .word 0x0 | |
160 | : .word 0x0 | |
161 | : | |
162 | :SECTION .MY_DATA1 TEXT_VA=0xf1110000, DATA_VA=0xd1110000 | |
163 | :attr_data { | |
164 | : Name = .MY_DATA1, | |
165 | : VA= 0x0d1110000, | |
166 | : RA= 0x1d1110000, | |
167 | : PA= ra2pa(0x1d1110000,0), | |
168 | : part_0_ctx_nonzero_tsb_config_0, | |
169 | : TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0, | |
170 | : TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, | |
171 | : TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 | |
172 | : } | |
173 | : | |
174 | :attr_text { | |
175 | : Name = .MY_DATA1, | |
176 | : VA= 0x0f1110000, | |
177 | : RA= 0x1f1110000, | |
178 | : PA= ra2pa(0x1f1110000,0), | |
179 | : part_0_ctx_nonzero_tsb_config_0, | |
180 | : TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0, | |
181 | : TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0, | |
182 | : TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1 | |
183 | : } | |
184 | : | |
185 | : .data | |
186 | :.global prot_area | |
187 | :prot_area: | |
188 | : .word 0xbeef | |
189 | : .skip 0x1000 | |
190 | : .word 0xbeef | |
191 | : | |
192 | :.end |