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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_peterson3.pal
CommitLineData
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AT		 1:
2:#define addrA_reg %l0
3:#define turn_reg %l1
4:#define data_base_reg %l2
5:#define my_id_reg %l4
6:#define global_cnt_reg %l5
7:#define prot_area_reg %l6
8:
9:#define test_reg1 %i0
10:#define test_reg2 %i1
11:#define test_reg3 %i2
12:#define temp_reg1 %i3
13:
14:#define TIMEOUT 0x1000
15:#define ITERATIONS 0x10
16:
17:#include "hboot.s"
18:
19:.global main
20:main:
21:
22:th_fork(th_main,test_reg1)
23:
24$proc_num = 8;
25if(scalar(@ARGV)){
26 $proc_num = $ARGV[0];
27}
28for ( $c = 0; $c < $proc_num; $c++ ){
29$offs = 4 * $c; # thread's own offset
30
31:th_main_${c}:
32: setx addrA, test_reg1, addrA_reg
33: add addrA_reg, ${offs}, temp_reg1
34: setx turn, test_reg1, turn_reg
35: setx prot_area, test_reg1, prot_area_reg
36: set ITERATIONS, global_cnt_reg
37: set ${c}, my_id_reg ! store my ID
38:
39:claim${c}:
40: set 1, test_reg1 ! store 1 into lock
41
42:giveturnaway${c}:
43$next = ($c + 1) % ${proc_num};
44: set ${next}, test_reg1
45: st test_reg1, [turn_reg]
46: cas [temp_reg1], %g0, test_reg1 ! use CAS here
47:
48:getlock${c}:
49: ld [turn_reg + 0x8], test_reg1
50: sub test_reg1, 0x55, test_reg1
51: brz test_reg1, good_end
52: nop
53: mov %g0, test_reg2 ! while flags are busy
54: ! AND turn is not mine
55: ! WAIT
56for ( $k = 0; $k < ${proc_num} * 4; $k = $k + 4) {
57: ld [addrA_reg + ${k}], test_reg1 ! accumulate flags
58: add test_reg1, test_reg2, test_reg2 ! in test_reg2
59}
60: subcc test_reg2, 0x1, %g0 ! if 1 -> not busy
61: be gotlock${c}
62: nop
63:
64:wait_turn${c}:
65: ld [turn_reg], test_reg3 ! read the turn reg.
66: subcc my_id_reg, test_reg3, %g0 ! and check
67: bne getlock${c}
68: nop
69:
70:gotlock${c}: ! do something
71: ld [prot_area_reg], test_reg1
72: inc test_reg1
73: st test_reg1, [prot_area_reg]
74:
75: ld [prot_area_reg + 0xc], test_reg1
76: inc test_reg1
77: st test_reg1, [prot_area_reg + 0xc]
78:
79: ld [prot_area_reg + 0x10], test_reg1
80: inc test_reg1
81: st test_reg1, [prot_area_reg + 0x10]
82:
83: ld [prot_area_reg + 0x1c], test_reg1
84: inc test_reg1
85: st test_reg1, [prot_area_reg + 0x1c]
86:
87: ld [prot_area_reg + 0x20], test_reg1
88: inc test_reg1
89: st test_reg1, [prot_area_reg + 0x20]
90:
91:clearlock${c}:
92: st %g0, [addrA_reg + ${offs}] ! release...
93: set ${next}, test_reg1
94: st test_reg1, [turn_reg]
95:
96if($c == $proc_num -1){
97: deccc global_cnt_reg
98: bne claim${c}
99: nop
100: set 0x55, test_reg1
101: st test_reg1, [turn_reg + 0x8]
102: ba good_end
103: nop
104}
105else{
106: ba claim${c}
107: nop
108}
109}
110:!---------------------------------------------------------------------
111:
112:good_end:
113: ta T_GOOD_TRAP
114:bad_end:
115: ta T_BAD_TRAP
116:
117:!==========================
118:
119:
120:SECTION .MY_DATA0 TEXT_VA=0xf0100000, DATA_VA=0xd0100000
121:attr_data {
122: Name = .MY_DATA0,
123: VA= 0x0d0100000
124: RA= 0x1d0100000
125: PA= ra2pa(0x1d0100000,0),
126: part_0_ctx_nonzero_tsb_config_0,
127: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
128: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
129: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
130: }
131:
132:attr_text {
133: Name = .MY_DATA0,
134: VA= 0x0f0100000
135: RA= 0x1f0100000
136: PA= ra2pa(0x1f0100000,0),
137: part_0_ctx_nonzero_tsb_config_0,
138: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
139: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
140: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
141: }
142:
143: .data
144:
145:.global addrA
146:.global turn
147:.align 0x4
148:addrA:
149for ( $k = 0; $k < 32; $k++) {
150: .word 0x0
151: .word 0x0
152}
153:
154:.skip 0x1000
155:.align 0x4
156:turn:
157: .word 0x0
158: .word 0x0
159: .word 0x0
160:
161:SECTION .MY_DATA1 TEXT_VA=0xf1110000, DATA_VA=0xd1110000
162:attr_data {
163: Name = .MY_DATA1,
164: VA= 0x0d1110000,
165: RA= 0x1d1110000,
166: PA= ra2pa(0x1d1110000,0),
167: part_0_ctx_nonzero_tsb_config_0,
168: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
169: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
170: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
171: }
172:
173:attr_text {
174: Name = .MY_DATA1,
175: VA= 0x0f1110000,
176: RA= 0x1f1110000,
177: PA= ra2pa(0x1f1110000,0),
178: part_0_ctx_nonzero_tsb_config_0,
179: TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
180: TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
181: TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
182: }
183:
184: .data
185:.global prot_area
186:prot_area:
187: .word 0xbeef
188: .skip 0x1000
189: .word 0xbeef
190:
191:.end
Full OpenSPARC design & verification tarball including full HDL.