Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_prod_cons1_pio.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tso_n1_prod_cons1_pio.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
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32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
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35*
36* ========== Copyright Header End ============================================
37*/
38#define JBI_CONFIG
39#define MAIN_PAGE_HV_ALSO
40#define spinlock_addr_reg %o0
41#define data_base_reg %o1
42#define my_id_reg %o3
43#define test_reg %o4
44#define global_cnt_reg %o5
45#define tmp1 %l1
46
47#define ITERATIONS 0x2
48
49#include "hboot.s"
50
51.global main
52
53main:
54ta T_CHANGE_HPRIV
55nop
56
57 setx spinlock_address, %l0, spinlock_addr_reg ! spinlock address
58 set ITERATIONS, global_cnt_reg !
59
60th_fork(th_main,%l0)
61
62! Some of the threads are producers, some are consumers
63! A pair of producer and consumer has the same ID.
64!=====================================================
65th_main_0:
66 add %g0, 0x8, my_id_reg ! this is my ID address
67 ba producer
68 nop
69
70th_main_1:
71 add %g0, 0x8, my_id_reg
72 ba consumer
73 nop
74
75th_main_2:
76 add %g0, 0x38, my_id_reg
77 ba producer
78 nop
79 !ba good_end
80 !nop
81
82th_main_3:
83 add %g0, 0x3c, my_id_reg
84 ba consumer
85 nop
86 !ba good_end
87 !nop
88
89th_main_4:
90 add %g0, 0x38, my_id_reg
91 ba consumer
92 nop
93 !ba good_end
94 !nop
95
96th_main_5:
97 add %g0, 0x3c, my_id_reg
98 ba producer
99 nop
100 !ba good_end
101 !nop
102
103th_main_6:
104 ba good_end
105 nop
106
107th_main_7:
108 ba good_end
109 nop
110
111!====================================================================================
112producer:
113 ld [spinlock_addr_reg + my_id_reg], test_reg ! try to acquire lock
114 tst test_reg ! did we get it?
115 be producer_gotlock
116 nop
117 ba producer
118 nop
119
120!====================================================================================
121consumer:
122 ld [spinlock_addr_reg + my_id_reg], test_reg ! try to acquire lock
123 sub test_reg, 0x55, %i1 ! code to end the test
124 tst %i1
125 be good_end ! end the test
126 nop
127 sub test_reg, 0x1, %i1 ! code for available data
128 tst %i1
129 be consumer_gotlock
130 nop
131 ba consumer
132 nop
133
134
135!====================================================================================
136producer_gotlock:
137 set 0x60, %l0
138 setx protected_area, tmp1, data_base_reg
139producer_loop0:
140 st %g0, [data_base_reg + my_id_reg] ! clean up
141 add data_base_reg, 0x40, data_base_reg ! increment the address
142 deccc %l0
143 bne producer_loop0 ! repeat
144 nop
145
146 set 0x60, %l0
147 setx protected_area, tmp1, data_base_reg
148 mov my_id_reg, %i1
149producer_loop1:
150 st %i1, [data_base_reg + my_id_reg] ! store my ID in there
151 add data_base_reg, 0x40, data_base_reg ! increment the address
152 add %i1, 1, %i1
153 deccc %l0
154 bne producer_loop1 ! repeat
155 nop
156
157 deccc global_cnt_reg
158 be cleanup_and_finish
159 nop
160 add %g0, 1 , tmp1
161 st tmp1, [spinlock_addr_reg + my_id_reg] ! data ready
162 ba producer
163 nop
164
165cleanup_and_finish:
166 add %g0, 0x55 , tmp1
167 st tmp1, [spinlock_addr_reg + my_id_reg] ! finish the test
168 ba good_end
169 nop
170
171!====================================================================================
172consumer_gotlock:
173 set 0x60, %l0
174 setx protected_area, tmp1, data_base_reg
175 mov my_id_reg, %i1
176consumer_loop1:
177 ld [data_base_reg + my_id_reg], %i2 ! load my ID in there
178 subcc %i2, %i1, %i2
179 bne bad_end
180 nop
181 add data_base_reg, 0x40, data_base_reg ! increment the address
182 inc %i1
183 deccc %l0
184 bne consumer_loop1 ! repeat
185 nop
186
187 st %g0, [spinlock_addr_reg+ my_id_reg] ! consumer ready
188
189 ba consumer
190 nop
191
192good_end:
193 ta T_GOOD_TRAP
194bad_end:
195 ta T_BAD_TRAP
196
197!==========================
198
199SECTION .MY_DATA0 DATA_VA=0xd0100000
200attr_data {
201 Name = .MY_DATA0,
202 VA= 0x0d0100000,
203 RA=0xc000000000,
204 PA=0xc000000000,
205 part_0_ctx_nonzero_tsb_config_0,
206 TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
207 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
208 TTE_L=0, TTE_CP=0, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
209 }
210
211 .data
212
213.global spinlock_address
214spinlock_address:
215 .skip 0x1000
216
217
218SECTION .MY_DATA1 DATA_VA=0xd1110000
219attr_data {
220 Name = .MY_DATA1,
221 VA= 0x0d1110000,
222 RA=0xc200bee000,
223 PA=0xc200bee000,
224 part_0_ctx_nonzero_tsb_config_1,
225 TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
226 TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
227 TTE_L=0, TTE_CP=0, TTE_CV=0, TTE_E=0, TTE_P=0, TTE_W=1
228 }
229
230 .data
231.global protected_area
232protected_area:
233 .word 0xbeef
234 .skip 0x1000
235 .word 0xbeef
236.end