[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_prod_cons_variation1_1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tso_n1_prod_cons_variation1_1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define addrA_reg  		%l0
#define addrB_reg		%l1
#define result0_reg	  	%l2
#define result1_reg	  	%l3
#define ready0_reg	  	%l4
#define ready1_reg	  	%l5
#define finish_reg	  	%l6

#define global_cnt_reg	  	%i0

#define tmp0	  		%o2
#define tmp1	  		%o3
#define test_reg		%o4
#define test2_reg		%o5

#define tmp1			%i1
#define tmp2			%i2
#define tmp3			%i3

#define ITERATIONS 	  	0x2

#include "hboot.s"

.global main

main:

	setx    addrA,		tmp0, addrA_reg
	setx    addrB, 		tmp0, addrB_reg
	setx    result0, 	tmp0, result0_reg
	setx    result1, 	tmp0, result1_reg
	setx    ready0, 	tmp0, ready0_reg
	setx    ready1, 	tmp0, ready1_reg
	setx    finish_area,	tmp0, finish_reg

        set     ITERATIONS,	global_cnt_reg 			! 

th_fork(th_main,tmp1)

!=====================================================
th_main_0:
	mov	0x1,	tmp3
loop00:
	st	tmp3, [addrA_reg]		! store non-zero to A

loop01:						! wait for A to be zero again.
        ld    	[finish_reg], test_reg		! check for end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrA_reg], test_reg
	brnz	test_reg, loop01
	nop

	nop; nop; nop; nop;
	nop; nop; nop; nop;
	nop; nop; nop; nop;
	nop; nop; nop; nop;

	ba	loop00				! loop
	nop

!=========================================================
th_main_1:

	mov	0x2,	tmp3
loop10:
	st	tmp3, [addrB_reg]		! store non-zero to B
loop11:						! wait for B to be zero again
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrB_reg], test_reg
	brnz	test_reg, loop11
	nop

	ba	loop10				! loop
	nop

!=========================================================
th_main_2:

	ba	good_end			! noise
	nop

!=========================================================
th_main_3:

loop30:

loop31:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrB_reg], test_reg		! load B until set
	brz	test_reg, loop31
	nop

        ld    	[addrA_reg], test_reg		! read A and store it
	st	test_reg,    [result0_reg]	! to result place.

	mov	0x1, test_reg
	st	test_reg,    [ready0_reg]	! flag ready

loop32:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[ready0_reg], test_reg		! wait for ready to be cleared
	brnz	test_reg, loop32
	nop

	ba	loop30				! loop
	nop

!=========================================================
th_main_4:

loop40:

loop41:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrA_reg], test_reg		! load A until set
	brz	test_reg, loop41
	nop

        ld    	[addrB_reg], test_reg		! load B and store it
	st	test_reg,    [result1_reg]	! to result place

	mov	0x1, test_reg
	st	test_reg,    [ready1_reg]	! flag ready

loop42:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[ready1_reg], test_reg		! wait for ready to be cleared
	brnz	test_reg, loop42
	nop

	ba	loop40				! loop
	nop


!=========================================================
th_main_5:

loop50:
        ld    	[ready0_reg], test_reg		! wait for ready0
	brz	test_reg, loop50
	nop

loop51:
        ld    	[ready1_reg], test_reg		! wait for ready1
	brz	test_reg, loop51
	nop

	ld	[result0_reg], test_reg		! load the 2 results
	ld	[result1_reg], test2_reg
	brnz	test_reg, loop5_cont		! if non-zero-> new-> OK
	nop
	brz	test2_reg, bad_end		! if both 0 -> BAD!!!
	nop

loop5_cont:

	st	%g0,   	[result0_reg]		! clear results
	st	%g0,   	[result1_reg]
	st	%g0,   	[addrA_reg]		! clear A and B
	st	%g0,   	[addrB_reg]
	st	%g0,    [ready0_reg]		! clear the ready
	st	%g0,    [ready1_reg]

	mov	0x0, tmp3			! check for end of test
	deccc	global_cnt_reg		
        move	%icc, 0x55, tmp3
	st	tmp3,    [finish_reg]		! and flag it
	brz	global_cnt_reg, good_end
	nop

	ba	loop50
	nop

!=========================================================

th_main_6:
	ba	good_end
	nop

th_main_7:
	ba	good_end
	nop

!====================================================================================
good_end:
        ta      T_GOOD_TRAP
bad_end:
        ta      T_BAD_TRAP

!==========================

SECTION .MY_DATA0  TEXT_VA=0xf0100000, DATA_VA=0xd0100000
attr_data {
        Name = .MY_DATA0,
        VA= 0x0d0100000
        RA= 0x1d0100000
        PA= ra2pa(0x1d0100000,0),
part_0_ctx_nonzero_tsb_config_0,
        TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
        }

attr_text {
        Name = .MY_DATA0,
        VA= 0x0f0100000
        RA= 0x1f0100000
        PA= ra2pa(0x1f0100000,0),
part_0_ctx_nonzero_tsb_config_0,
        TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
        }

	.data

.global addrA
addrA:
	.word 0x0
	.skip 0x100
.global result0
result0:
	.word	0x0
.global ready0
ready0:
	.word	0x0

SECTION .MY_DATA1  TEXT_VA=0xf1110000, DATA_VA=0xd1110000
attr_data {
        Name = .MY_DATA1,
        VA= 0x0d1110000,
        RA= 0x1d1110000,
        PA= ra2pa(0x1d1110000,0),
part_0_ctx_nonzero_tsb_config_1,
        TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
        }

attr_text {
        Name = .MY_DATA1,
        VA= 0x0f1110000,
        RA= 0x1f1110000,
        PA= ra2pa(0x1f1110000,0),
part_0_ctx_nonzero_tsb_config_1,
        TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
        }

	.data
.global addrB
addrB:
	.word	0x0
	.skip 0x100
.global result1
result1:
	.word	0x0
.global ready1
ready1:
	.word	0x0
	
.global finish_area
finish_area:
	.word	0x0
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tso_n1_prod_cons_variation1_1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define addrA_reg %l0
	39	#define addrB_reg %l1
	40	#define result0_reg %l2
	41	#define result1_reg %l3
	42	#define ready0_reg %l4
	43	#define ready1_reg %l5
	44	#define finish_reg %l6
	45
	46	#define global_cnt_reg %i0
	47
	48	#define tmp0 %o2
	49	#define tmp1 %o3
	50	#define test_reg %o4
	51	#define test2_reg %o5
	52
	53	#define tmp1 %i1
	54	#define tmp2 %i2
	55	#define tmp3 %i3
	56
	57	#define ITERATIONS 0x2
	58
	59	#include "hboot.s"
	60
	61	.global main
	62
	63	main:
	64
65	setx addrA, tmp0, addrA_reg
66	setx addrB, tmp0, addrB_reg
67	setx result0, tmp0, result0_reg
68	setx result1, tmp0, result1_reg
69	setx ready0, tmp0, ready0_reg
70	setx ready1, tmp0, ready1_reg
71	setx finish_area, tmp0, finish_reg
72
73	set ITERATIONS, global_cnt_reg !
74
75	th_fork(th_main,tmp1)
76
77	!=====================================================
78	th_main_0:
79	mov 0x1, tmp3
80	loop00:
81	st tmp3, [addrA_reg] ! store non-zero to A
82
83	loop01: ! wait for A to be zero again.
84	ld [finish_reg], test_reg ! check for end
85	sub test_reg, 0x55, tmp2
86	brz tmp2, good_end
87	nop
88
89	ld [addrA_reg], test_reg
90	brnz test_reg, loop01
91	nop
92
93	nop; nop; nop; nop;
94	nop; nop; nop; nop;
95	nop; nop; nop; nop;
96	nop; nop; nop; nop;
97
98	ba loop00 ! loop
99	nop
100
101	!=========================================================
102	th_main_1:
103
104	mov 0x2, tmp3
105	loop10:
106	st tmp3, [addrB_reg] ! store non-zero to B
107	loop11: ! wait for B to be zero again
108	ld [finish_reg], test_reg ! check for an end
109	sub test_reg, 0x55, tmp2
110	brz tmp2, good_end
111	nop
112
113	ld [addrB_reg], test_reg
114	brnz test_reg, loop11
115	nop
116
117	ba loop10 ! loop
118	nop
119
120	!=========================================================
121	th_main_2:
122
123	ba good_end ! noise
124	nop
125
126	!=========================================================
127	th_main_3:
128
129	loop30:
130
131	loop31:
132	ld [finish_reg], test_reg ! check for an end
133	sub test_reg, 0x55, tmp2
134	brz tmp2, good_end
135	nop
136
137	ld [addrB_reg], test_reg ! load B until set
138	brz test_reg, loop31
139	nop
140
141	ld [addrA_reg], test_reg ! read A and store it
142	st test_reg, [result0_reg] ! to result place.
143
144	mov 0x1, test_reg
145	st test_reg, [ready0_reg] ! flag ready
146
147	loop32:
148	ld [finish_reg], test_reg ! check for an end
149	sub test_reg, 0x55, tmp2
150	brz tmp2, good_end
151	nop
152
153	ld [ready0_reg], test_reg ! wait for ready to be cleared
154	brnz test_reg, loop32
155	nop
156
157	ba loop30 ! loop
158	nop
159
160	!=========================================================
161	th_main_4:
162
163	loop40:
164
165	loop41:
166	ld [finish_reg], test_reg ! check for an end
167	sub test_reg, 0x55, tmp2
168	brz tmp2, good_end
169	nop
170
171	ld [addrA_reg], test_reg ! load A until set
172	brz test_reg, loop41
173	nop
174
175	ld [addrB_reg], test_reg ! load B and store it
176	st test_reg, [result1_reg] ! to result place
177
178	mov 0x1, test_reg
179	st test_reg, [ready1_reg] ! flag ready
180
181	loop42:
182	ld [finish_reg], test_reg ! check for an end
183	sub test_reg, 0x55, tmp2
184	brz tmp2, good_end
185	nop
186
187	ld [ready1_reg], test_reg ! wait for ready to be cleared
188	brnz test_reg, loop42
189	nop
190
191	ba loop40 ! loop
192	nop
193
194
195	!=========================================================
196	th_main_5:
197
198	loop50:
199	ld [ready0_reg], test_reg ! wait for ready0
200	brz test_reg, loop50
201	nop
202
203	loop51:
204	ld [ready1_reg], test_reg ! wait for ready1
205	brz test_reg, loop51
206	nop
207
208	ld [result0_reg], test_reg ! load the 2 results
209	ld [result1_reg], test2_reg
210	brnz test_reg, loop5_cont ! if non-zero-> new-> OK
211	nop
212	brz test2_reg, bad_end ! if both 0 -> BAD!!!
213	nop
214
215	loop5_cont:
216
217	st %g0, [result0_reg] ! clear results
218	st %g0, [result1_reg]
219	st %g0, [addrA_reg] ! clear A and B
220	st %g0, [addrB_reg]
221	st %g0, [ready0_reg] ! clear the ready
222	st %g0, [ready1_reg]
223
224	mov 0x0, tmp3 ! check for end of test
225	deccc global_cnt_reg
226	move %icc, 0x55, tmp3
227	st tmp3, [finish_reg] ! and flag it
228	brz global_cnt_reg, good_end
229	nop
230
231	ba loop50
232	nop
233
234	!=========================================================
235
236	th_main_6:
237	ba good_end
238	nop
239
240	th_main_7:
241	ba good_end
242	nop
243
244	!====================================================================================
245	good_end:
246	ta T_GOOD_TRAP
247	bad_end:
248	ta T_BAD_TRAP
249
250	!==========================
251
252	SECTION .MY_DATA0 TEXT_VA=0xf0100000, DATA_VA=0xd0100000
253	attr_data {
254	Name = .MY_DATA0,
255	VA= 0x0d0100000
256	RA= 0x1d0100000
257	PA= ra2pa(0x1d0100000,0),
258	part_0_ctx_nonzero_tsb_config_0,
259	TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
260	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
261	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
262	}
263
264	attr_text {
265	Name = .MY_DATA0,
266	VA= 0x0f0100000
267	RA= 0x1f0100000
268	PA= ra2pa(0x1f0100000,0),
269	part_0_ctx_nonzero_tsb_config_0,
270	TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
271	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
272	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
273	}
274
275	.data
276
277	.global addrA
278	addrA:
279	.word 0x0
280	.skip 0x100
281	.global result0
282	result0:
283	.word 0x0
284	.global ready0
285	ready0:
286	.word 0x0
287
288	SECTION .MY_DATA1 TEXT_VA=0xf1110000, DATA_VA=0xd1110000
289	attr_data {
290	Name = .MY_DATA1,
291	VA= 0x0d1110000,
292	RA= 0x1d1110000,
293	PA= ra2pa(0x1d1110000,0),
294	part_0_ctx_nonzero_tsb_config_1,
295	TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
296	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
297	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
298	}
299
300	attr_text {
301	Name = .MY_DATA1,
302	VA= 0x0f1110000,
303	RA= 0x1f1110000,
304	PA= ra2pa(0x1f1110000,0),
305	part_0_ctx_nonzero_tsb_config_1,
306	TTE_G=1, TTE_Context=0x44, TTE_V=1, TTE_Size=0, TTE_NFO=0,
307	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
308	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
309	}
310
311	.data
312	.global addrB
313	addrB:
314	.word 0x0
315	.skip 0x100
316	.global result1
317	result1:
318	.word 0x0
319	.global ready1
320	ready1:
321	.word 0x0
322
323	.global finish_area
324	finish_area:
325	.word 0x0
326	.end