[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_prod_cons_variation2_1.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tso_n1_prod_cons_variation2_1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define addrA_reg  		%l0
#define addrB_reg		%l1
#define addrC_reg		%l2
#define result0_reg	  	%l3
#define result1_reg	  	%l4
#define ready0_reg	  	%l5
#define ready1_reg	  	%l6
#define finish_reg	  	%l7

#define global_cnt_reg	  	%i0

#define tmp0	  		%o2
#define tmp1	  		%o3
#define test_reg		%o4
#define test2_reg		%o5

#define tmp1			%i1
#define tmp2			%i2
#define tmp3			%i3

#define ITERATIONS 	  	0x2

#include "hboot.s"

.global main

main:

	setx    addrA,		tmp0, addrA_reg
	setx    addrB, 		tmp0, addrB_reg
	setx    addrC, 		tmp0, addrC_reg
	setx    result0, 	tmp0, result0_reg
	setx    result1, 	tmp0, result1_reg
	setx    ready0, 	tmp0, ready0_reg
	setx    ready1, 	tmp0, ready1_reg
	setx    finish_area,	tmp0, finish_reg

        set     ITERATIONS,	global_cnt_reg 			! 

th_fork(th_main,tmp1)

!=====================================================
th_main_0:
loop00:
	mov	0x2,	tmp3
	st	tmp3, [addrC_reg]		!
	mov	0x1,	tmp3
	st	tmp3, [addrA_reg]		! store non-zero to A

loop01:						! wait for A to be zero again.
        ld    	[finish_reg], test_reg		! OR for the end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrA_reg], test_reg
	brnz	test_reg, loop01
	nop

	nop; nop; nop; nop;

	ba	loop00				! loop
	nop

!=========================================================
th_main_1:

loop10:
	mov	0x3,	tmp3
	st	tmp3, [addrC_reg]		! 
	mov	0x1,	tmp3
	st	tmp3, [addrB_reg]		! store non-zero to B

loop11:						! wait for B to be zero again
        ld    	[finish_reg], test_reg		! or for the end.
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrB_reg], test_reg
	brnz	test_reg, loop11
	nop

	ba	loop10				! loop
	nop

!=========================================================
th_main_2:

	ba	good_end			! noise
	nop

!=========================================================
th_main_3:

loop30:

loop31:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrA_reg], test_reg		! load A until set
	brz	test_reg, loop31
	nop

loop32:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrB_reg], test_reg		! load B  until set
	brz	test_reg, loop32
	nop

        ld    	[addrC_reg], test_reg		! read C and store it.
	st	test_reg,    [result0_reg]	! to result place.

	mov	0x1, test_reg
	st	test_reg,    [ready0_reg]	! flag ready

loop33:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[ready0_reg], test_reg		! wait for ready to be cleared
	brnz	test_reg, loop33
	nop

	ba	loop30				! loop
	nop

!=========================================================
th_main_4:

loop40:

loop41:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrA_reg], test_reg		! load A until set
	brz	test_reg, loop41
	nop

loop42:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[addrB_reg], test_reg		! load B until set
	brz	test_reg, loop42
	nop

        ld    	[addrC_reg], test_reg		! load B and store it
	st	test_reg,    [result1_reg]	! to result place

	mov	0x1, test_reg
	st	test_reg,    [ready1_reg]	! flag ready

loop43:
        ld    	[finish_reg], test_reg		! check for an end
	sub	test_reg, 0x55, tmp2
	brz	tmp2, good_end
	nop

        ld    	[ready1_reg], test_reg		! wait for ready to be cleared
	brnz	test_reg, loop43
	nop

	ba	loop40				! loop
	nop

!=========================================================
th_main_5:

loop50:
        ld    	[ready0_reg], test_reg		! wait for ready0
	brz	test_reg, loop50
	nop

loop51:
        ld    	[ready1_reg], test_reg		! wait for ready1
	brz	test_reg, loop51
	nop

	ld	[result0_reg], test_reg		! load the 2 results,
	ld	[result1_reg], test2_reg
	subcc	test_reg, test2_reg, %g0	! if non-equal-> BAD
	bne	bad_end	
	nop

loop5_cont:
	st	%g0,   	[result0_reg]		! clear results
	st	%g0,   	[result1_reg]
	st	%g0,   	[addrA_reg]		! clear A and B
	st	%g0,   	[addrB_reg]
	st	%g0,   	[addrC_reg]
	st	%g0,    [ready0_reg]		! clear the ready
	st	%g0,    [ready1_reg]

	mov	0x0, tmp3			! check for end of test
	deccc	global_cnt_reg		
        move	%icc, 0x55, tmp3
	st	tmp3,    [finish_reg]		! and flag it
	brz	global_cnt_reg, good_end
	nop

	ba	loop50
	nop

!=========================================================

th_main_6:					! noise
	ba	good_end
	nop

th_main_7:					! noise
	ba	good_end
	nop

!=========================================================
good_end:
        ta      T_GOOD_TRAP
bad_end:
        ta      T_BAD_TRAP

!=========================================================

.data

.global addrA
.align 0x40
addrA:
	.word 0x0
	.skip 0x100
.global result0
result0:
	.word	0x0
.global ready0
ready0:
	.word	0x0

.global addrB
addrB:
	.word	0x0
	.skip 0x100
.global result1
result1:
	.word	0x0
.global ready1
ready1:
	.word	0x0
	
.global finish_area
finish_area:
	.word	0x0

.align 0x40
.global addrC
addrC:
	.word	0x0
	.skip 0x100

.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tso_n1_prod_cons_variation2_1.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define addrA_reg %l0
	39	#define addrB_reg %l1
	40	#define addrC_reg %l2
	41	#define result0_reg %l3
	42	#define result1_reg %l4
	43	#define ready0_reg %l5
	44	#define ready1_reg %l6
	45	#define finish_reg %l7
	46
	47	#define global_cnt_reg %i0
	48
	49	#define tmp0 %o2
	50	#define tmp1 %o3
	51	#define test_reg %o4
	52	#define test2_reg %o5
	53
	54	#define tmp1 %i1
	55	#define tmp2 %i2
	56	#define tmp3 %i3
	57
	58	#define ITERATIONS 0x2
	59
	60	#include "hboot.s"
	61
	62	.global main
	63
	64	main:
65
66	setx addrA, tmp0, addrA_reg
67	setx addrB, tmp0, addrB_reg
68	setx addrC, tmp0, addrC_reg
69	setx result0, tmp0, result0_reg
70	setx result1, tmp0, result1_reg
71	setx ready0, tmp0, ready0_reg
72	setx ready1, tmp0, ready1_reg
73	setx finish_area, tmp0, finish_reg
74
75	set ITERATIONS, global_cnt_reg !
76
77	th_fork(th_main,tmp1)
78
79	!=====================================================
80	th_main_0:
81	loop00:
82	mov 0x2, tmp3
83	st tmp3, [addrC_reg] !
84	mov 0x1, tmp3
85	st tmp3, [addrA_reg] ! store non-zero to A
86
87	loop01: ! wait for A to be zero again.
88	ld [finish_reg], test_reg ! OR for the end
89	sub test_reg, 0x55, tmp2
90	brz tmp2, good_end
91	nop
92
93	ld [addrA_reg], test_reg
94	brnz test_reg, loop01
95	nop
96
97	nop; nop; nop; nop;
98
99	ba loop00 ! loop
100	nop
101
102	!=========================================================
103	th_main_1:
104
105	loop10:
106	mov 0x3, tmp3
107	st tmp3, [addrC_reg] !
108	mov 0x1, tmp3
109	st tmp3, [addrB_reg] ! store non-zero to B
110
111	loop11: ! wait for B to be zero again
112	ld [finish_reg], test_reg ! or for the end.
113	sub test_reg, 0x55, tmp2
114	brz tmp2, good_end
115	nop
116
117	ld [addrB_reg], test_reg
118	brnz test_reg, loop11
119	nop
120
121	ba loop10 ! loop
122	nop
123
124	!=========================================================
125	th_main_2:
126
127	ba good_end ! noise
128	nop
129
130	!=========================================================
131	th_main_3:
132
133	loop30:
134
135	loop31:
136	ld [finish_reg], test_reg ! check for an end
137	sub test_reg, 0x55, tmp2
138	brz tmp2, good_end
139	nop
140
141	ld [addrA_reg], test_reg ! load A until set
142	brz test_reg, loop31
143	nop
144
145	loop32:
146	ld [finish_reg], test_reg ! check for an end
147	sub test_reg, 0x55, tmp2
148	brz tmp2, good_end
149	nop
150
151	ld [addrB_reg], test_reg ! load B until set
152	brz test_reg, loop32
153	nop
154
155	ld [addrC_reg], test_reg ! read C and store it.
156	st test_reg, [result0_reg] ! to result place.
157
158	mov 0x1, test_reg
159	st test_reg, [ready0_reg] ! flag ready
160
161	loop33:
162	ld [finish_reg], test_reg ! check for an end
163	sub test_reg, 0x55, tmp2
164	brz tmp2, good_end
165	nop
166
167	ld [ready0_reg], test_reg ! wait for ready to be cleared
168	brnz test_reg, loop33
169	nop
170
171	ba loop30 ! loop
172	nop
173
174	!=========================================================
175	th_main_4:
176
177	loop40:
178
179	loop41:
180	ld [finish_reg], test_reg ! check for an end
181	sub test_reg, 0x55, tmp2
182	brz tmp2, good_end
183	nop
184
185	ld [addrA_reg], test_reg ! load A until set
186	brz test_reg, loop41
187	nop
188
189	loop42:
190	ld [finish_reg], test_reg ! check for an end
191	sub test_reg, 0x55, tmp2
192	brz tmp2, good_end
193	nop
194
195	ld [addrB_reg], test_reg ! load B until set
196	brz test_reg, loop42
197	nop
198
199	ld [addrC_reg], test_reg ! load B and store it
200	st test_reg, [result1_reg] ! to result place
201
202	mov 0x1, test_reg
203	st test_reg, [ready1_reg] ! flag ready
204
205	loop43:
206	ld [finish_reg], test_reg ! check for an end
207	sub test_reg, 0x55, tmp2
208	brz tmp2, good_end
209	nop
210
211	ld [ready1_reg], test_reg ! wait for ready to be cleared
212	brnz test_reg, loop43
213	nop
214
215	ba loop40 ! loop
216	nop
217
218	!=========================================================
219	th_main_5:
220
221	loop50:
222	ld [ready0_reg], test_reg ! wait for ready0
223	brz test_reg, loop50
224	nop
225
226	loop51:
227	ld [ready1_reg], test_reg ! wait for ready1
228	brz test_reg, loop51
229	nop
230
231	ld [result0_reg], test_reg ! load the 2 results,
232	ld [result1_reg], test2_reg
233	subcc test_reg, test2_reg, %g0 ! if non-equal-> BAD
234	bne bad_end
235	nop
236
237	loop5_cont:
238	st %g0, [result0_reg] ! clear results
239	st %g0, [result1_reg]
240	st %g0, [addrA_reg] ! clear A and B
241	st %g0, [addrB_reg]
242	st %g0, [addrC_reg]
243	st %g0, [ready0_reg] ! clear the ready
244	st %g0, [ready1_reg]
245
246	mov 0x0, tmp3 ! check for end of test
247	deccc global_cnt_reg
248	move %icc, 0x55, tmp3
249	st tmp3, [finish_reg] ! and flag it
250	brz global_cnt_reg, good_end
251	nop
252
253	ba loop50
254	nop
255
256	!=========================================================
257
258	th_main_6: ! noise
259	ba good_end
260	nop
261
262	th_main_7: ! noise
263	ba good_end
264	nop
265
266	!=========================================================
267	good_end:
268	ta T_GOOD_TRAP
269	bad_end:
270	ta T_BAD_TRAP
271
272	!=========================================================
273
274	.data
275
276	.global addrA
277	.align 0x40
278	addrA:
279	.word 0x0
280	.skip 0x100
281	.global result0
282	result0:
283	.word 0x0
284	.global ready0
285	ready0:
286	.word 0x0
287
288	.global addrB
289	addrB:
290	.word 0x0
291	.skip 0x100
292	.global result1
293	result1:
294	.word 0x0
295	.global ready1
296	ready1:
297	.word 0x0
298
299	.global finish_area
300	finish_area:
301	.word 0x0
302
303	.align 0x40
304	.global addrC
305	addrC:
306	.word 0x0
307	.skip 0x100
308
309	.end