[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / tso / tso_directed / tso_n1_self_mod103.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tso_n1_self_mod103.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_BASE_DATA_ADDR     0x160000
#define MAIN_BASE_TEXT_ADDR     0x150000
#define MAIN_BASE_DATA_ADDR_RA  0x100160000
#define MAIN_BASE_TEXT_ADDR_RA  0x100150000

#define USER_PAGE_CUSTOM_MAP
#include "hboot.s"

SECTION .MAIN  TEXT_VA=0x150000, DATA_VA=0x160000

attr_text {
        Name = .MAIN,
        VA=MAIN_BASE_TEXT_ADDR,
        RA=MAIN_BASE_TEXT_ADDR_RA,
        PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
part_0_ctx_nonzero_tsb_config_0,
        TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_EP=1, TTE_P=0, TTE_W=1
        }
attr_data {
        Name = .MAIN,
        VA=MAIN_BASE_DATA_ADDR,
        RA=MAIN_BASE_DATA_ADDR_RA,
        PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
part_0_ctx_nonzero_tsb_config_0,
        TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
        TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
        TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
        }

.text
.global main

main:	clr	%l0

	th_fork(main)

main_0:

      	add     %g0, 0x20, %i3             ! loop counter

loop0:
	clr	%l1
execute1:
	set	main01,%i0
	jmpl	%i0,%o7
        nop 
	add	%l1, %l0, %l1
        nop
        nop

modify1:
	set	main02,%i0    	!get some known data into the store reg.
	set	main01,%i1   	!change the data at main1
	ld	[%i1],%l0       
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		!update the I$ to be consistent with the l2

execute2:
        set     main01,%i0
        jmpl    %i0,%o7    	!the jump causes a new cache line to be
        nop               	!loaded into the l2 and the icache.
	add	%l1, %l0, %l1
        nop
        nop

modify2:
	set	main03,%i0    	!get some known data into the store reg.
	set	main01,%i1   	!change the data at main1
	ld	[%i1],%l0       
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		!update the I$ to be consistent with the l2

execute3:
        set     main01,%i0
        jmpl    %i0,%o7     	!the jump causes a new cache line to be
        nop              	!loaded into the l2 and the icache.
	add	%l1, %l0, %l1
        nop
        nop

modify3:
	set	main04,%i0    	! get some known data into the store reg.
	set	main01,%i1   	! change the data at main1
	ld	[%i1],%l0       
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		! update the I$ to be consistent with the l2

execute4:
        set     main01,%i0
        jmpl    %i0,%o7      	! the jump causes a new cache line to be
        nop             	! loaded into the l2 and the icache.
	add	%l1, %l0, %l1
        nop
        nop

modify4:
	set	main05,%i0    	! get some known data into the store reg.
	set	main01,%i1   	! change the data at main1
	ld	[%i1],%l0       
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush	%i1 		! update the I$ to be consistent with the l2

execute5:
        set     main01,%i0
        jmpl    %i0,%o7		! the jump causes a new cache line to be
        nop               	! loaded into the l2 and the icache.
	add	%l1, %l0, %l1
        nop
        nop

	set	15, %i0
	subcc	%i0, %l1, %i0
	bnz	bad_end
	nop

modify5:
	set	main06,%i0    	! get some known data into the store reg.
	set	main01,%i1    	! change the data at main1
	ld	[%i1],%l0       
	ld	[%i0],%l0       
	st	%l0,[%i1]
	flush   %i1		! flush

        dec %i3
        brnz %i3, loop0
        nop

normal_end:
        ta      T_GOOD_TRAP
bad_end:
        ta      T_BAD_TRAP

! the point of these next two pages is to have text pages that
! can be written and read
! The first page holds 2 cache lines worth, the second page has 1 cache line.

ALIGN_PAGE_8K
user_text2_start:

main01:
        mov     1,%l0           ! Replaced with copied_code second pass
	jmpl	%o7+8, %g0
	nop
main02:
	mov	2,%l0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
main03:
	mov	3,%l0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop

main04:
	mov	4,%l0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
main05:
	mov	5,%l0
        nop
        nop
        nop
        nop
        nop

main06:
	mov	1,%l0
        nop
        nop
        nop
        nop
        nop
user_text2_end:

main_1:
main_4:
	set	main01,%i1   		! look at main1
	set	main02,%i2   		! look at main1
	set	main03,%i3   		! look at main1
	set	main04,%i4   		! look at main1
	set	main05,%i5   		! look at main1
	set	main06,%i6   		! look at main1

      	setx    0x100, %o2, %o3	! loop counter

loop1or4_2:
	ld	[%i1], %l0
	ld	[%i1 + 0x10], %l1	
	nop
	ld	[%i2], %l0
	ld	[%i2 + 0x10], %l1	
	nop
	ld	[%i3], %l0
	ld	[%i3 + 0x10], %l1	
	nop
	ld	[%i4], %l0
	ld	[%i4 + 0x10], %l1	
	nop
	ld	[%i5], %l0
	ld	[%i5 + 0x10], %l1	
	nop
	ld	[%i6], %l0
	ld	[%i6 + 0x10], %l1	
	nop

        dec %o3
        brnz %o3, loop1or4_2
        nop

        ta      T_GOOD_TRAP

/***********************************************************************
   Test case data start
 ***********************************************************************/
.data
user_data_start:
	.word 0x0
user_data_end:
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tso_n1_self_mod103.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_BASE_DATA_ADDR 0x160000
	39	#define MAIN_BASE_TEXT_ADDR 0x150000
	40	#define MAIN_BASE_DATA_ADDR_RA 0x100160000
	41	#define MAIN_BASE_TEXT_ADDR_RA 0x100150000
	42
	43	#define USER_PAGE_CUSTOM_MAP
	44	#include "hboot.s"
	45
	46	SECTION .MAIN TEXT_VA=0x150000, DATA_VA=0x160000
	47
	48	attr_text {
	49	Name = .MAIN,
	50	VA=MAIN_BASE_TEXT_ADDR,
	51	RA=MAIN_BASE_TEXT_ADDR_RA,
	52	PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
	53	part_0_ctx_nonzero_tsb_config_0,
	54	TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
	55	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
	56	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_EP=1, TTE_P=0, TTE_W=1
	57	}
	58	attr_data {
	59	Name = .MAIN,
	60	VA=MAIN_BASE_DATA_ADDR,
	61	RA=MAIN_BASE_DATA_ADDR_RA,
	62	PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
	63	part_0_ctx_nonzero_tsb_config_0,
	64	TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
65	TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
66	TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
67	}
68
69	.text
70	.global main
71
72	main: clr %l0
73
74	th_fork(main)
75
76	main_0:
77
78	add %g0, 0x20, %i3 ! loop counter
79
80	loop0:
81	clr %l1
82	execute1:
83	set main01,%i0
84	jmpl %i0,%o7
85	nop
86	add %l1, %l0, %l1
87	nop
88	nop
89
90	modify1:
91	set main02,%i0 !get some known data into the store reg.
92	set main01,%i1 !change the data at main1
93	ld [%i1],%l0
94	ld [%i0],%l0
95	st %l0,[%i1]
96	flush %i1 !update the I$ to be consistent with the l2
97
98	execute2:
99	set main01,%i0
100	jmpl %i0,%o7 !the jump causes a new cache line to be
101	nop !loaded into the l2 and the icache.
102	add %l1, %l0, %l1
103	nop
104	nop
105
106	modify2:
107	set main03,%i0 !get some known data into the store reg.
108	set main01,%i1 !change the data at main1
109	ld [%i1],%l0
110	ld [%i0],%l0
111	st %l0,[%i1]
112	flush %i1 !update the I$ to be consistent with the l2
113
114	execute3:
115	set main01,%i0
116	jmpl %i0,%o7 !the jump causes a new cache line to be
117	nop !loaded into the l2 and the icache.
118	add %l1, %l0, %l1
119	nop
120	nop
121
122	modify3:
123	set main04,%i0 ! get some known data into the store reg.
124	set main01,%i1 ! change the data at main1
125	ld [%i1],%l0
126	ld [%i0],%l0
127	st %l0,[%i1]
128	flush %i1 ! update the I$ to be consistent with the l2
129
130	execute4:
131	set main01,%i0
132	jmpl %i0,%o7 ! the jump causes a new cache line to be
133	nop ! loaded into the l2 and the icache.
134	add %l1, %l0, %l1
135	nop
136	nop
137
138	modify4:
139	set main05,%i0 ! get some known data into the store reg.
140	set main01,%i1 ! change the data at main1
141	ld [%i1],%l0
142	ld [%i0],%l0
143	st %l0,[%i1]
144	flush %i1 ! update the I$ to be consistent with the l2
145
146	execute5:
147	set main01,%i0
148	jmpl %i0,%o7 ! the jump causes a new cache line to be
149	nop ! loaded into the l2 and the icache.
150	add %l1, %l0, %l1
151	nop
152	nop
153
154	set 15, %i0
155	subcc %i0, %l1, %i0
156	bnz bad_end
157	nop
158
159	modify5:
160	set main06,%i0 ! get some known data into the store reg.
161	set main01,%i1 ! change the data at main1
162	ld [%i1],%l0
163	ld [%i0],%l0
164	st %l0,[%i1]
165	flush %i1 ! flush
166
167	dec %i3
168	brnz %i3, loop0
169	nop
170
171	normal_end:
172	ta T_GOOD_TRAP
173	bad_end:
174	ta T_BAD_TRAP
175
176	! the point of these next two pages is to have text pages that
177	! can be written and read
178	! The first page holds 2 cache lines worth, the second page has 1 cache line.
179
180	ALIGN_PAGE_8K
181	user_text2_start:
182
183	main01:
184	mov 1,%l0 ! Replaced with copied_code second pass
185	jmpl %o7+8, %g0
186	nop
187	main02:
188	mov 2,%l0
189	nop
190	nop
191	nop
192	nop
193	nop
194	nop
195	nop
196	nop
197	nop
198	main03:
199	mov 3,%l0
200	nop
201	nop
202	nop
203	nop
204	nop
205	nop
206	nop
207	nop
208	nop
209	nop
210	nop
211	nop
212	nop
213	nop
214	nop
215	nop
216	nop
217	nop
218	nop
219
220	main04:
221	mov 4,%l0
222	nop
223	nop
224	nop
225	nop
226	nop
227	nop
228	nop
229	nop
230	main05:
231	mov 5,%l0
232	nop
233	nop
234	nop
235	nop
236	nop
237
238	main06:
239	mov 1,%l0
240	nop
241	nop
242	nop
243	nop
244	nop
245	user_text2_end:
246
247	main_1:
248	main_4:
249	set main01,%i1 ! look at main1
250	set main02,%i2 ! look at main1
251	set main03,%i3 ! look at main1
252	set main04,%i4 ! look at main1
253	set main05,%i5 ! look at main1
254	set main06,%i6 ! look at main1
255
256	setx 0x100, %o2, %o3 ! loop counter
257
258	loop1or4_2:
259	ld [%i1], %l0
260	ld [%i1 + 0x10], %l1
261	nop
262	ld [%i2], %l0
263	ld [%i2 + 0x10], %l1
264	nop
265	ld [%i3], %l0
266	ld [%i3 + 0x10], %l1
267	nop
268	ld [%i4], %l0
269	ld [%i4 + 0x10], %l1
270	nop
271	ld [%i5], %l0
272	ld [%i5 + 0x10], %l1
273	nop
274	ld [%i6], %l0
275	ld [%i6 + 0x10], %l1
276	nop
277
278	dec %o3
279	brnz %o3, loop1or4_2
280	nop
281
282	ta T_GOOD_TRAP
283
284	/***********************************************************************
285	Test case data start
286	***********************************************************************/
287	.data
288	user_data_start:
289	.word 0x0
290	user_data_end: