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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: tso_n2_ncrdwr1.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | #define ASI_NUCLEUS 0x40 | |
40 | #define ASI_NUCLEUS_LITTLE 0xc0 | |
41 | #define ASI_BLK_P 0xf0 | |
42 | #define ASI_BLK_S 0xf1 | |
43 | #define ASI_BLK_PL 0xf8 | |
44 | #define ASI_BLK_SL 0xf9 | |
45 | #define ASI_BLK_INIT_ST_QUAD_LDD_P 0xe2 | |
46 | #define ASI_BLK_INIT_ST_QUAD_LDD_P 0xe3 | |
47 | #define ASI_NUCLEUS_QUAD_LDD 0x24 | |
48 | #define ENABLE_PCIE_LINK_TRAINING | |
49 | #include "hboot.s" | |
50 | ||
51 | .text | |
52 | .global main | |
53 | main: | |
54 | ta T_CHANGE_HPRIV | |
55 | nop | |
56 | ||
57 | /************************************ | |
58 | set up pointers | |
59 | *************************************/ | |
60 | setx 0xdeadbeefdeadbeef, %g1, %g2 | |
61 | setx 0xc100beef00, %g1, %g3 ! MEM32 address space | |
62 | /************************************ | |
63 | Start doing non cacheable access | |
64 | RW's are done to the DMUPIO space | |
65 | starting from 0xC1 | |
66 | *************************************/ | |
67 | !===================== | |
68 | ! Now some NC writes and reads | |
69 | !===================== | |
70 | mov %g0, %g4 | |
71 | set 0x1, %g2 | |
72 | set 0x10, %g5 | |
73 | ||
74 | stloop1: | |
75 | stx %g2, [%g3 + %g4] | |
76 | inc %g2 | |
77 | add 0x8, %g4, %g4 | |
78 | deccc %g5 | |
79 | bne stloop1 | |
80 | nop | |
81 | ||
82 | mov 0x78, %g4 | |
83 | set 0x10, %g2 | |
84 | set 0x10, %g5 | |
85 | ||
86 | ldloop1: | |
87 | ldx [%g3 + %g4], %g1 | |
88 | subcc %g2, %g1, %g0 | |
89 | bne h_bad_end | |
90 | nop | |
91 | dec %g2 | |
92 | sub %g4, 0x8, %g4 | |
93 | deccc %g5 | |
94 | bne ldloop1 | |
95 | nop | |
96 | ||
97 | !======================== | |
98 | mov %g0, %g4 | |
99 | set 0x1, %g2 | |
100 | set 0x10, %g5 | |
101 | ||
102 | stloop2: | |
103 | st %g2, [%g3 + %g4] | |
104 | inc %g2 | |
105 | add 0x4, %g4, %g4 | |
106 | deccc %g5 | |
107 | bne stloop2 | |
108 | nop | |
109 | ||
110 | mov 0x3c, %g4 | |
111 | set 0x10, %g2 | |
112 | set 0x10, %g5 | |
113 | ||
114 | ldloop2: | |
115 | ld [%g3 + %g4], %g1 | |
116 | subcc %g2, %g1, %g0 | |
117 | bne h_bad_end | |
118 | nop | |
119 | dec %g2 | |
120 | sub %g4, 0x4, %g4 | |
121 | deccc %g5 | |
122 | bne ldloop2 | |
123 | nop | |
124 | ||
125 | !============================= | |
126 | ||
127 | mov %g0, %g4 | |
128 | set 0x1, %g2 | |
129 | set 0x10, %g5 | |
130 | ||
131 | stloop3: | |
132 | sth %g2, [%g3 + %g4] | |
133 | inc %g2 | |
134 | add 0x2, %g4, %g4 | |
135 | deccc %g5 | |
136 | bne stloop3 | |
137 | nop | |
138 | ||
139 | mov 0x1e, %g4 | |
140 | set 0x10, %g2 | |
141 | set 0x10, %g5 | |
142 | ||
143 | ldloop3: | |
144 | lduh [%g3 + %g4], %g1 | |
145 | subcc %g2, %g1, %g0 | |
146 | bne h_bad_end | |
147 | nop | |
148 | dec %g2 | |
149 | sub %g4, 0x2, %g4 | |
150 | deccc %g5 | |
151 | bne ldloop3 | |
152 | nop | |
153 | ||
154 | !============================= | |
155 | mov %g0, %g4 | |
156 | set 0x1, %g2 | |
157 | set 0x10, %g5 | |
158 | ||
159 | stloop4: | |
160 | stb %g2, [%g3 + %g4] | |
161 | inc %g2 | |
162 | add 0x1, %g4, %g4 | |
163 | deccc %g5 | |
164 | bne stloop4 | |
165 | nop | |
166 | ||
167 | mov 0xf, %g4 | |
168 | set 0x10, %g2 | |
169 | set 0x10, %g5 | |
170 | ||
171 | ldloop4: | |
172 | ldub [%g3 + %g4], %g1 | |
173 | subcc %g2, %g1, %g0 | |
174 | bne h_bad_end | |
175 | nop | |
176 | dec %g2 | |
177 | sub %g4, 0x1, %g4 | |
178 | deccc %g5 | |
179 | bne ldloop4 | |
180 | nop | |
181 | ||
182 | normal_end: | |
183 | ta T_GOOD_TRAP | |
184 | nop | |
185 | ||
186 | h_bad_end: | |
187 | ta T_BAD_TRAP | |
188 | nop | |
189 | ||
190 | /* | |
191 | * Data section | |
192 | */ | |
193 | ||
194 | .data | |
195 | user_data_start: | |
196 | .word 0xD6B3479D | |
197 | .word 0xDB28926C | |
198 | .end |