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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: Debug_Event_L2PaBank.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define Soc_Decr_Pa 0x8600000010 | |
42 | ||
43 | ||
44 | #define L2_ERR_STAT_REG 0xAB00000000 | |
45 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
46 | ||
47 | #define TEST_DATA0 0x1000100081c3e008 | |
48 | #define TEST_DATA1 0x2000200081c3e008 | |
49 | #define TEST_DATA2 0x3000300081c3e008 | |
50 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
51 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
52 | ||
53 | #ifdef MCU0 | |
54 | #define L2_BANK_ADDR 0x0 | |
55 | #define MCU_BANK_ADDR 0x0 | |
56 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
57 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
58 | #define ERROR_ADDR 0x20200000 | |
59 | #define DBG_ERR_PA 0xAA00000000 | |
60 | #define DBG_ERR_VAL 0x4 | |
61 | #define Soc_Decr_Val 0x00000000000003 | |
62 | #define L2_Addr_Mask_Reg 0xAF00000000 | |
63 | #define L2_Addr_Mask_Val 0x000000002200aa00 | |
64 | #define L2_Addr_Cmp_Reg 0xBF00000000 | |
65 | #define L2_Addr_Cmp_Val 0x000000002200aa00 | |
66 | #endif | |
67 | ||
68 | #ifdef MCU1 | |
69 | #define L2_BANK_ADDR 0x80 | |
70 | #define MCU_BANK_ADDR 0x80 | |
71 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
72 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
73 | #define DBG_ERR_PA 0xAA00000080 | |
74 | #define DBG_ERR_VAL 0x4 | |
75 | #define Soc_Decr_Val 0x00000000000030 | |
76 | #define L2_Addr_Mask_Reg 0xAF00000080 | |
77 | #define L2_Addr_Mask_Val 0x000000002200aa00 | |
78 | #define L2_Addr_Cmp_Reg 0xBF00000080 | |
79 | #define L2_Addr_Cmp_Val 0x000000002200aa00 | |
80 | ||
81 | #endif | |
82 | ||
83 | #ifdef MCU2 | |
84 | #define L2_BANK_ADDR 0x100 | |
85 | #define MCU_BANK_ADDR 0x100 | |
86 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
87 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
88 | #define ERROR_ADDR 0x20200100 | |
89 | #define DBG_ERR_PA 0xAA00000100 | |
90 | #define DBG_ERR_VAL 0x4 | |
91 | #define Soc_Decr_Val 0x0000000000300 | |
92 | #define L2_Addr_Mask_Reg 0xAF00000100 | |
93 | #define L2_Addr_Mask_Val 0x000000002200aa00 | |
94 | #define L2_Addr_Cmp_Reg 0xBF00000100 | |
95 | #define L2_Addr_Cmp_Val 0x000000002200aa00 | |
96 | #endif | |
97 | ||
98 | #ifdef MCU3 | |
99 | #define L2_BANK_ADDR 0x180 | |
100 | #define MCU_BANK_ADDR 0x180 | |
101 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
102 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
103 | #define DBG_ERR_PA 0xAA00000180 | |
104 | #define DBG_ERR_VAL 0x4 | |
105 | #define Soc_Decr_Val 0x0000000003000 | |
106 | #define L2_Addr_Mask_Reg 0xAF00000180 | |
107 | #define L2_Addr_Mask_Val 0x000000002200aa00 | |
108 | #define L2_Addr_Cmp_Reg 0xBF00000180 | |
109 | #define L2_Addr_Cmp_Val 0x000000002200aa00 | |
110 | #endif | |
111 | ||
112 | ||
113 | #include "hboot.s" | |
114 | #include "asi_s.h" | |
115 | #include "err_defines.h" | |
116 | ||
117 | ||
118 | .text | |
119 | .global main | |
120 | .global My_Corrected_ECC_error_trap | |
121 | ||
122 | ||
123 | ||
124 | main: | |
125 | ta T_CHANGE_HPRIV | |
126 | setup_soc_decr_reg: | |
127 | setx L2_Addr_Mask_Reg,%l1,%l4 | |
128 | add %l4,L2_BANK_ADDR,%l4 | |
129 | setx L2_Addr_Mask_Val,%l2,%l3 | |
130 | add %l3,L2_BANK_ADDR,%l3 | |
131 | stx %l3,[%l4] | |
132 | nop | |
133 | membar 0x40 | |
134 | ||
135 | setx L2_Addr_Cmp_Reg,%l4,%l5 | |
136 | add %l5,L2_BANK_ADDR,%l5 | |
137 | setx L2_Addr_Cmp_Val,%g5,%g4 | |
138 | add %g4,L2_BANK_ADDR,%g4 | |
139 | stx %g4,[%l5] | |
140 | nop | |
141 | membar 0x40 | |
142 | ||
143 | nop | |
144 | setx Soc_Decr_Pa,%l1,%g4 | |
145 | setx Soc_Decr_Val,%l7,%g5 | |
146 | stx %g5,[%g4] | |
147 | nop | |
148 | membar 0x40 | |
149 | ||
150 | ||
151 | disable_l1: | |
152 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
153 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
154 | andn %l0, 0x3, %l0 | |
155 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
156 | ||
157 | ||
158 | clear_dram_esr_0: | |
159 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
160 | setx DRAM_ES_W1C_VALUE, %l0, %l5 | |
161 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
162 | ! add %g5, MCU_BANK_ADDR, %g5 | |
163 | stx %l5, [%g5] | |
164 | ||
165 | set_DRAM_error_inject_ch0: | |
166 | mov 0x606, %l1 ! ECC Mask (Multi-bit error) | |
167 | mov 0x1, %l2 | |
168 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
169 | Or %l1, %l3, %l1 ! Set single shot ; | |
170 | mov 0x1, %l2 | |
171 | sllx %l2, DRAM_EI_ENB, %l3 | |
172 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
173 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
174 | ! add %g6, MCU_BANK_ADDR, %g6 | |
175 | stx %l1, [%g6] | |
176 | membar 0x40 | |
177 | ||
178 | enable_err_reporting: | |
179 | setx L2EE_PA0, %l0, %l1 | |
180 | add %l1, L2_BANK_ADDR, %l1 | |
181 | ldx [%l1], %l2 | |
182 | mov 0x3, %l0 | |
183 | or %l2, %l0, %l2 | |
184 | stx %l2, [%l1] | |
185 | ||
186 | ||
187 | ! Write 1 to clear L2 Error status registers | |
188 | clear_l2_ESR: | |
189 | setx L2ES_PA0, %l3, %l4 | |
190 | add %l4, L2_BANK_ADDR, %l4 | |
191 | stx %l5, [%l4] | |
192 | nop | |
193 | ||
194 | set_L2_Off_Mode: | |
195 | setx L2CS_PA0, %l6, %g1 | |
196 | add %g1, L2_BANK_ADDR, %g1 | |
197 | mov 0x1, %l0 | |
198 | stx %l0, [%g1] | |
199 | ||
200 | ||
201 | store_to_L2_way0: | |
202 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
203 | add %g2, L2_BANK_ADDR, %g2 | |
204 | stx %g5, [%g2] | |
205 | membar #Sync | |
206 | read_error_address_ch0: | |
207 | ldx [%g2], %l1 | |
208 | membar #Sync | |
209 | ||
210 | ||
211 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
212 | write_mcu_channel_0: | |
213 | setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way | |
214 | add %g3, L2_BANK_ADDR, %g3 | |
215 | stx %g5, [%g3] | |
216 | membar #Sync | |
217 | ||
218 | /** | |
219 | *read_error_address_ch0: | |
220 | * ldx [%g2], %l1 | |
221 | * membar #Sync | |
222 | *! ldx [%g3], %l2 | |
223 | *! membar #Sync | |
224 | **/ | |
225 | ||
226 | ||
227 | check_DRAM_ESR_0: | |
228 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
229 | ! add %g5, MCU_BANK_ADDR, %g5 | |
230 | ldx [%g5], %l6 | |
231 | setx 0xffc0000000000000, %l0,%o2 | |
232 | and %l6,%o2,%l6 | |
233 | ||
234 | ||
235 | compute_dram_ESR: | |
236 | mov 0x1, %l1 | |
237 | sllx %l1, DRAM_ES_DAU, %l0 | |
238 | ||
239 | ||
240 | verify_dram_ESR: | |
241 | cmp %l0, %l6 | |
242 | // bne %xcc, test_fail | |
243 | nop | |
244 | ||
245 | check_L2_ESR_0: | |
246 | setx L2_ERR_STAT_REG, %l3, %g5 | |
247 | add %g5, L2_BANK_ADDR, %g5 | |
248 | ldx [%g5], %l6 | |
249 | ||
250 | compute_L2_ESR: | |
251 | setx 0xfffffffff0000000, %l3, %l0 | |
252 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits | |
253 | mov 0x1, %l1 | |
254 | sllx %l1, L2ES_DAU, %l0 | |
255 | mov 0x1, %l1 | |
256 | sllx %l1, L2ES_VEU, %l2 | |
257 | or %l0, %l2, %l3 | |
258 | ||
259 | verify_L2_ESR: | |
260 | cmp %l6, %l3 | |
261 | bne %xcc, test_fail | |
262 | nop | |
263 | ||
264 | ||
265 | setx L2EA_PA0, %l2, %l3 | |
266 | add %l3, L2_BANK_ADDR, %l3 | |
267 | check_l2_EAR: | |
268 | ldx [%l3], %l4 | |
269 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
270 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
271 | add %g2, L2_BANK_ADDR, %g2 | |
272 | ||
273 | setx 0xffffffffc0, %l0,%o2 | |
274 | and %l4, %o2, %l4 | |
275 | cmp %l4, %g2 | |
276 | // bne %xcc, test_fail | |
277 | nop | |
278 | ||
279 | check_Corr_err_trap: | |
280 | ! Check if a Corrected ECC Error Trap happened | |
281 | set EXECUTED, %l0 | |
282 | cmp %o0, %l0 | |
283 | // bne test_fail | |
284 | nop | |
285 | mov TT_Data_Access_Error, %l0 | |
286 | cmp %o1, %l0 | |
287 | // bne test_fail | |
288 | nop | |
289 | ||
290 | ||
291 | ba test_pass | |
292 | nop | |
293 | ||
294 | My_Corrected_ECC_error_trap: | |
295 | ||
296 | !My_Recoverable_Sw_error_trap: | |
297 | ! Signal trap taken | |
298 | setx EXECUTED, %l0, %o0 | |
299 | ! save trap type value | |
300 | rdpr %tt, %o1 | |
301 | retry | |
302 | nop | |
303 | ||
304 | ||
305 | /******************************************************* | |
306 | * Exit code | |
307 | *******************************************************/ | |
308 | ||
309 | test_pass: | |
310 | ta T_GOOD_TRAP | |
311 | ||
312 | ||
313 | test_fail: | |
314 | ta T_BAD_TRAP | |
315 | ||
316 | ||
317 |