[OpenSPARC-T2-DV] / verif / diag / assembly / dbp / Debug_Event_L2_Pa.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: Debug_Event_L2_Pa.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#define  DRAM_ERR_STAT_REG              0x8400000280
#define  L2_ERR_STAT_REG                0xAB00000000

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define ADDR1      		0xfffc00002000aa00
#define TEST_DATA1		0xaaaaaaaaaaaaaaaa
#define  DRAM_ERR_INJ_REG   	0x8400000290
#define  L2_ENTRY_PA        0xa000000000

#define ERR_BITS                0x2
#define ERR_BITS_EXPECT         0x8000000000000002

#define DBG_ERR_PA  0xAA00000000
#define DBG_ERR_VAL 0x7

/***Following will enable the MCU Debug Events in case of an Error*****/

#define  Soc_Decr_Pa         0x8600000010
#define  Soc_Decr_Val        0x00000000000003

#define  L2_Addr_Mask_Reg    0xAF00000000
#define  L2_Addr_Mask_Val    0x001f3f03fffffffc
#define  L2_Addr_Cmp_Reg     0xBF00000000
#define  L2_Addr_Cmp_Val     0x000100008000aa00	
    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0
setup_soc_decr_reg:
        setx L2_Addr_Mask_Reg,%l1,%g3
        setx L2_Addr_Cmp_Reg,%l4,%g7
        stx  %g7,[%g3]
	membar #Sync	
	
	
        setx Soc_Decr_Pa,%l1,%g3
        setx Soc_Decr_Val,%l4,%g7
        stx %g7,[%g3]
        nop
        nop

setup_dram_dbg:
          setx DBG_ERR_PA,%l0,%g1
          setx DBG_ERR_VAL,%l3,%g5
          stx %g5,[%g1]
          nop
          nop


disable_l1_DCache:
	ldxa  [%g0] ASI_LSU_CONTROL, %l0
	! Remove bit 2
	andn  %l0, 0x2, %l0
	stxa  %l0, [%g0] ASI_LSU_CONTROL

clear_l2_ESR:
	setx  L2_ES_W1C_VALUE, %l0, %l1
	setx  L2ES_PA0, %l6, %g1
	stx   %l1, [%g1]

set_L2_Directly_Mapped_Mode:
	setx  L2CS_PA0, %l6, %g1
	mov   0x2, %l0
	stx   %l0, [%g1]


store_to_L2:
	setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
	setx  0x2000aa00, %l0, %g2
	stx %g5, [%g2]
	stx %g5, [%g2+8]
	membar #Sync

	clr %l6
	set 0x7, %l5
loop:
	 inc %l6
	 cmp %l6,%l5
	 bne loop
	 nop

L2_diag_load:
	setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
	setx  L2_ENTRY_PA, %l0, %g4
	and   %g2, %l2, %g5
	or    %g5, %g4, %g5
	ldx   [%g5], %g6
	membar #Sync

! Flip two	bits
	xor    %g6, 0x600, %g6
	stx   %g6, [%g5]
	membar #Sync


L2_err_enable:
        set     0x7, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]


piu_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

dma_rdd:
	nop
UsrEvnt_rdd:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

cause_trap:
        setx    0x2000a000, %g3, %g1
        ldx     [%g1], %g2

        setx    0x2100a000, %g3, %g1
	stx	%g0, [%g1]

        setx    0x4100a000, %g3, %g1
        ldx     [%g1], %g2

eie_reg_ones_rdd:
        setx    SOC_EIE_REG, %g3, %g2
        setx 	0xffffffffffffffff, %g3, %g1
        stx     %g1, [%g2]
        membar  0x40

enable_l1_DCache:
        ldxa  [%g0] ASI_LSU_CONTROL, %l0
        or    %l0, 0x2, %l0
        stxa  %l0, [%g0] ASI_LSU_CONTROL


	set	0x1, %g1
        setx    0x30, %g7, %g6
err_trap_loop_rdd:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_tt_rdd
	nop

	ba	err_trap_loop_rdd
	nop

check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop


check_l2_trap_cnt:
	set	0x1, %l0
	cmp	%i0, %l0
	bne	test_failed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7
	inc	%i0

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
	ba	test_failed
	nop


l2_trap:
	nop

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu0_esr_L2Trap_tt40:
        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

      !  setx  0xffffffffffff0000, %l2, %l1
      !  andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %g0, %l4, %i4
        brnz    %i4, test_failed
        nop


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEC bit

        mov   	0x1, %l1
        sllx  	%l1, L2ES_LDRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]

trap_done_tt40:
       	done 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: Debug_Event_L2_Pa.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#define DRAM_ERR_STAT_REG 0x8400000280
	46	#define L2_ERR_STAT_REG 0xAB00000000
	47
	48	#include "err_defines.h"
	49	#include "hboot.s"
	50	#include "peu_defines.h"
	51
	52	#define DMA_DATA_ADDR 0x0000000123456700
	53	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	54	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	55	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	56
	57	#define DMA_DATA_ADDR 0x0000000123456700
	58	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	59	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	60
	61	#define ADDR1 0xfffc00002000aa00
	62	#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
	63	#define DRAM_ERR_INJ_REG 0x8400000290
	64	#define L2_ENTRY_PA 0xa000000000
65
66	#define ERR_BITS 0x2
67	#define ERR_BITS_EXPECT 0x8000000000000002
68
69	#define DBG_ERR_PA 0xAA00000000
70	#define DBG_ERR_VAL 0x7
71
72	/*Following will enable the MCU Debug Events in case of an Error***/
73
74	#define Soc_Decr_Pa 0x8600000010
75	#define Soc_Decr_Val 0x00000000000003
76
77	#define L2_Addr_Mask_Reg 0xAF00000000
78	#define L2_Addr_Mask_Val 0x001f3f03fffffffc
79	#define L2_Addr_Cmp_Reg 0xBF00000000
80	#define L2_Addr_Cmp_Val 0x000100008000aa00
81
82	/************************************************************************
83	Test case code start
84	************************************************************************/
85	.text
86	.global main
87	.global My_Corrected_ECC_error_trap
88	.global My_Recoverable_Sw_error_trap
89
90	main:
91	ta T_CHANGE_HPRIV
92	nop
93
94	clr %i7
95	clr %o6
96	clr %o7
97	clr %i0
98	setup_soc_decr_reg:
99	setx L2_Addr_Mask_Reg,%l1,%g3
100	setx L2_Addr_Cmp_Reg,%l4,%g7
101	stx %g7,[%g3]
102	membar #Sync
103
104
105	setx Soc_Decr_Pa,%l1,%g3
106	setx Soc_Decr_Val,%l4,%g7
107	stx %g7,[%g3]
108	nop
109	nop
110
111	setup_dram_dbg:
112	setx DBG_ERR_PA,%l0,%g1
113	setx DBG_ERR_VAL,%l3,%g5
114	stx %g5,[%g1]
115	nop
116	nop
117
118
119	disable_l1_DCache:
120	ldxa [%g0] ASI_LSU_CONTROL, %l0
121	! Remove bit 2
122	andn %l0, 0x2, %l0
123	stxa %l0, [%g0] ASI_LSU_CONTROL
124
125	clear_l2_ESR:
126	setx L2_ES_W1C_VALUE, %l0, %l1
127	setx L2ES_PA0, %l6, %g1
128	stx %l1, [%g1]
129
130	set_L2_Directly_Mapped_Mode:
131	setx L2CS_PA0, %l6, %g1
132	mov 0x2, %l0
133	stx %l0, [%g1]
134
135
136	store_to_L2:
137	setx TEST_DATA1, %l0, %g5
138
139	store_to_L2_way0:
140	setx 0x2000aa00, %l0, %g2
141	stx %g5, [%g2]
142	stx %g5, [%g2+8]
143	membar #Sync
144
145	clr %l6
146	set 0x7, %l5
147	loop:
148	inc %l6
149	cmp %l6,%l5
150	bne loop
151	nop
152
153	L2_diag_load:
154	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
155	setx L2_ENTRY_PA, %l0, %g4
156	and %g2, %l2, %g5
157	or %g5, %g4, %g5
158	ldx [%g5], %g6
159	membar #Sync
160
161	! Flip two bits
162	xor %g6, 0x600, %g6
163	stx %g6, [%g5]
164	membar #Sync
165
166
167	L2_err_enable:
168	set 0x7, %l1
169	mov 0xaa, %g2
170	sllx %g2, 32, %g2
171	stx %l1, [%g2]
172	stx %l1, [%g2 + 0x40]
173	stx %l1, [%g2 + 0x80]
174	stx %l1, [%g2 + 0xc0]
175	stx %l1, [%g2 + 0x100]
176	stx %l1, [%g2 + 0x140]
177	stx %l1, [%g2 + 0x180]
178	stx %l1, [%g2 + 0x1c0]
179
180
181	piu_iommu:
182	! enable bypass in IOMMU
183	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
184	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
185	stx %g3, [%g2]
186	ldx [%g2], %g3
187
188	dma_rdd:
189	nop
190	UsrEvnt_rdd:
191	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, , )
192
193	ldx [%g2], %g3
194	ldx [%g2], %g3
195	ldx [%g2], %g3
196	ldx [%g2], %g3
197
198	cause_trap:
199	setx 0x2000a000, %g3, %g1
200	ldx [%g1], %g2
201
202	setx 0x2100a000, %g3, %g1
203	stx %g0, [%g1]
204
205	setx 0x4100a000, %g3, %g1
206	ldx [%g1], %g2
207
208	eie_reg_ones_rdd:
209	setx SOC_EIE_REG, %g3, %g2
210	setx 0xffffffffffffffff, %g3, %g1
211	stx %g1, [%g2]
212	membar 0x40
213
214	enable_l1_DCache:
215	ldxa [%g0] ASI_LSU_CONTROL, %l0
216	or %l0, 0x2, %l0
217	stxa %l0, [%g0] ASI_LSU_CONTROL
218
219
220	set 0x1, %g1
221	setx 0x30, %g7, %g6
222	err_trap_loop_rdd:
223	cmp %g6, %g0
224	be %xcc, test_failed
225	nop
226
227	cmp %g1, %i7
228	be %xcc, check_tt_rdd
229	nop
230
231	ba err_trap_loop_rdd
232	nop
233
234	check_tt_rdd:
235	mov 0x40, %l0
236	cmp %o7, %l0
237	bne %xcc, test_failed
238	nop
239
240
241	check_l2_trap_cnt:
242	set 0x1, %l0
243	cmp %i0, %l0
244	bne test_failed
245	nop
246
247	test_passed:
248	EXIT_GOOD
249
250	test_failed:
251	EXIT_BAD
252
253
254	/************************************************************************
255	RAS
256	Trap Handlers
257	************************************************************************/
258	My_Recoverable_Sw_error_trap:
259	! Signal trap taken
260	setx EXECUTED, %l0, %o6
261	! save trap type value
262	rdpr %tt, %o7
263
264	inc %i7
265	inc %i0
266
267	check_desr_NcuTrap_tt40:
268	ldxa [%g0]0x4c, %g2
269	nop
270
271	setx 0xb300000000000000, %l0, %g3
272	subcc %g2, %g3, %g4
273	brnz %g4, l2_trap
274	nop
275
276	check_per_tt40:
277	ba test_failed
278	nop
279
280
281	l2_trap:
282	nop
283
284	check_desr_L2Trap_tt40:
285	setx 0xb000000000000000, %l0, %g3
286	subcc %g2, %g3, %g4
287	brnz %g4, test_failed
288	nop
289
290	check_mcu0_esr_L2Trap_tt40:
291	setx DRAM_ERR_STAT_REG, %l3, %g5
292	ldx [%g5], %l3
293
294	! setx 0xffffffffffff0000, %l2, %l1
295	! andcc %l1, %l3, %l4 ! Donot check SYND bits
296
297	sub %g0, %l4, %i4
298	brnz %i4, test_failed
299	nop
300
301
302	check_L2_4_ESR_L2Trap_tt40:
303	setx L2_ERR_STAT_REG, %l3, %g5
304	ldx [%g5], %l6
305
306	setx 0x7ffffffff0000000, %l3, %l0
307	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEC bit
308
309	mov 0x1, %l1
310	sllx %l1, L2ES_LDRU, %l0
311
312	mov 0x1, %l1
313	sllx %l1, L2ES_VEU, %l2
314
315	or %l0, %l2, %i4
316
317	cmp %l5, %i4
318	bne %xcc, test_failed
319	nop
320
321	clear_l2_esr_L2Trap_tt40:
322	stx %g0, [%g5]
323
324	trap_done_tt40:
325	done
326	nop
327
328
329
330	My_Corrected_ECC_error_trap:
331	ba test_failed
332	nop
333
334
335	/************************************************************************
336	Test case data start
337	************************************************************************/
338
339	SECTION .DATA DATA_VA=DMA_DATA_ADDR
340	attr_data {
341	Name = .DATA,
342	hypervisor,
343	compressimage
344	}
345
346	.data
347	.global PCIAddr9
348	.xword 0x0001020304050607
349	.xword 0x08090a0b0c0d0e0f
350	.xword 0x1011121314151617
351	.xword 0x18191a1b1c1d1e1f
352	.xword 0x2021222324252627
353	.xword 0x28292a2b2c2d2e2f
354	.xword 0x3031323334353637
355	.xword 0x38393a3b3c3d3e3f
356
357	.xword 0x4041424344454647
358	.xword 0x48494a4b4c4d4e4f
359	.xword 0x5051525354555657
360	.xword 0x58595a5b5c5d5e5f
361	.xword 0x6061626364656667
362	.xword 0x68696a6b6c6d6e6f
363	.xword 0x7071727374757677
364	.xword 0x78797a7b7c7d7e7f
365
366	.xword 0x8081828384858687
367	.xword 0x88898a8b8c8d8e8f
368	.xword 0x9091929394959697
369	.xword 0x98999a9b9c9d9e9f
370	.xword 0xa0a1a2a3a4a5a6a7
371	.xword 0xa8a9aaabacadaeaf
372	.xword 0xb0b1b2b3b4b5b6b7
373	.xword 0xb8b9babbbcbdbebf
374
375	.xword 0xc0c1c2c3c4c5c6c7
376	.xword 0xc8c9cacbcccdcecf
377	.xword 0xd0d1d2d3d4d5d6d7
378	.xword 0xd8d9dadbdcdddedf
379	.xword 0xe0e1e2e3e4e5e6e7
380	.xword 0xe8e9eaebecedeeef
381	.xword 0xf0f1f2f3f4f5f6f7
382	.xword 0xf8f9fafbfcfdfeff
383
384	.xword 0x0001020304050607
385	.xword 0x08090a0b0c0d0e0f
386	.xword 0x1011121314151617
387	.xword 0x18191a1b1c1d1e1f
388	.xword 0x2021222324252627
389	.xword 0x28292a2b2c2d2e2f
390	.xword 0x3031323334353637
391	.xword 0x38393a3b3c3d3e3f
392
393	.xword 0x4041424344454647
394	.xword 0x48494a4b4c4d4e4f
395	.xword 0x5051525354555657
396	.xword 0x58595a5b5c5d5e5f
397	.xword 0x6061626364656667
398	.xword 0x68696a6b6c6d6e6f
399	.xword 0x7071727374757677
400	.xword 0x78797a7b7c7d7e7f
401
402	.xword 0x8081828384858687
403	.xword 0x88898a8b8c8d8e8f
404	.xword 0x9091929394959697
405	.xword 0x98999a9b9c9d9e9f
406	.xword 0xa0a1a2a3a4a5a6a7
407	.xword 0xa8a9aaabacadaeaf
408	.xword 0xb0b1b2b3b4b5b6b7
409	.xword 0xb8b9babbbcbdbebf
410
411	.xword 0xc0c1c2c3c4c5c6c7
412	.xword 0xc8c9cacbcccdcecf
413	.xword 0xd0d1d2d3d4d5d6d7
414	.xword 0xd8d9dadbdcdddedf
415	.xword 0xe0e1e2e3e4e5e6e7
416	.xword 0xe8e9eaebecedeeef
417	.xword 0xf0f1f2f3f4f5f6f7
418	.xword 0xf8f9fafbfcfdfeff
419
420	/************************************************************************/
421
422