[OpenSPARC-T2-DV] / verif / diag / assembly / debug / checkp / checkpoint_replay.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: checkpoint_replay.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ASI_INTR_ID 0x63

#define PART_0_BASE 0x100000000
#define CREGS_L2_CTL_REG 0x000000
#define KERNEL_BASE_DATA_VA      0x1f0c34000
#define KERNEL_BASE_DATA_RA      0x0f0c34000
#define KERNEL_BASE_TEXT_VA 0x1f1834000
#define KERNEL_BASE_TEXT_RA 0x0f1834000
#define MAIN_BASE_BSS_VA  0x1e0400000
#define MAIN_BASE_BSS_RA  0x0e0400000
#define MAIN_BASE_TEXT_VA 0x1e0200000
#define MAIN_BASE_TEXT_RA 0x0e0200000
#define MAIN_BASE_DATA_VA 0x1e0300000
#define MAIN_BASE_DATA_RA 0x0e0300000
/*put htrap code out of the way of the checkpoint memimage */
#define HV_RED_TEXT_PA          0x1f0040000
#define HV_RED_DATA_PA          0x1f004c000
#define HV_TRAP_BASE_PA         0x1f0080000
#define HV_TRAP_DATA_PA         0x1f008c000
#define PART0_Z_ADDR_0 0x1f0100000
#define PART0_NZ_ADDR_0 0x1f0200000
#define PART_0_LINK_AREA_BASE_ADDR 0x1f0300000
#define USER_HEAP_DATA_RA    0x0f0400000
#if 0
#define PART7_D_NZ_PS1_ADDR     0x1f4000000
#define PART0_D_NZ_PS0_ADDR     0x1f0600000
#define PART0_D_Z_PS0_ADDR      0x1f0500000
#define PART0_I_NZ_PS1_ADDR     0x1f0400000
#define PART0_I_Z_PS1_ADDR      0x1f0300000
#define PART0_I_NZ_PS0_ADDR     0x1f0200000
#define PART0_I_Z_PS0_ADDR      0x1f0100000

#endif
!no interrupts until after checkpointing so we can warm up the int pending regs correctly
#define CREGS_TSTATE_PSTATE_IE 0
#define CREGS_FPRS_FEF 1
#define DEBUG_INIT
#include "hboot.s"
#include "my_console.h"

!
! This is a generated diag. for 3des encription checking.
!
	.text
	.global main
main:
	nop
	ta      T_CHANGE_HPRIV
	nop
#ifdef CCU_NOCHANGE
	setx 0x8300000000, %g2, %g4
	mov  1, %g3
	sllx %g3, 32, %g3
	ldx  [%g4], %g2
	andn %g2, %g3, %g3
	stx  %g3, [%g4]    !clear change bit in ccu
#endif

#if 0
	ldxa    [%g0]ASI_INTR_ID, %g3
	andcc %g3, 0x3f, %g0
	bne no_print
	nop
!work around axis dram init problem. Not l2 miss while writing RAs bits
setx 0x1000, %g1, %g4
setx 0x9700000008, %g1, %g2
set 0xe, %g3
ba,a 1f
.align 0x40
1:
stx %g3, [%g2]
add %g2, %g4, %g2
stx %g3, [%g2]
add %g2, %g4, %g2
stx %g3, [%g2]
add %g2, %g4, %g2
stx %g3, [%g2]

!dram_ras_addr_width_reg <- e


setx 0x8000010020, %g1, %g2
!jbi_error_ovf <- 0
!stx %g3, [%g2]
sub %g0, 1, %g3
stx %g3, [%g2]
add %g2, 8, %g2
stx %g3, [%g2]
setx 0x8000010080, %g1, %g2
stx %g3, [%g2]
add %g2, 8, %g2
stx %g3, [%g2]
add %g2, 8, %g2
stx %g3, [%g2]
add %g2, 8, %g2
stx %g3, [%g2]
add %g2, 8, %g2
stx %g3, [%g2]

#include "system_regs.h.new.2"
#define HV_UART               0xfff0c2c000
setx    HV_UART, %g2, %g1
	ba uart_init
	rd %pc, %g7

! PRINT("\r\n");
!
!        PRINT("##### Reset/Config start #####\r\n");
!                PRINT("\r\n");
!                        PRINT("Reset status ...\r\n");

#ifdef SYNC_HACK_LOOP
	setx 0x800e602040, %g3, %g5
	sub %g0, 0x1, %g3
	stx %g3, [%g5]
	set SYNC_HACK_LOOP, %g1
1:
	ldx [%g5], %g3
	subcc %g1, 1, %g1
	bne 1b
	nop
#endif
	!IOB j int vec
	setx 0x9800000a00, %g3, %g5
	mov 0x1f, %g3
	stx %g3, [%g5]
#ifdef JBUS_DEBUG_PORT
!debug port setup
 setx 0x9800001820, %g3, %g2
!clear
 stx %g0, [%g2]
 stx %g0, [%g2+0x8]
 stx %g0, [%g2+0x10]
 stx %g0, [%g2+0x18]
 stx %g0, [%g2+0x20]
 setx 0x8, %g2, %g1           ; setx 0x9800001800, %g3, %g2; stx %g1, [%g2]
 setx 0x100, %g2, %g1         ; setx 0x9800002000, %g3, %g2; stx %g1, [%g2]
 setx 0x10000, %g2, %g1       ; setx 0x9800002100, %g3, %g2; stx %g1, [%g2]
 setx 0x3000ffffffff, %g2, %g1; setx 0x9800002140, %g3, %g2; stx %g1, [%g2]
 setx 0x0000ffffffff, %g2, %g1; setx 0x9800002148, %g3, %g2; stx %g1, [%g2]
 setx 0x3000ffffffff, %g2, %g1; setx 0x9800002180, %g3, %g2; stx %g1, [%g2]
 setx 0x0000ffffffff, %g2, %g1; setx 0x9800002188, %g3, %g2; stx %g1, [%g2]
 setx 0x6105ff, %g2, %g1      ; setx 0x8000004100, %g3, %g2; stx %g1, [%g2]
#endif
no_print:
!enable dbg port for bank 0
setx 0xa900000000, %g1, %g4
mov 1, %g1
sllx %g1, 20, %g1
stx %g1, [%g4]

#if 0
!only replay 1 thread per core for now
	ldxa    [%g0]ASI_INTR_ID, %g3
	andcc %g3, 0x7, %g0
	be do_replay
	nop
	ba,a diag_pass
#endif

do_replay:
!poke uart control addr so that write fifo will appear empty
   !     setx 0x1f10002005, %g1, %g2
   !     mov 0x40, %g1
   !     stb %g1,[%g2]
   !     wrpr %g0, 1, %tl
   !     wrhpr %g0, 0, %htstate

	!%tl save addr
	! setx 0x0000000000101148, %g2, %g1
	setx 0x0000000100801148, %g2, %g1
	ldxa    [%g0]ASI_INTR_ID, %g3
	and     %g3, 0x3f, %g3
	sllx    %g3, 16 , %g3
	add %g1, %g3, %g3
	ldx [%g3], %g3
#endif
#include "replay.s"

des_test:

start_msg_0:


diag_pass:
	ta T_GOOD_TRAP
	nop
#include "my_console.s"
/*
 ********************************
 *      Diag FAILED !           *
 ********************************
 */

diag_fail:
	set     0xdeadcafe,     %l7
	ta T_BAD_TRAP
	nop
	nop

	.data
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: checkpoint_replay.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ASI_INTR_ID 0x63
	39
	40	#define PART_0_BASE 0x100000000
	41	#define CREGS_L2_CTL_REG 0x000000
	42	#define KERNEL_BASE_DATA_VA 0x1f0c34000
	43	#define KERNEL_BASE_DATA_RA 0x0f0c34000
	44	#define KERNEL_BASE_TEXT_VA 0x1f1834000
	45	#define KERNEL_BASE_TEXT_RA 0x0f1834000
	46	#define MAIN_BASE_BSS_VA 0x1e0400000
	47	#define MAIN_BASE_BSS_RA 0x0e0400000
	48	#define MAIN_BASE_TEXT_VA 0x1e0200000
	49	#define MAIN_BASE_TEXT_RA 0x0e0200000
	50	#define MAIN_BASE_DATA_VA 0x1e0300000
	51	#define MAIN_BASE_DATA_RA 0x0e0300000
	52	/put htrap code out of the way of the checkpoint memimage /
	53	#define HV_RED_TEXT_PA 0x1f0040000
	54	#define HV_RED_DATA_PA 0x1f004c000
	55	#define HV_TRAP_BASE_PA 0x1f0080000
	56	#define HV_TRAP_DATA_PA 0x1f008c000
	57	#define PART0_Z_ADDR_0 0x1f0100000
	58	#define PART0_NZ_ADDR_0 0x1f0200000
	59	#define PART_0_LINK_AREA_BASE_ADDR 0x1f0300000
	60	#define USER_HEAP_DATA_RA 0x0f0400000
	61	#if 0
	62	#define PART7_D_NZ_PS1_ADDR 0x1f4000000
	63	#define PART0_D_NZ_PS0_ADDR 0x1f0600000
	64	#define PART0_D_Z_PS0_ADDR 0x1f0500000
65	#define PART0_I_NZ_PS1_ADDR 0x1f0400000
66	#define PART0_I_Z_PS1_ADDR 0x1f0300000
67	#define PART0_I_NZ_PS0_ADDR 0x1f0200000
68	#define PART0_I_Z_PS0_ADDR 0x1f0100000
69
70	#endif
71	!no interrupts until after checkpointing so we can warm up the int pending regs correctly
72	#define CREGS_TSTATE_PSTATE_IE 0
73	#define CREGS_FPRS_FEF 1
74	#define DEBUG_INIT
75	#include "hboot.s"
76	#include "my_console.h"
77
78	!
79	! This is a generated diag. for 3des encription checking.
80	!
81	.text
82	.global main
83	main:
84	nop
85	ta T_CHANGE_HPRIV
86	nop
87	#ifdef CCU_NOCHANGE
88	setx 0x8300000000, %g2, %g4
89	mov 1, %g3
90	sllx %g3, 32, %g3
91	ldx [%g4], %g2
92	andn %g2, %g3, %g3
93	stx %g3, [%g4] !clear change bit in ccu
94	#endif
95
96	#if 0
97	ldxa [%g0]ASI_INTR_ID, %g3
98	andcc %g3, 0x3f, %g0
99	bne no_print
100	nop
101	!work around axis dram init problem. Not l2 miss while writing RAs bits
102	setx 0x1000, %g1, %g4
103	setx 0x9700000008, %g1, %g2
104	set 0xe, %g3
105	ba,a 1f
106	.align 0x40
107	1:
108	stx %g3, [%g2]
109	add %g2, %g4, %g2
110	stx %g3, [%g2]
111	add %g2, %g4, %g2
112	stx %g3, [%g2]
113	add %g2, %g4, %g2
114	stx %g3, [%g2]
115
116	!dram_ras_addr_width_reg <- e
117
118
119
120	setx 0x8000010020, %g1, %g2
121	!jbi_error_ovf <- 0
122	!stx %g3, [%g2]
123	sub %g0, 1, %g3
124	stx %g3, [%g2]
125	add %g2, 8, %g2
126	stx %g3, [%g2]
127	setx 0x8000010080, %g1, %g2
128	stx %g3, [%g2]
129	add %g2, 8, %g2
130	stx %g3, [%g2]
131	add %g2, 8, %g2
132	stx %g3, [%g2]
133	add %g2, 8, %g2
134	stx %g3, [%g2]
135	add %g2, 8, %g2
136	stx %g3, [%g2]
137
138	#include "system_regs.h.new.2"
139	#define HV_UART 0xfff0c2c000
140	setx HV_UART, %g2, %g1
141	ba uart_init
142	rd %pc, %g7
143
144	! PRINT("\r\n");
145	!
146	! PRINT("##### Reset/Config start #####\r\n");
147	! PRINT("\r\n");
148	! PRINT("Reset status ...\r\n");
149
150	#ifdef SYNC_HACK_LOOP
151	setx 0x800e602040, %g3, %g5
152	sub %g0, 0x1, %g3
153	stx %g3, [%g5]
154	set SYNC_HACK_LOOP, %g1
155	1:
156	ldx [%g5], %g3
157	subcc %g1, 1, %g1
158	bne 1b
159	nop
160	#endif
161	!IOB j int vec
162	setx 0x9800000a00, %g3, %g5
163	mov 0x1f, %g3
164	stx %g3, [%g5]
165	#ifdef JBUS_DEBUG_PORT
166	!debug port setup
167	setx 0x9800001820, %g3, %g2
168	!clear
169	stx %g0, [%g2]
170	stx %g0, [%g2+0x8]
171	stx %g0, [%g2+0x10]
172	stx %g0, [%g2+0x18]
173	stx %g0, [%g2+0x20]
174	setx 0x8, %g2, %g1 ; setx 0x9800001800, %g3, %g2; stx %g1, [%g2]
175	setx 0x100, %g2, %g1 ; setx 0x9800002000, %g3, %g2; stx %g1, [%g2]
176	setx 0x10000, %g2, %g1 ; setx 0x9800002100, %g3, %g2; stx %g1, [%g2]
177	setx 0x3000ffffffff, %g2, %g1; setx 0x9800002140, %g3, %g2; stx %g1, [%g2]
178	setx 0x0000ffffffff, %g2, %g1; setx 0x9800002148, %g3, %g2; stx %g1, [%g2]
179	setx 0x3000ffffffff, %g2, %g1; setx 0x9800002180, %g3, %g2; stx %g1, [%g2]
180	setx 0x0000ffffffff, %g2, %g1; setx 0x9800002188, %g3, %g2; stx %g1, [%g2]
181	setx 0x6105ff, %g2, %g1 ; setx 0x8000004100, %g3, %g2; stx %g1, [%g2]
182	#endif
183	no_print:
184	!enable dbg port for bank 0
185	setx 0xa900000000, %g1, %g4
186	mov 1, %g1
187	sllx %g1, 20, %g1
188	stx %g1, [%g4]
189
190	#if 0
191	!only replay 1 thread per core for now
192	ldxa [%g0]ASI_INTR_ID, %g3
193	andcc %g3, 0x7, %g0
194	be do_replay
195	nop
196	ba,a diag_pass
197	#endif
198
199	do_replay:
200	!poke uart control addr so that write fifo will appear empty
201	! setx 0x1f10002005, %g1, %g2
202	! mov 0x40, %g1
203	! stb %g1,[%g2]
204	! wrpr %g0, 1, %tl
205	! wrhpr %g0, 0, %htstate
206
207	!%tl save addr
208	! setx 0x0000000000101148, %g2, %g1
209	setx 0x0000000100801148, %g2, %g1
210	ldxa [%g0]ASI_INTR_ID, %g3
211	and %g3, 0x3f, %g3
212	sllx %g3, 16 , %g3
213	add %g1, %g3, %g3
214	ldx [%g3], %g3
215	#endif
216	#include "replay.s"
217
218	des_test:
219
220	start_msg_0:
221
222
223	diag_pass:
224	ta T_GOOD_TRAP
225	nop
226	#include "my_console.s"
227	/*
228	********************************
229	* Diag FAILED ! *
230	********************************
231	*/
232
233	diag_fail:
234	set 0xdeadcafe, %l7
235	ta T_BAD_TRAP
236	nop
237	nop
238
239	.data
240