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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / debug / checkp / replay.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: replay.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ASI_INTR_ID 0x63
39#include "checkp.h"
40.seg "text"
41.register %g2,#scratch
42.register %g3,#scratch
43.register %g6,#scratch
44.register %g7,#scratch
45/*{{{ dump memory (rdaddr,wraddr, tempreg, tempreg1, count)*/
46#define dump_memory(rdaddr,wraddr, tempreg, tempreg1, count) \
476: ;\
48ldda [rdaddr]0xf0, %f0 ;\
49stda %f0, [wraddr]0xe0 ;\
50add rdaddr, 0x40, rdaddr ;\
51subcc count, 0x40, count ;\
52bne 6b ;\
53add wraddr, 0x40, wraddr ;\
54membar #Sync ;\
55
56/*}}} */
57/*{{{ dump pages (rdaddr,wraddr, temppage, tempreg, tempreg1, tempreg2, asi_num, stride, count)*/
58#define PA_MASK 0x7ffffffe000
59/*
60 save
61*/
62#define dump_pages(rdaddr,wraddr, temppage, tempreg, tempreg1, tempreg2, asi_num, stride, count) \
63ldxa [%g0]0x45, tempreg1 ;\
64mov 3, tempreg2 ;\
65sllx tempreg2, 48, tempreg2 ;\
66xor tempreg1, tempreg2, tempreg1 ;\
67xor tempreg1, 8, tempreg1 ;\
68stxa tempreg1, [%g0]0x45 ;\
69membar #Sync ;\
70ba 8f ;\
71nop ;\
720: ;\
73ldxa [rdaddr]asi_num, tempreg ;\
74 ;\
75setx PA_MASK, tempreg2, tempreg1 ;\
76srlx tempreg, 61, tempreg2 ;\
77and tempreg, tempreg1, tempreg ;\
78 ;\
79mov 1, tempreg1 ;\
80subcc tempreg2, 0x4, %g0 ;\
81be 1f ;\
82nop ;\
83subcc tempreg2, 0x5, %g0 ;\
84be 2f ;\
85nop ;\
86subcc tempreg2, 0x6, %g0 ;\
87be 3f ;\
88nop ;\
89subcc tempreg2, 0x7, %g0 ;\
90be 4f ;\
91nop ;\
92ba 7f ;\
93nop ;\
94 ;\
951: ;\
96sllx tempreg1, 13, tempreg1 ;\
97ba 5f ;\
98nop ;\
992: ;\
100sllx tempreg1, 16, tempreg1 ;\
101ba 5f ;\
102nop ;\
1033: ;\
104sllx tempreg1, 19, tempreg1 ;\
105ba 5f ;\
106nop ;\
1074: ;\
108sllx tempreg1, 22, tempreg1 ;\
1095: ;\
110srlx tempreg, 40, tempreg2 ;\
111andcc tempreg2, 7, tempreg2 ;\
112brnz tempreg2,7f ;\
113nop ;\
114stxa tempreg, [temppage]0x14 ;\
115setx 0x4000e602100, tempreg, tempreg2 ;\
116ldxa [temppage]0x14, tempreg ; \
117stxa tempreg, [tempreg2]0x15 ; \
1188: ;\
119set 1, tempreg1 ;\
120sllx tempreg1, 28, tempreg1 ;\
121set 0x3, tempreg ;\
122sllx tempreg, 28, tempreg ;\
1236: ;\
124ldda [tempreg]0xf0, %f0 ;\
125stda %f0, [wraddr]0xe0 ;\
126add tempreg, 0x40, tempreg ;\
127subcc tempreg1, 0x40, tempreg1 ;\
128bne 6b ;\
129add wraddr, 0x40, wraddr ;\
130membar #Sync ;\
131ba 9f ;\
1327: ;\
133subcc count, 1, count ;\
134bne 0b ;\
135add rdaddr, stride, rdaddr ;\
1369: ;\
137membar #Sync ;\
138ldxa [%g0]0x45, tempreg1 ;\
139mov 3, tempreg2 ;\
140sllx tempreg2, 48, tempreg2 ;\
141xor tempreg1, 8, tempreg1 ;\
142xor tempreg1, tempreg2, tempreg1 ;\
143stxa tempreg1, [%g0]0x45 ;\
144membar #Sync ;\
145
146
147
148!stxa wraddr, [tempreg2]0x15 ; \
149!ba 7f ;\
150!nop ;\
151!ldxa [tempreg]0x14, %f0 ;\
152
153/*}}} */
154/*{{{ 64bit asi x8 dump (rdaddr,wraddr, tempaddr, tempreg, asi, stride, count)*/
155
156#define asi_dump(rdaddr,wraddr, tempaddr, tempreg, asi_num, stride, count) \
157srlx count, 3, count ;\
1581: \
159ldxa [rdaddr]asi_num, tempreg ;\
160add rdaddr, stride, rdaddr ;\
161stx tempreg,[tempaddr] ;\
162ldd [tempaddr], %f0 ;\
163 ;\
164ldxa [rdaddr]asi_num, tempreg ;\
165add rdaddr, stride, rdaddr ;\
166stx tempreg,[tempaddr+0x8] ;\
167ldd [tempaddr+0x8], %f2 ;\
168 ;\
169ldxa [rdaddr]asi_num, tempreg ;\
170add rdaddr, stride, rdaddr ;\
171stx tempreg,[tempaddr+0x10] ;\
172ldd [tempaddr+0x10], %f4 ;\
173 ;\
174ldxa [rdaddr]asi_num, tempreg ;\
175add rdaddr, stride, rdaddr ;\
176stx tempreg,[tempaddr+0x18] ;\
177ldd [tempaddr+0x18], %f6 ;\
178 ;\
179ldxa [rdaddr]asi_num, tempreg ;\
180add rdaddr, stride, rdaddr ;\
181stx tempreg,[tempaddr+0x20] ;\
182ldd [tempaddr+0x20], %f8 ;\
183 ;\
184ldxa [rdaddr]asi_num, tempreg ;\
185add rdaddr, stride, rdaddr ;\
186stx tempreg,[tempaddr+0x28] ;\
187ldd [tempaddr+0x28], %f10 ;\
188 ;\
189ldxa [rdaddr]asi_num, tempreg ;\
190add rdaddr, stride, rdaddr ;\
191stx tempreg,[tempaddr+0x30] ;\
192ldd [tempaddr+0x30], %f12 ;\
193 ;\
194ldxa [rdaddr]asi_num, tempreg ;\
195add rdaddr, stride, rdaddr ;\
196stx tempreg,[tempaddr+0x38] ;\
197ldd [tempaddr+0x38], %f14 ;\
198 ;\
199membar #Sync ;\
200stda %f0, [wraddr]0xf0 ;\
201add wraddr, 0x40, wraddr ;\
202subcc count, 1, count ;\
203bne 1b ;\
204nop
205
206!copy data out to memory ;\
207! ldda [tempaddr]0xf0,%f0 ;\
208
209/*}}} */
210/*{{{ dmmu off*/
211#define dmmu_off(tempreg1, tempreg2) \
212set 3, tempreg2 ;\
213sllx tempreg2, 48, tempreg2 ;\
214ldxa [%g0]0x45, tempreg1 ;\
215or tempreg1, tempreg2, tempreg1 ;\
216andn tempreg1, 8, tempreg1 ;\
217stxa tempreg1, [%g0]0x45 ;\
218membar #Sync ;\
219/*}}} */
220/*{{{ dmmu on*/
221#define dmmu_on(tempreg1, tempreg2) \
222set 3, tempreg2 ;\
223sllx tempreg2, 48, tempreg2 ;\
224ldxa [%g0]0x45, tempreg1 ;\
225andn tempreg1, tempreg2, tempreg1 ;\
226or tempreg1, 8, tempreg1 ;\
227stxa tempreg1, [%g0]0x45 ;\
228membar #Sync ;\
229/*}}} */
230
231setx DUMP_BASE_ADDR, %g3, %g1
232 ldxa [%g0]ASI_INTR_ID, %g3
233and %g3, 0x3f, %g3
234sllx %g3, 16 , %g3
235add %g1, %g3, %g3
236add %g3, 0x800, %g2
237!xxx fprs should be part of checkpoint
238wr %g0, 7, %fprs
239!wr %g0, 0, %fprs
240/*{{{ dump sparc registers*/
241mov %g3, %g1
242mov %g2, %g5
243!get gl correct here, and copy %g5 into correct gl level
244ldx [%g5+8], %g3
245mov %g5, %l5
246wrpr %g3, %gl
247mov %l5, %g5
248
249
250#include "dump_regs.h"
251
252mov %g5, %g2
253mov %g1, %g3
254
255! add %g2, 0x40, %g2
256! andn %g2, 0x3f, %g2
257
258/*}}} */
259add %g2, 0x3f, %g2
260andn %g2, 0x3f, %g2
261/*{{{ load scratchpad*/
262mov 0, %g5
2631:
264ldx [%g2], %g1
265stxa %g1, [%g5]0x4f
266add %g5, 8, %g5
267subcc %g5, 0x40, %g0
268bne 1b
269add %g2, 0x8, %g2
270
271/*}}} */
272/*{{{ load interrupt*/
273mov 0, %g5
274mov 0x3c0, %g6
2751:
276ldx [%g2+%g5], %g1
277stxa %g1, [%g6]0x25
278add %g5, 8, %g5
279subcc %g5, 0x40, %g0
280bne 1b
281add %g6, 8, %g6
282add %g2, 0x40, %g2
283
284!interrupt pending
285ldx [%g2], %g1
286add %g2, 8, %g2
287
288!mondo data
289ldx [%g2], %g1
290add %g2, 8, %g2
291
292!mondo data
293ldx [%g2], %g1
294add %g2, 8, %g2
295
296!mondo busy
297ldx [%g2], %g1
298add %g2, 8, %g2
299
300/*}}} */
301add %g2, 0x3f, %g2
302andn %g2, 0x3f, %g2
303
304 ldxa [%g0]ASI_INTR_ID, %g1
305andcc %g1, 0x7, %g0
306bne not_thr_0_of_core
307nop
308mov 0x80, %g5
309stxa %g0, [%g5]0x5f
310!blow away TLB contents in case they upset new stuff
311stxa %g0, [%g5]0x57
312#if 0
313/*{{{ load itlb*/
314setx 0x00ffffffffffe000, %g1, %g7
315
316mov 0, %g5
3171:
318mov 0x30, %g6
319add %g2, 0x200, %g4
320ldx [%g4+%g5], %g1
321stxa %g1, [%g6]0x50
322
323ldx [%g2+%g5], %g6
324srlx %g6, 63, %g4
325!don't write entry into TLB if not valid (might evict an earlier valid entry with same VA/ctx)
326brz %g4, 3f
327xor %g1, %g6, %g1
328andcc %g1, %g7, %g0
329bne 2f
330nop
331or %g5, 0x200, %g5
3322:
333stxa %g6, [%g5]0x55
3343:
335andcc %g5, 0x1ff, %g5
336add %g5, 8, %g5
337subcc %g5, 0x200, %g0
338bne 1b
339nop
340/*}}} */
341!add %g2, 0x400, %g2
342/*{{{ load itlb again - only entries with used bit*/
343setx 0x00ffffffffffe000, %g1, %g7
344
345mov 0, %g5
3461:
347mov 0x30, %g6
348add %g2, 0x200, %g4
349ldx [%g4+%g5], %g1
350stxa %g1, [%g6]0x50
351
352ldx [%g2+%g5], %g6
353srlx %g6, 63, %g4
354!don't write entry into TLB if not valid (might evict an earlier valid entry with same VA/ctx)
355brz %g4, 3f
356xor %g1, %g6, %g1
357andcc %g1, %g7, %g0
358bne 2f
359nop
360or %g5, 0x200, %g5
3612:
362!don't write entry a second time if we don't want to set used bit
363mov 1, %g1
364sllx %g1, 47, %g1
365andcc %g1, %g6, %g1
366brz %g1, 3f
367nop
368stxa %g6, [%g5]0x55
3693:
370andcc %g5, 0x1ff, %g5
371add %g5, 8, %g5
372subcc %g5, 0x200, %g0
373bne 1b
374nop
375/*}}} */
376add %g2, 0x400, %g2
377/*{{{ load dtlb*/
378setx 0x00ffffffffffe000, %g1, %g7
379mov 0, %g5
3801:
381mov 0x30, %g6
382add %g2, 0x200, %g4
383ldx [%g4+%g5], %g1
384stxa %g1, [%g6]0x58
385ldx [%g2+%g5], %g6
386srlx %g6, 63, %g4
387!don't write entry into TLB if not valid (might evict an earlier valid entry with same VA/ctx)
388brz %g4, 3f
389xor %g1, %g6, %g1
390andcc %g1, %g7, %g0
391bne 2f
392nop
393or %g5, 0x200, %g5
3942:
395stxa %g6, [%g5]0x5d
3963:
397andcc %g5, 0x1ff, %g5
398add %g5, 8, %g5
399subcc %g5, 0x200, %g0
400bne 1b
401nop
402
403
404
405/*}}} */
406!add %g2, 0x400, %g2
407/*{{{ load dtlb again - only entries with used bit*/
408setx 0x00ffffffffffe000, %g1, %g7
409mov 0, %g5
4101:
411mov 0x30, %g6
412add %g2, 0x200, %g4
413ldx [%g4+%g5], %g1
414stxa %g1, [%g6]0x58
415ldx [%g2+%g5], %g6
416srlx %g6, 63, %g4
417!don't write entry into TLB if not valid (might evict an earlier valid entry with same VA/ctx)
418brz %g4, 3f
419xor %g1, %g6, %g1
420andcc %g1, %g7, %g0
421bne 2f
422nop
423or %g5, 0x200, %g5
4242:
425
426!don't write entry a second time if we don't want to set used bit
427mov 1, %g1
428sllx %g1, 47, %g1
429andcc %g1, %g6, %g1
430brz %g1, 3f
431nop
432stxa %g6, [%g5]0x5d
4333:
434andcc %g5, 0x1ff, %g5
435add %g5, 8, %g5
436subcc %g5, 0x200, %g0
437bne 1b
438nop
439
440
441
442/*}}} */
443add %g2, 0x400, %g2
444#endif
445not_thr_0_of_core:
446
447#if 0
448setx DUMP_BASE_ADDR, %g3, %g1
449/*{{{ align threads*/
450!sync up all the stick regs
451!setx 0x80000010, %g1, %g3
452!ldx [%g3], %g6
453
454setx DUMP_BASE_ADDR, %g3, %g1
455 ldxa [%g0]ASI_INTR_ID, %g3
456and %g3, 0x3f, %g3
457
458
459/*{{{ spin waiting for all threads to arrive...*/
460#ifndef THREAD_COUNT
461#define NUM_THREADS 8
462#else
463#define NUM_THREADS THREAD_COUNT
464#endif
465mov 1, %g2
466stb %g2, [%g1+%g3]
467
468!wait for all threads to set sync byte
4692:
470mov 0, %g2
471mov 0, %g5
4721:
473ldub [%g1+%g2], %g4
474add %g4, %g5, %g5
475subcc %g2, (NUM_THREADS-1), %g0
476bne 1b
477add %g2, 1, %g2
478subcc %g5, NUM_THREADS, %g0
479bne 2b
480nop
481
482
483add %g1, 0x40, %g1
484mov 1, %g2
485stb %g2, [%g1+%g3]
486
487!wait for all threads to set sync byte
4882:
489mov 0, %g2
490mov 0, %g5
4911:
492ldub [%g1+%g2], %g4
493add %g4, %g5, %g5
494subcc %g2, (NUM_THREADS-1), %g0
495bne 1b
496add %g2, 1, %g2
497subcc %g5, NUM_THREADS, %g0
498bne 2b
499nop
500
501sub %g1, 0x40, %g1
502
503stb %g0, [%g1+%g3]
504!wait for all threads to clear sync byte
5052:
506mov 0, %g2
507mov 0, %g5
5081:
509ldub [%g1+%g2], %g4
510add %g4, %g5, %g5
511subcc %g2, (NUM_THREADS-1), %g0
512bne 1b
513add %g2, 1, %g2
514subcc %g5, 0, %g0
515bne 2b
516nop
517
518add %g1, 0x40, %g1
519stb %g0, [%g1+%g3]
520!wait for all threads to clear sync byte
5212:
522mov 0, %g2
523mov 0, %g5
5241:
525ldub [%g1+%g2], %g4
526add %g4, %g5, %g5
527subcc %g2, (NUM_THREADS-1), %g0
528bne 1b
529add %g2, 1, %g2
530subcc %g5, 0, %g0
531bne 2b
532nop
533sub %g1, 0x40, %g1
534/*}}} */
535! addcc %g3, %g0, %g0
536! bne dont_dump
537sllx %g3, 16 , %g3
538or %g1, %g3, %g3
539
540!add %g3, 0x80, %g3
541!mov %fprs, %g1
542!mov 4, %fprs
543!stx %g1 ,[%g3]
544!add %g3, 0x800, %g2
545
546!sync up all the stick regs
547!setx 0x80000010, %g1, %g3
548!addcc %g6, %g0, %g0
549!bne 1f
550!nop
551!add %g6, 1, %g1
552! wr %g0, %asr24
553!stx %g1, [%g3]
554!1:
555/*}}} */
556!poke interrupt units to deliver anything pending
557 ldxa [%g0]ASI_INTR_ID, %g3
558andcc %g3, 0x3f, %g0
559bne no_poke
560/*{{{ poke interrupts*/
561 !cpuids: 0x2 0x5 0x8 0x9 0xa 0xb 0xd 0xf 0x11 0x14 0x15 0x18 0x1a 0x1b 0x1d 0x1e 0x1f
562 mov 0x03f, %g1
563 stxa %g1, [%g0]0x73
564#if 0
565 add %g1, 0x100, %g1
566 add %g1, 0x100, %g1
567 add %g1, 0x100, %g1
568 stxa %g1, [%g0]0x73 !5
569 add %g1, 0x100, %g1
570 add %g1, 0x100, %g1
571 add %g1, 0x100, %g1
572 stxa %g1, [%g0]0x73 !8
573 add %g1, 0x100, %g1
574 stxa %g1, [%g0]0x73
575 add %g1, 0x100, %g1
576 stxa %g1, [%g0]0x73
577 add %g1, 0x100, %g1
578 stxa %g1, [%g0]0x73
579 add %g1, 0x100, %g1
580 add %g1, 0x100, %g1
581 stxa %g1, [%g0]0x73 !d
582 add %g1, 0x100, %g1
583 add %g1, 0x100, %g1
584 stxa %g1, [%g0]0x73 !f
585 add %g1, 0x100, %g1
586 add %g1, 0x100, %g1
587 stxa %g1, [%g0]0x73 !11
588 !cpuids: 0x2 0x5 0x8 0x9 0xa 0xb 0xd 0xf 0x11 0x14 0x15 0x18 0x1a 0x1b 0x1d 0x1e 0x1f
589 add %g1, 0x100, %g1
590 add %g1, 0x100, %g1
591 add %g1, 0x100, %g1
592 stxa %g1, [%g0]0x73 !14
593 add %g1, 0x100, %g1
594 stxa %g1, [%g0]0x73 !15
595 add %g1, 0x100, %g1
596 add %g1, 0x100, %g1
597 add %g1, 0x100, %g1
598 stxa %g1, [%g0]0x73 !18
599 add %g1, 0x100, %g1
600 add %g1, 0x100, %g1
601 stxa %g1, [%g0]0x73 !1a
602 add %g1, 0x100, %g1
603 stxa %g1, [%g0]0x73 !1b
604 add %g1, 0x100, %g1
605 add %g1, 0x100, %g1
606 stxa %g1, [%g0]0x73 !1d
607 add %g1, 0x100, %g1
608 stxa %g1, [%g0]0x73 !1e
609 add %g1, 0x100, %g1
610 stxa %g1, [%g0]0x73 !1f
611#endif
612/*}}} */
613/*{{{ old*/
614 mov 0x43f, %g1
615 stxa %g1, [%g0]0x73
616 add %g1, 0x100, %g1
617 stxa %g1, [%g0]0x73
618 add %g1, 0x100, %g1
619 stxa %g1, [%g0]0x73
620 add %g1, 0x100, %g1
621 stxa %g1, [%g0]0x73
622/*}}} */
623#endif
624no_poke:
625#if 1
626#else
627mov %asr24, %g2
628mov 1, %g1
629sllx %g1, 24, %g1
630add %g2, %g1, %g2
631#endif
632retl
633nop
634#if 0
635sub %g0, 1, %g2
636!wrhpr %g2, %g0, %asr31
637.word 0xbf988000
638!wrhpr %g0, 0, %hintp
639.word 0x87982000
640retry
641#endif
Full OpenSPARC design & verification tarball including full HDL.