projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: exu_ecc_inj_error_n2.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define H_HT0_Internal_Processor_Error_0x29 My_Internal_Processor_Error_Trap | |
| 39 | ||
| 40 | #define MAIN_PAGE_HV_ALSO | |
| 41 | #define ASI_DMMU 0x58 | |
| 42 | #define ASI_SEI 0x43 | |
| 43 | #define ASI_SES 0x4C | |
| 44 | ||
| 45 | #include "hboot.s" | |
| 46 | ||
| 47 | .text | |
| 48 | .global main | |
| 49 | .global My_Internal_Processor_Error_Trap | |
| 50 | ||
| 51 | ||
| 52 | .align 64 | |
| 53 | ||
| 54 | main: | |
| 55 | ||
| 56 | ta T_CHANGE_HPRIV | |
| 57 | ||
| 58 | ! Sparc Error Injection Register should power up 0 | |
| 59 | ldxa [%g0] ASI_SEI, %l1 | |
| 60 | cmp %l1, 0 | |
| 61 | bne test_fail | |
| 62 | nop | |
| 63 | ||
| 64 | ! New Stuff | |
| 65 | ||
| 66 | setx 0x0f0d0f0f, %i0, %i3 | |
| 67 | setx 0x0f0d0f0f, %i0, %i4 | |
| 68 | ||
| 69 | ||
| 70 | !enable cerer.bit_52 | |
| 71 | ||
| 72 | setx 0x10, %g0, %g1 ! VA for pscce 12.7.1 | |
| 73 | setx 0x18, %g0, %g2 ! VA for ceter 12.7.2 | |
| 74 | ||
| 75 | set_pscce_bit52: | |
| 76 | setx 0x0010000000000000, %l0, %l2 | |
| 77 | stxa %l2, [%g0+%g1] ASI_SES | |
| 78 | ldxa [%g0+%g1] ASI_SES, %l6 | |
| 79 | cmp %l2, %l6 | |
| 80 | bne test_fail | |
| 81 | ||
| 82 | ||
| 83 | set_ceter_bit62: | |
| 84 | setx 0x4000000000000000, %l0, %l3 | |
| 85 | stxa %l3, [%g0+%g2] ASI_SES !enable ceter.pscce 12.7.2 | |
| 86 | ldxa [%g0+%g2] ASI_SES, %l7 | |
| 87 | cmp %l3, %l7 | |
| 88 | bne test_fail | |
| 89 | ||
| 90 | enable_err_inj_reg: | |
| 91 | setx 0x0000000082000001, %i0, %l4 ! Enable error injection | |
| 92 | setx 0x0000000000000000, %i0, %l5 ! Enable error injection | |
| 93 | stxa %l4, [%g0] ASI_SEI !write_asi_err_inject_reg pg:12.7.9 | |
| 94 | !ldxa [%g0] ASI_SEI, %l6 | |
| 95 | !cmp %l4, %l6 | |
| 96 | !bne test_fail | |
| 97 | ||
| 98 | execute_instr_with_bad_ecc: | |
| 99 | add %i3, %i4, %i4 ! <= shd cause an error to be injected | |
| 100 | add %i3, %i3, %i5 ! <= shd cause an error to be injected | |
| 101 | ||
| 102 | stxa %l5, [%g0] ASI_SEI !turn off error inject | |
| 103 | ||
| 104 | add %i0, %i0, %i0 | |
| 105 | add %i0, %i0, %i0 | |
| 106 | add %i0, %i0, %i0 | |
| 107 | add %i0, %i0, %i0 | |
| 108 | add %i0, %i0, %i0 | |
| 109 | add %i0, %i0, %i0 | |
| 110 | add %i5, %i2, %i7 ! <= err shd be detected | |
| 111 | add %i0, %i0, %i0 | |
| 112 | add %i0, %i0, %i0 | |
| 113 | add %i0, %i0, %i0 | |
| 114 | add %i4, %i0, %i4 | |
| 115 | add %i0, %i0, %i0 | |
| 116 | add %i0, %i0, %i0 | |
| 117 | add %i0, %i0, %i0 | |
| 118 | ||
| 119 | ||
| 120 | ba test_fail | |
| 121 | nop | |
| 122 | ||
| 123 | ||
| 124 | My_Internal_Processor_Error_Trap: | |
| 125 | ||
| 126 | setx 0x10, %g0, %g1 ! VA for pscce 12.7.1 | |
| 127 | setx 0x18, %g0, %g2 ! VA for ceter 12.7.2 | |
| 128 | setx 0x20, %g0, %g3 ! VA for ceter 12.7.4.2 | |
| 129 | ||
| 130 | !Check status registers | |
| 131 | ldxa [%g0+%g2] ASI_DMMU, %l6 | |
| 132 | ldxa [%g0+%g3] ASI_DMMU, %l7 | |
| 133 | ||
| 134 | setx 0x0000000000000002, %o0, %o6 | |
| 135 | cmp %o6, %l6 | |
| 136 | bne test_fail | |
| 137 | setx 0x000000000000409d, %o0, %o7 | |
| 138 | cmp %o7, %l7 | |
| 139 | bne test_fail | |
| 140 | ||
| 141 | ba test_pass | |
| 142 | nop | |
| 143 | ||
| 144 | /******************************************************* | |
| 145 | * Exit code | |
| 146 | *******************************************************/ | |
| 147 | ||
| 148 | test_pass: | |
| 149 | ||
| 150 | ||
| 151 | ||
| 152 | ta T_GOOD_TRAP | |
| 153 | ||
| 154 | test_fail: | |
| 155 | ta T_BAD_TRAP | |
| 156 | ||
| 157 |