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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / exu / exu_muldiv_n2.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: exu_muldiv_n2.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define NUM_MUL_CASES 6
39#define NUM_DIV_CASES 4
40#define NUM_IMMED_CASES 5
41
42! for divide by zero cases
43#define H_T0_Division_By_Zero
44#define My_T0_Division_By_Zero \
45rdpr %tstate, %i1; \
46rdpr %tt, %i1; \
47rdpr %tpc, %i0; \
48rdpr %tnpc, %i1; \
49done; \
50nop;
51
52/*******************************************************/
53#include "hboot.s"
54
55.global main
56main:
57th_fork(th_main,%l0) ! start up to four threads.
58 ! All threads do the same thing, but with different data patterns.
59 ! No need to run more than one core.
60th_main_0:
61 setx mul_data_t0,%g7,%g1
62 ba all_threads1
63 nop
64
65th_main_1:
66 setx mul_data_t1,%g7,%g1
67 ba all_threads1
68 nop
69
70th_main_2:
71 setx mul_data_t2,%g7,%g1
72 ba all_threads1
73 nop
74
75th_main_3:
76 setx mul_data_t3,%g7,%g1
77 ba all_threads1
78 nop
79
80all_threads1:
81 !*************************************************************
82 ! Operand2 as a register: MULX, UMUL, SMUL, UMULcc, SMULcc
83 !*************************************************************
84 add %g0,NUM_MUL_CASES,%g2
85 mova %icc,%g1,%g3 ! keep the multiply operand address handy
86
87mul_loop1:
88 ldx [%g1],%l1
89 ldx [%g1+8],%l2
90 wr %g0,%g0,%ccr ! ccr clear
91
92 mulx %l1,%l2,%l4
93 umul %l1,%l2,%l5
94 rd %y,%i1 ! be sure SAS looks at Y-reg
95 smul %l1,%l2,%l6
96 rd %y,%i1
97
98 wr %g0,%g0,%ccr ! clear ccr
99 umulcc %l1,%l2,%l7
100 rd %y,%i1
101 wr %g0,%g0,%ccr
102 smulcc %l1,%l2,%l6
103 rd %y,%i1
104
105 wr %g0,0xff,%ccr ! set ccr. Should not matter.
106 umulcc %l1,%l2,%l7
107 rd %y,%i1
108 wr %g0,0xff,%ccr
109 smulcc %l1,%l2,%l6
110 rd %y,%i1
111
112 sub %g2,0x1,%g2
113 brnz,pt %g2,mul_loop1
114 add %g1,0x10,%g1 ! move operand pointer
115
116 !**********************************
117 ! Operand2 as a register: MULScc
118 !**********************************
119#ifndef MULSCC_BUGS
120 mova %icc,%g3,%g1 ! same ops as mul_loop1
121 add %g0,NUM_MUL_CASES,%g2
122mulscc_1:
123 wr %g0,%g0,%ccr ! ccr clear
124 ldx [%g1],%l1
125 ldx [%g1+8],%l2
126 wr %l1,0,%y ! lower bits of multiplier into Y-reg
127 rd %y,%l0 ! for sas debug
128 srl %l1,0,%l1 ! clear rs1 upper
129 srl %l2,0,%l2 ! clear rs2 upper
130 mulx %l1,%l2,%l4 ! save for later compare
131 add %g0,0,%l1 ! clear rs1 (product upper) completely
132
133 add %g0,32,%l3 ! bit position counter
134mulscc_2:
135 sub %l3,1,%l3
136 mulscc %l1,%l2,%l1
137 brgez,pt %l3,mulscc_2
138 nop
139
140 sllx %l1,33,%l1 ! product upper
141 rd %y,%l3 ! product lower
142 or %l1,%l3,%l3 ! full product should be equal to mulx
143 subcc %l3,%l4,%l5
144 tnz T_BAD_TRAP
145 nop
146
147 sub %g2,0x1,%g2
148 brnz,pt %g2,mulscc_1
149 add %g1,0x10,%g1 ! move operand pointer
150#endif
151
152 !****************************************
153 ! Operand2 as a register: SDIVX, UDIVX
154 !****************************************
155 rdth_id ! get thid in %o1
156 cmp %o1,0
157 be th_divx_0
158 cmp %o1,1
159 be th_divx_1
160 cmp %o1,2
161 be th_divx_2
162 nop
163 ba th_divx_3 ! if there are more than 4 threads...
164 nop
165
166th_divx_0:
167 setx divx_data_t0,%g7,%g1
168 ba all_threads2
169 nop
170
171th_divx_1:
172 setx divx_data_t1,%g7,%g1
173 ba all_threads2
174 nop
175
176th_divx_2:
177 setx divx_data_t2,%g7,%g1
178 ba all_threads2
179 nop
180
181th_divx_3:
182 setx divx_data_t3,%g7,%g1
183 ba all_threads2
184 nop
185
186all_threads2:
187 add %g0,NUM_DIV_CASES,%g2
188
189divx_loop1:
190 ldx [%g1],%l1
191 ldx [%g1+8],%l2
192 wr %g0,%g0,%ccr ! ccr clear
193
194 sdivx %l1,%l2,%l3
195 udivx %l1,%l2,%l4
196 sdivx %l2,%l1,%l5 ! use each operand as divisor and dividend
197 udivx %l2,%l1,%l6
198
199 sub %g2,0x1,%g2
200 brnz,pt %g2,divx_loop1
201 add %g1,0x10,%g1 ! move operand pointer
202
203 !*******************************************************
204 ! Operand2 as a register: SDIV, SDIVcc, UDIV, UDIVcc
205 !*******************************************************
206 rdth_id ! get thid in %o1
207 cmp %o1,3
208 be th_div_3
209 cmp %o1,2
210 be th_div_2
211 cmp %o1,1
212 be th_div_1
213 nop
214 ! if there are more than 4 threads, run with same data as t0
215th_div_0:
216 setx div_data_t0,%g7,%g1
217 ba all_threads3
218 nop
219
220th_div_1:
221 setx div_data_t1,%g7,%g1
222 ba all_threads3
223 nop
224
225th_div_2:
226 setx div_data_t2,%g7,%g1
227 ba all_threads3
228 nop
229
230th_div_3:
231 setx div_data_t3,%g7,%g1
232 ba all_threads3
233 nop
234
235all_threads3:
236 add %g0,NUM_DIV_CASES,%g2
237 sub %g0,1,%g3 ! build masks for part 2 of the test
238 srl %g3,0,%g3 ! g3 is foxes in lower half
239 sllx %g3,32,%g4 ! g4 is foxes in upper half
240
241div_loop1:
242 ldx [%g1],%l1
243 ldx [%g1+8],%l2
244 wr %g0,%g0,%ccr ! ccr clear
245
246 ! pick up Y from top half of %l1. Invert %l1<63:32>.
247 mov %l1,%l0
248 srlx %l0,32,%l0
249 wr %l0,%g0,%y
250 xor %l1,%g4,%l1 ! invert upper half of %l1
251
252 sdiv %l1,%l2,%l3
253 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
254 udiv %l1,%l2,%l4
255 wr %l0,%g0,%y
256 sdivcc %l1,%l2,%l3
257 wr %g0,%g0,%ccr ! ccr clear
258 wr %l0,%g0,%y
259 udivcc %l1,%l2,%l3
260
261 ! pick up Y from top half of %l2. Clear %l2<63:32>.
262 mov %l2,%l0
263 srlx %l0,32,%l0
264 wr %l0,%g0,%y
265 and %l2,%g3,%l2 ! clear upper half of %l2
266
267 sdiv %l2,%l1,%l5
268 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
269 udiv %l2,%l1,%l6
270 wr %l0,%g0,%y
271 wr %g0,0xff,%ccr ! ccr set
272 sdivcc %l1,%l2,%l3
273 wr %g0,0xff,%ccr ! ccr set
274 wr %l0,%g0,%y
275 udivcc %l1,%l2,%l3
276
277 sub %g2,0x1,%g2
278 brnz,pt %g2,div_loop1
279 add %g1,0x10,%g1 ! move operand pointer
280
281 !**************************
282 ! Operand2 as immediate
283 !**************************
284
285 setx immed_data,%g7,%g1 ! run all threads with same immediate cases
286 add %g0,NUM_IMMED_CASES,%g2
287immed_loop:
288 ldx [%g1],%l1
289 wr %g0,%g0,%ccr ! ccr clear
290
291 ! immed13 = 0
292 mulx %l1,0x0000,%l4
293 umul %l1,0x0000,%l5
294 smul %l1,0x0000,%l6
295 umulcc %l1,0x0000,%l7
296 smulcc %l1,0x0000,%l6
297 wr %l1,0,%y
298#ifndef MULSCC_BUGS
299 mulscc %l1,0x0000,%l5
300#endif
301 sdivx %l1,0x0000,%l3
302 udivx %l1,0x0000,%l4
303 mov %l1,%l0
304 srlx %l0,32,%l0 ! use %l0 to hold %y value
305 wr %l0,%g0,%y
306 xor %l1,%g4,%l1 ! invert upper half of %l1
307
308 sdiv %l1,0x0000,%l3
309 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
310 udiv %l1,0x0000,%l4
311 wr %l0,%g0,%y
312 sdivcc %l1,0x0000,%l3
313 wr %l0,%g0,%y
314 udivcc %l1,0x0000,%l3
315
316 ! immed13 = 1
317 mulx %l1,0x0001,%l4
318 umul %l1,0x0001,%l5
319 smul %l1,0x0001,%l6
320 umulcc %l1,0x0001,%l7
321 smulcc %l1,0x0001,%l6
322 wr %l1,0,%y
323#ifndef MULSCC_BUGS
324 mulscc %l1,0x0001,%l5
325#endif
326 sdivx %l1,0x0001,%l3
327 udivx %l1,0x0001,%l4
328 mov %l1,%l0
329 srlx %l0,32,%l0 ! use %l0 to hold %y value
330 wr %l0,%g0,%y
331 xor %l1,%g4,%l1 ! invert upper half of %l1
332
333 sdiv %l1,0x0001,%l3
334 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
335 udiv %l1,0x0001,%l4
336 wr %l0,%g0,%y
337 sdivcc %l1,0x0001,%l3
338 wr %l0,%g0,%y
339 udivcc %l1,0x0001,%l3
340
341 ! immed13 = -1
342 mulx %l1,0x1fff,%l4
343 umul %l1,0x1fff,%l5
344 smul %l1,0x1fff,%l6
345 umulcc %l1,0x1fff,%l7
346 smulcc %l1,0x1fff,%l6
347 wr %l1,0,%y
348#ifndef MULSCC_BUGS
349 mulscc %l1,0x1fff,%l5
350#endif
351 sdivx %l1,0x1fff,%l3
352 udivx %l1,0x1fff,%l4
353 mov %l1,%l0
354 srlx %l0,32,%l0 ! use %l0 to hold %y value
355 wr %l0,%g0,%y
356 xor %l1,%g4,%l1 ! invert upper half of %l1
357
358 sdiv %l1,0x1fff,%l3
359 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
360 udiv %l1,0x1fff,%l4
361 wr %l0,%g0,%y
362 sdivcc %l1,0x1fff,%l3
363 wr %l0,%g0,%y
364 udivcc %l1,0x1fff,%l3
365
366 ! immed13 = 0x0fff
367 mulx %l1,0x0fff,%l4
368 umul %l1,0x0fff,%l5
369 smul %l1,0x0fff,%l6
370 umulcc %l1,0x0fff,%l7
371 smulcc %l1,0x0fff,%l6
372 wr %l1,0,%y
373#ifndef MULSCC_BUGS
374 mulscc %l1,0x0fff,%l5
375#endif
376 sdivx %l1,0x0fff,%l3
377 udivx %l1,0x0fff,%l4
378 mov %l1,%l0
379 srlx %l0,32,%l0 ! use %l0 to hold %y value
380 wr %l0,%g0,%y
381 xor %l1,%g4,%l1 ! invert upper half of %l1
382
383 sdiv %l1,0x0fff,%l3
384 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
385 udiv %l1,0x0fff,%l4
386 wr %l0,%g0,%y
387 sdivcc %l1,0x0fff,%l3
388 wr %l0,%g0,%y
389 udivcc %l1,0x0fff,%l3
390
391 ! immed13 = 0x1000
392 mulx %l1,0x1000,%l4
393 umul %l1,0x1000,%l5
394 smul %l1,0x1000,%l6
395 umulcc %l1,0x1000,%l7
396 smulcc %l1,0x1000,%l6
397 wr %l1,0,%y
398#ifndef MULSCC_BUGS
399 mulscc %l1,0x1000,%l5
400#endif
401 sdivx %l1,0x1000,%l3
402 udivx %l1,0x1000,%l4
403 mov %l1,%l0
404 srlx %l0,32,%l0 ! use %l0 to hold %y value
405 wr %l0,%g0,%y
406 xor %l1,%g4,%l1 ! invert upper half of %l1
407
408 sdiv %l1,0x1000,%l3
409 wr %l0,%g0,%y ! div ops are allowed to trash Y, so reload
410 udiv %l1,0x1000,%l4
411 wr %l0,%g0,%y
412 sdivcc %l1,0x1000,%l3
413 wr %l0,%g0,%y
414 udivcc %l1,0x1000,%l3
415
416 sub %g2,0x1,%g2
417 brnz,pt %g2,immed_loop
418 add %g1,8,%g1 ! move operand pointer
419
420 !***************************************************************
421 ! MULScc cases for icc.n, icc.v and Y<0> to hit all combinations
422 !***************************************************************
423#ifndef MULSCC_BUGS
424
425 add %g0,0xfff,%l1
426 ! icc.nv=00, Y<0>=0
427 wr %g0,0,%y
428 wr %g0,0x00,%ccr
429 mulscc %l1,0x1fff,%l2
430 ! icc.nv=01, Y<0>=0
431 wr %g0,0,%y
432 wr %g0,0x02,%ccr
433 mulscc %l1,0x1fff,%l2
434 ! icc.nv=10, Y<0>=0
435 wr %g0,0,%y
436 wr %g0,0x08,%ccr
437 mulscc %l1,0x1fff,%l2
438 ! icc.nv=11, Y<0>=0
439 wr %g0,0,%y
440 wr %g0,0x0a,%ccr
441 mulscc %l1,0x1fff,%l2
442
443 ! icc.nv=00, Y<0>=1
444 wr %g0,1,%y
445 wr %g0,0x00,%ccr
446 mulscc %l1,0x1fff,%l2
447 ! icc.nv=01, Y<0>=1
448 wr %g0,1,%y
449 wr %g0,0x02,%ccr
450 mulscc %l1,0x1fff,%l2
451 ! icc.nv=10, Y<0>=1
452 wr %g0,1,%y
453 wr %g0,0x08,%ccr
454 mulscc %l1,0x1fff,%l2
455 ! icc.nv=11, Y<0>=1
456 wr %g0,1,%y
457 wr %g0,0x0a,%ccr
458 mulscc %l1,0x1fff,%l2
459#endif
460/********************************************************************************
461* The following test cases check implementation dependent cases.
462* 1. long ops in the delay slot of a branch, with and without nullification
463* 2. uninitialized cache lines and the divide by zero detect logic
464* 3. contention for register write ports
465**********************************************************************************/
466
467 !*******************************************************************
468 ! Mul/Div operations in delay slots of a branch. Data is unimportant
469 !*******************************************************************
470 sub %g0,1,%l1
471 wr %l1,0,%y
472 ! branch taken, delay instr not annulled
473 add %g0,%g0,%l2
474 brz,a,pt %l2,br_pt_1
475 mulx %l1,0x0101,%l4
476 nop
477 nop
478br_pt_1:
479 brz,a,pt %l2,br_pt_2
480 umul %l1,0x0101,%l5
481 nop
482 nop
483br_pt_2:
484 brz,a,pt %l2,br_pt_3
485 smul %l1,0x0101,%l6
486 nop
487 nop
488br_pt_3:
489 brz,a,pt %l2,br_pt_4
490 umulcc %l1,0x0101,%l7
491 nop
492 nop
493br_pt_4:
494 brz,a,pt %l2,br_pt_5
495 smulcc %l1,0x0101,%l6
496 nop
497 nop
498br_pt_5:
499#ifndef MULSCC_BUGS
500 brz,a,pt %l2,br_pt_6
501 mulscc %l1,0x0101,%l5
502 nop
503 nop
504#endif
505br_pt_6:
506 brz,a,pt %l2,br_pt_7
507 sdivx %l1,0x0101,%l3
508 nop
509 nop
510br_pt_7:
511 brz,a,pt %l2,br_pt_8
512 udivx %l1,0x0101,%l4
513 nop
514 nop
515br_pt_8:
516 brz,a,pt %l2,br_pt_9
517 sdiv %l1,0x0101,%l5
518 nop
519 nop
520br_pt_9:
521 brz,a,pt %l2,br_pt_10
522 udiv %l1,0x0101,%l7
523 nop
524 nop
525br_pt_10:
526 brz,a,pt %l2,br_pt_11
527 sdivcc %l1,0x0101,%l6
528 nop
529 nop
530br_pt_11:
531 brz,a,pt %l2,br_pt_12
532 udivcc %l1,0x0101,%l3
533 nop
534 nop
535br_pt_12:
536
537 ! branch taken, delay instr annulled
538 add %g0,1,%l2
539 brz,a,pt %l2,br_pta_1
540 mulx %l1,0x0101,%l4
541 nop
542 nop
543br_pta_1:
544 brz,a,pt %l2,br_pta_2
545 umul %l1,0x0101,%l5
546 nop
547 nop
548br_pta_2:
549 brz,a,pt %l2,br_pta_3
550 smul %l1,0x0101,%l6
551 nop
552 nop
553br_pta_3:
554 brz,a,pt %l2,br_pta_4
555 umulcc %l1,0x0101,%l7
556 nop
557 nop
558br_pta_4:
559 brz,a,pt %l2,br_pta_5
560 smulcc %l1,0x0101,%l6
561 nop
562 nop
563br_pta_5:
564#ifndef MULSCC_BUGS
565 brz,a,pt %l2,br_pta_6
566 mulscc %l1,0x0101,%l5
567 nop
568 nop
569#endif
570br_pta_6:
571 brz,a,pt %l2,br_pta_7
572 sdivx %l1,0x0101,%l3
573 nop
574 nop
575br_pta_7:
576 brz,a,pt %l2,br_pta_8
577 udivx %l1,0x0101,%l4
578 nop
579 nop
580br_pta_8:
581 brz,a,pt %l2,br_pta_9
582 sdiv %l1,0x0101,%l5
583 nop
584 nop
585br_pta_9:
586 brz,a,pt %l2,br_pta_10
587 udiv %l1,0x0101,%l7
588 nop
589 nop
590br_pta_10:
591 brz,a,pt %l2,br_pta_11
592 sdivcc %l1,0x0101,%l6
593 nop
594 nop
595br_pta_11:
596 brz,a,pt %l2,br_pta_12
597 udivcc %l1,0x0101,%l3
598 nop
599 nop
600br_pta_12:
601
602
603 ! branch taken, delay instr not annulled
604 add %g0,%g0,%l2
605 brz,a,pn %l2,br_pn_1
606 mulx %l1,0x0101,%l4
607 nop
608 nop
609br_pn_1:
610 brz,a,pn %l2,br_pn_2
611 umul %l1,0x0101,%l5
612 nop
613 nop
614br_pn_2:
615 brz,a,pn %l2,br_pn_3
616 smul %l1,0x0101,%l6
617 nop
618 nop
619br_pn_3:
620 brz,a,pn %l2,br_pn_4
621 umulcc %l1,0x0101,%l7
622 nop
623 nop
624br_pn_4:
625 brz,a,pn %l2,br_pn_5
626 smulcc %l1,0x0101,%l6
627 nop
628 nop
629br_pn_5:
630#ifndef MULSCC_BUGS
631 brz,a,pn %l2,br_pn_6
632 mulscc %l1,0x0101,%l5
633 nop
634 nop
635#endif
636br_pn_6:
637 brz,a,pn %l2,br_pn_7
638 sdivx %l1,0x0101,%l3
639 nop
640 nop
641br_pn_7:
642 brz,a,pn %l2,br_pn_8
643 udivx %l1,0x0101,%l4
644 nop
645 nop
646br_pn_8:
647 brz,a,pn %l2,br_pn_9
648 sdiv %l1,0x0101,%l5
649 nop
650 nop
651br_pn_9:
652 brz,a,pn %l2,br_pn_10
653 udiv %l1,0x0101,%l7
654 nop
655 nop
656br_pn_10:
657 brz,a,pn %l2,br_pn_11
658 sdivcc %l1,0x0101,%l6
659 nop
660 nop
661br_pn_11:
662 brz,a,pn %l2,br_pn_12
663 udivcc %l1,0x0101,%l3
664 nop
665 nop
666br_pn_12:
667
668 ! branch taken, delay instr annulled
669 add %g0,1,%l2
670 brz,a,pn %l2,br_pna_1
671 mulx %l1,0x0101,%l4
672 nop
673 nop
674br_pna_1:
675 brz,a,pn %l2,br_pna_2
676 umul %l1,0x0101,%l5
677 nop
678 nop
679br_pna_2:
680 brz,a,pn %l2,br_pna_3
681 smul %l1,0x0101,%l6
682 nop
683 nop
684br_pna_3:
685 brz,a,pn %l2,br_pna_4
686 umulcc %l1,0x0101,%l7
687 nop
688 nop
689br_pna_4:
690 brz,a,pn %l2,br_pna_5
691 smulcc %l1,0x0101,%l6
692 nop
693 nop
694br_pna_5:
695#ifndef MULSCC_BUGS
696 brz,a,pn %l2,br_pna_6
697 mulscc %l1,0x0101,%l5
698 nop
699 nop
700#endif
701br_pna_6:
702 brz,a,pn %l2,br_pna_7
703 sdivx %l1,0x0101,%l3
704 nop
705 nop
706br_pna_7:
707 brz,a,pn %l2,br_pna_8
708 udivx %l1,0x0101,%l4
709 nop
710 nop
711br_pna_8:
712 brz,a,pn %l2,br_pna_9
713 sdiv %l1,0x0101,%l5
714 nop
715 nop
716br_pna_9:
717 brz,a,pn %l2,br_pna_10
718 udiv %l1,0x0101,%l7
719 nop
720 nop
721br_pna_10:
722 brz,a,pn %l2,br_pna_11
723 sdivcc %l1,0x0101,%l6
724 nop
725 nop
726br_pna_11:
727 brz,a,pn %l2,br_pna_12
728 udivcc %l1,0x0101,%l3
729 nop
730 nop
731br_pna_12:
732
733
734 !***********************************************************************
735 ! Div rs2 used during a cache miss on a previously unused cache line.
736 ! X's in the divide-by-zero logic have caused problems in the past.
737 !***********************************************************************
738 add %g0,42,%l1
739 wr %l1,0,%y
740 ! *** UDIVX ***
741 setx udivx_miss1,%g7,%g1
742 ldx [%g1],%l2
743 udivx %l1,%l2,%l3
744
745 setx udivx_miss2,%g7,%g1
746 ldx [%g1],%l2
747 udivx %l1,%l2,%l4
748
749 setx udivx_miss3,%g7,%g1
750 ldx [%g1],%l2
751 nop ! change timing slightly
752 udivx %l1,%l2,%l4
753
754 setx udivx_miss4,%g7,%g1
755 ldx [%g1],%l2
756 udivx %l1,%l2,%l3 ! loaded value is zero
757
758
759 ! *** SDIVX ***
760 setx sdivx_miss1,%g7,%g1
761 ldx [%g1],%l2
762 sdivx %l1,%l2,%l1 ! rs1 same as rd
763
764 setx sdivx_miss2,%g7,%g1
765 ldx [%g1],%l2
766 sdivx %l1,%l2,%l2 ! rs2 same as rd
767
768 setx sdivx_miss3,%g7,%g1
769 ldx [%g1],%l2
770 nop ! change timing slightly
771 sdivx %l1,%l2,%l4
772
773 setx udivx_miss4,%g7,%g1
774 ldx [%g1],%l2
775 sdivx %l1,%l2,%l2 ! loaded value is zero
776
777
778 ! *** UDIV ***
779 setx udiv_miss1,%g7,%g1
780 ldx [%g1],%l2
781 udiv %l1,%l2,%l3
782
783 setx udiv_miss2,%g7,%g1
784 ldx [%g1],%l2
785 udiv %l1,%l2,%l4
786
787 setx udiv_miss3,%g7,%g1
788 ldx [%g1],%l2
789 nop ! change timing slightly
790 udiv %l1,%l2,%l2
791
792 setx udiv_miss4,%g7,%g1
793 ldx [%g1],%l2
794 udiv %l1,%l2,%l1 ! loaded value is zero
795
796
797 ! *** SDIVcc ***
798 setx sdivcc_miss1,%g7,%g1
799 ldx [%g1],%l2
800 sdivcc %l1,%l2,%l4
801
802 setx sdivcc_miss2,%g7,%g1
803 ldx [%g1],%l2
804 sdivcc %l1,%l2,%l3
805
806 setx sdivcc_miss3,%g7,%g1
807 ldx [%g1],%l2
808 nop ! change timing slightly
809 sdivcc %l1,%l2,%l4
810
811 setx sdivcc_miss4,%g7,%g1
812 ldx [%g1],%l2
813 sdivcc %l1,%l2,%g1 ! loaded value is zero
814
815
816 !****************************************************************
817 ! contention for register write ports
818 !****************************************************************
819reg_port_test:
820 rdth_id ! get thid in %o1
821 cmp %o1,3
822 be th_reg_3
823 cmp %o1,2
824 be th_reg_2
825 cmp %o1,1
826 be th_reg_1
827 nop
828 ! if there are more than 4 threads, run with same data as t0
829th_reg_0:
830 setx reg_port_contention_0,%g7,%g1
831 ba all_threads4
832 nop
833
834th_reg_1:
835 setx reg_port_contention_1,%g7,%g1
836 ba all_threads4
837 nop
838
839th_reg_2:
840 setx reg_port_contention_2,%g7,%g1
841 ba all_threads4
842 nop
843
844th_reg_3:
845 setx reg_port_contention_3,%g7,%g1
846 ba all_threads4
847 nop
848
849all_threads4:
850 ldx [%g1],%l1 ! cache miss, rs1
851 mulx %l1,0x0002,%l4
852 ldx [%g1],%l2 ! cache hit, rs1
853 mulx %l2,%l1,%l4
854
855 add %g1,0x20,%g1
856 ldx [%g1],%l1 ! cache miss, rs2
857 umul %l2,%l1,%l5
858 ldx [%g1+8],%l1 ! cache hit, rs2
859 umul %l2,%l1,%l5
860
861 add %g1,0x20,%g1
862 ldsb [%g1],%l1 ! cache miss, byte load, rs1
863 smul %l1,0x0008,%l3
864 ldub [%g1+13],%l6 ! cache hit, byte load, rs2
865 smul %l1,%l6,%l5
866
867 add %g1,0x20,%g1
868 ldsh [%g1+2],%l1 ! cache miss, halfword load, rs2
869 umulcc %l1,%l3,%l7
870 lduh [%g1],%l4 ! cache hit, halfword load, rs1
871 umulcc %l4,%l1,%l7
872
873 add %g1,0x20,%g1
874 ldsw [%g1+8],%l1 ! cache miss, word load, rs1
875 smulcc %l1,0x0020,%l6 ! same rd as next load
876 lduw [%g1],%l6 ! cache hit, word load, rs1
877 smulcc %l6,0x0020,%l5
878
879#ifndef MULSCC_BUGS
880 add %g1,0x20,%g1
881 wr %l1,0,%y
882 ldx [%g1],%l1 ! cache miss, rs1
883 mulscc %l1,0x0040,%l1
884 ldx [%g1+8],%l2 ! cache hit, rs2
885 mulscc %l1,%l2,%l5
886#endif
887
888 add %g1,0x20,%g1
889 ldx [%g1+8],%l1 ! cache miss, rs1 = rs2
890 mulx %l1,%l1,%l4
891 ldx [%g1],%l2 ! cache hit, rs1 = rs2
892 mulx %l2,%l2,%l4
893
894 add %g1,0x20,%g1
895 ldx [%g1],%l1 ! cache miss, rs1
896 sdivx %l1,%l3,%l3
897 ldx [%g1],%l3 ! cache hit, rs1
898 sdivx %l1,%l3,%l3
899
900 add %g1,0x20,%g1
901 ldx [%g1],%l2 ! cache miss, rs2
902 udivx %l1,%l2,%l4
903 ldx [%g1],%l2 ! cache hit, rs2
904 udivx %l1,%l2,%l4
905
906 add %g1,0x20,%g1
907 ldx [%g1],%l1 ! cache miss, rs1 and rs2
908 ldx [%g1+0x10],%l2
909 sdiv %l1,%l2,%l3
910 ldx [%g1+8],%l1 ! cache hit, rs1 and rs2
911 ldx [%g1+0x18],%l2
912 sdiv %l1,%l2,%l3
913
914 add %g1,0x20,%g1
915 ldx [%g1],%l1 ! cache miss, rs2 and rs1
916 ldx [%g1+0x10],%l2
917 udiv %l2,%l1,%l4
918 ldx [%g1],%l1 ! cache hit, rs2 and rs1
919 ldx [%g1+0x10],%l2
920 udiv %l2,%l1,%l4
921
922 add %g1,0x20,%g1
923 ldsw [%g1],%l1 ! cache miss, word load, rs1
924 sdivcc %l1,%l2,%l3
925 ldsw [%g1+4],%l1 ! cache hit, word load, rs2
926 sdivcc %l2,%l1,%l4
927
928 add %g1,0x20,%g1
929 lduh [%g1],%l1 ! cache miss, halfword load, rs2
930 udivcc %l2,%l1,%l3
931 ldsh [%g1],%l1 ! cache hit, halfword load, rs2
932 udivcc %l3,%l1,%l3
933
934good_end:
935 ta T_GOOD_TRAP
936 nop
937 nop
938
939
940!==========================
941.data
942.align 0x1fff+1
943 ! at an 8k boundary...
944
945 ! be sure each mul_data_t* has same number of cases
946mul_data_t0:
947 .xword 0x0000000000000000
948 .xword 0x0000000000000001
949
950 .xword 0x0000000000000003
951 .xword 0x000000000000000c
952
953 .xword 0x000000007fffffff
954 .xword 0x0000000080000000
955
956 .xword 0x0000000080000001
957 .xword 0x00000000fffffffe
958
959 .xword 0x7fffffffffffffff
960 .xword 0x8000000000000000
961
962 .xword 0x8000000000000001
963 .xword 0xfffffffffffffffc
964
965mul_data_t1:
966 .xword 0xffffffffffffffff
967 .xword 0x0000000000000001
968
969 .xword 0x000000007ffffffc
970 .xword 0x000000007fffffff
971
972 .xword 0x0000000080000000
973 .xword 0x0000000080000001
974
975 .xword 0x00000000fffffffe
976 .xword 0x7fffffffffffffff
977
978 .xword 0x8000000000000000
979 .xword 0x8000000000000001
980
981 .xword 0xffffffffffffffff
982 .xword 0xaaaaaaaaaaaaaaaa
983
984mul_data_t2:
985 .xword 0xaaaaaaaaaaaaaaaa
986 .xword 0x5555555555555555
987
988 .xword 0x1111111111111111
989 .xword 0xeeeeeeeeeeeeeeee
990
991 .xword 0xfffffffffffffffc
992 .xword 0xffffffff00000001
993
994 .xword 0x0000000088888888
995 .xword 0x0000000080000001
996
997 .xword 0x0000000000000001
998 .xword 0x00000000fffffffe
999
1000 .xword 0xffffffffffffffff
1001 .xword 0x80000aaa5550000e
1002
1003mul_data_t3:
1004 .xword 0x2222222222222222
1005 .xword 0x4444444444444444
1006
1007 .xword 0xcccccccccccccccc
1008 .xword 0x0000000000000002
1009
1010 .xword 0x0000000000000002
1011 .xword 0xf0f0f0f0f0f0f0f0
1012
1013 .xword 0xe11d548a139bcb18
1014 .xword 0x000000005aeb5d3b
1015
1016 .xword 0x056e61a23ad8a1c8
1017 .xword 0x6adb9bfd446daaac
1018
1019 .xword 0x000000002e5f37ec
1020 .xword 0x000000002eb16c25
1021
1022divx_data_t0:
1023 .xword 0x0000000000000000
1024 .xword 0x0000000000000001
1025
1026 .xword 0x0000000000000064
1027 .xword 0x0000000000000005
1028
1029 .xword 0x000000007ffffffc ! positive remainder
1030 .xword 0x000000007ffffffe
1031
1032 .xword 0x000000007fffffff
1033 .xword 0x0000000080000000
1034
1035divx_data_t1:
1036 .xword 0x0000000080000001
1037 .xword 0x00000000fffffffe
1038
1039 .xword 0x00000000ffffffff
1040 .xword 0x7ffffffffffffffe
1041
1042 .xword 0x7fffffffffffffff
1043 .xword 0x8000000000000000
1044
1045 .xword 0x8000000000000001
1046 .xword 0xfffffffffffffffc
1047
1048divx_data_t2:
1049 .xword 0xfffffffffffffffe
1050 .xword 0xffffffffffffffff
1051
1052 .xword 0x0000000000000001
1053 .xword 0x0000000000000010
1054
1055 .xword 0x0000000000000011
1056 .xword 0x000000007ffffffc
1057
1058 .xword 0x000000007ffffffe
1059 .xword 0x000000007fffffff
1060
1061divx_data_t3:
1062 .xword 0x0000000080000000
1063 .xword 0x0000000080000001
1064
1065 .xword 0x00000000fffffffe
1066 .xword 0x00000000ffffffff
1067
1068 .xword 0x7ffffffffffffffe
1069 .xword 0x7fffffffffffffff
1070
1071 .xword 0x8000000000000000 ! overflow case 800...000/-1
1072 .xword 0xffffffffffffffff
1073
1074div_data_t0:
1075 .xword 0x0000000000000000
1076 .xword 0x0000000000000001
1077
1078 .xword 0xffffffffffffff9c ! -100 decimal
1079 .xword 0x0000000000000014
1080
1081 .xword 0x000000007ffffffc
1082 .xword 0x000000007ffffffe
1083
1084 .xword 0x000000007fffffff
1085 .xword 0x0000000080000000
1086
1087div_data_t1:
1088 .xword 0x0000000080000001
1089 .xword 0x00000000fffffffe
1090
1091 .xword 0x00000000ffffffff
1092 .xword 0x7ffffffffffffffe
1093
1094 .xword 0x7fffffffffffffff
1095 .xword 0x8000000000000000 ! overflow case 800..../-1
1096
1097 .xword 0x8000000000000001
1098 .xword 0xfffffffffffffffc
1099
1100div_data_t2:
1101 .xword 0xfffffffffffffffe
1102 .xword 0xffffffffffffffff
1103
1104 .xword 0x0000000000000001
1105 .xword 0x0000000000000010
1106
1107 .xword 0x0000000000000011
1108 .xword 0x000000007ffffffc
1109
1110 .xword 0x000000007ffffffe
1111 .xword 0x000000007fffffff
1112
1113div_data_t3:
1114 .xword 0x0000000080000000
1115 .xword 0x0000000080000001
1116
1117 .xword 0x00000000fffffffe
1118 .xword 0x00000000ffffffff
1119
1120 .xword 0x7ffffffffffffffe
1121 .xword 0x7fffffffffffffff
1122
1123 .xword 0x8000000000000000 ! overflow case 800...000/-1
1124 .xword 0xffffffffffffffff
1125
1126immed_data:
1127 .word 0x00000000, 0x00000000
1128 .word 0x00000000, 0x7fffffff
1129 .word 0x00000000, 0x00000001
1130 .word 0x7fffffff, 0xffffffff
1131 .word 0xffffffff, 0xffffffff
1132
1133
1134.align 0x100
1135 !*********************************************************************
1136 ! at a 256byte boundary for cache miss/ uninitialized cache line tests
1137 !*********************************************************************
1138udivx_miss1:
1139 .word 0x00000000, 0x00001111 ! first half of line
1140.align 0x20
1141 .word 0, 0
1142udivx_miss2:
1143 .word 0x00000000, 0x00002222 ! second half of line
1144.align 0x20
1145udivx_miss3:
1146 .word 0xffffffff, 0xffff3333 ! for use with nop case
1147.align 0x20
1148udivx_miss4:
1149 .word 0x00000000, 0x00000000 ! divide by zero
1150
1151.align 0x20
1152sdivx_miss1:
1153 .word 0x00000000, 0x00001111 ! first half of line
1154.align 0x20
1155 .word 0, 0
1156sdivx_miss2:
1157 .word 0x00000000, 0x00002222 ! second half of line
1158.align 0x20
1159sdivx_miss3:
1160 .word 0xffffffff, 0xffff3333 ! for use with nop case
1161.align 0x20
1162sdivx_miss4:
1163 .word 0x00000000, 0x00000000 ! divide by zero
1164
1165.align 0x20
1166udiv_miss1:
1167 .word 0x00000000, 0x00001111 ! first half of line
1168.align 0x20
1169 .word 0, 0
1170udiv_miss2:
1171 .word 0x00000000, 0x00002222 ! second half of line
1172.align 0x20
1173udiv_miss3:
1174 .word 0xffffffff, 0xffff3333 ! for use with nop case
1175.align 0x20
1176udiv_miss4:
1177 .word 0x00000000, 0x00000000 ! divide by zero
1178
1179.align 0x20
1180sdivcc_miss1:
1181 .word 0x00000000, 0x00001111 ! first half of line
1182.align 0x20
1183 .word 0, 0
1184sdivcc_miss2:
1185 .word 0x00000000, 0x00002222 ! second half of line
1186.align 0x20
1187sdivcc_miss3:
1188 .word 0xffffffff, 0xffff3333 ! for use with nop case
1189.align 0x20
1190sdivcc_miss4:
1191 .word 0x00000000, 0x00000000 ! divide by zero
1192
1193.align 0x100
1194reg_port_contention_0: ! boring data
1195 .word 0x10000000, 0x00000001, 0xffffffff, 0xffffffff
1196 .word 0x20000000, 0x00000002, 0xffffffff, 0xfffffffe
1197 .word 0x40000000, 0x00000004, 0xffffffff, 0xfffffffd
1198 .word 0x80000000, 0x00000008, 0xffffffff, 0xfffffffb
1199 .word 0x01000000, 0x00000010, 0xffffffff, 0xfffffff7
1200 .word 0x02000000, 0x00000020, 0xffffffff, 0xffffffef
1201 .word 0x04000000, 0x00000040, 0xffffffff, 0xffffffdf
1202 .word 0x08000000, 0x00000080, 0xffffffff, 0xffffffbf
1203 .word 0x00100000, 0x00000100, 0xffffffff, 0xffffff7f
1204 .word 0x00200000, 0x00000200, 0xffffffff, 0xfffffeff
1205 .word 0x00400000, 0x00000400, 0xffffffff, 0xfffffdff
1206 .word 0x00800000, 0x00000800, 0xffffffff, 0xfffffbff
1207 .word 0x00010000, 0x00001000, 0xffffffff, 0xfffff7ff
1208 .word 0x00020000, 0x00002000, 0xffffffff, 0xffffefff
1209 .word 0x00040000, 0x00004000, 0xffffffff, 0xffffdfff
1210 .word 0x00080000, 0x00008000, 0xffffffff, 0xffffbfff
1211 .word 0x00001000, 0x00010000, 0xffffffff, 0xffff7fff
1212 .word 0x00002000, 0x00020000, 0xffffffff, 0xfffeffff
1213 .word 0x00004000, 0x00040000, 0xffffffff, 0xfffdffff
1214 .word 0x00008000, 0x00080000, 0xffffffff, 0xfffbffff
1215 .word 0x00000100, 0x00100000, 0xffffffff, 0xfff7ffff
1216 .word 0x10000000, 0x00000001, 0xffffffff, 0xffffffff
1217 .word 0x20000000, 0x00000002, 0xffffffff, 0xfffffffe
1218 .word 0x40000000, 0x00000004, 0xffffffff, 0xfffffffd
1219 .word 0x80000000, 0x00000008, 0xffffffff, 0xfffffffb
1220 .word 0x01000000, 0x00000010, 0xffffffff, 0xfffffff7
1221 .word 0x02000000, 0x00000020, 0xffffffff, 0xffffffef
1222 .word 0x04000000, 0x00000040, 0xffffffff, 0xffffffdf
1223 .word 0x08000000, 0x00000080, 0xffffffff, 0xffffffbf
1224 .word 0x00100000, 0x00000100, 0xffffffff, 0xffffff7f
1225 .word 0x00200000, 0x00000200, 0xffffffff, 0xfffffeff
1226 .word 0x00400000, 0x00000400, 0xffffffff, 0xfffffdff
1227 .word 0x00800000, 0x00000800, 0xffffffff, 0xfffffbff
1228 .word 0x00010000, 0x00001000, 0xffffffff, 0xfffff7ff
1229 .word 0x00020000, 0x00002000, 0xffffffff, 0xffffefff
1230 .word 0x00040000, 0x00004000, 0xffffffff, 0xffffdfff
1231 .word 0x00080000, 0x00008000, 0xffffffff, 0xffffbfff
1232 .word 0x00001000, 0x00010000, 0xffffffff, 0xffff7fff
1233 .word 0x00002000, 0x00020000, 0xffffffff, 0xfffeffff
1234 .word 0x00004000, 0x00040000, 0xffffffff, 0xfffdffff
1235 .word 0x00008000, 0x00080000, 0xffffffff, 0xfffbffff
1236 .word 0x00000100, 0x00100000, 0xffffffff, 0xfff7ffff
1237
1238reg_port_contention_1: ! boring data
1239 .word 0x1dead000, 0xdead0001, 0xffffffff, 0xffffffff
1240 .word 0x2dead000, 0xdead0002, 0xffffffff, 0xfffffffe
1241 .word 0x4dead000, 0xdead0004, 0xffffffff, 0xfffffffd
1242 .word 0x8dead000, 0xdead0008, 0xffffffff, 0xfffffffb
1243 .word 0x01dead00, 0xdead0010, 0xffffffff, 0xfffffff7
1244 .word 0x02dead00, 0xdead0020, 0xffffffff, 0xffffffef
1245 .word 0x04dead00, 0xdead0040, 0xffffffff, 0xffffffdf
1246 .word 0x08dead00, 0xdead0080, 0xffffffff, 0xffffffbf
1247 .word 0x001dead0, 0xdead0100, 0xffffffff, 0xffffff7f
1248 .word 0x002dead0, 0xdead0200, 0xffffffff, 0xfffffeff
1249 .word 0x004dead0, 0xdead0400, 0xffffffff, 0xfffffdff
1250 .word 0x008dead0, 0xdead0800, 0xffffffff, 0xfffffbff
1251 .word 0x0001dead, 0xdead1000, 0xffffffff, 0xfffff7ff
1252 .word 0x0002dead, 0xdead2000, 0xffffffff, 0xffffefff
1253 .word 0x0004dead, 0xdead4000, 0xffffffff, 0xffffdfff
1254 .word 0x0008dead, 0xdead8000, 0xffffffff, 0xffffbfff
1255 .word 0xdead1000, 0x0001dead, 0xffffffff, 0xffff7fff
1256 .word 0xdead2000, 0x0002dead, 0xffffffff, 0xfffeffff
1257 .word 0xdead4000, 0x0004dead, 0xffffffff, 0xfffdffff
1258 .word 0xdead8000, 0x0008dead, 0xffffffff, 0xfffbffff
1259 .word 0xdead0100, 0x001dead0, 0xffffffff, 0xfff7ffff
1260 .word 0x1dead000, 0xdead0001, 0xffffffff, 0xffffffff
1261 .word 0x2dead000, 0xdead0002, 0xffffffff, 0xfffffffe
1262 .word 0x4dead000, 0xdead0004, 0xffffffff, 0xfffffffd
1263 .word 0x8dead000, 0xdead0008, 0xffffffff, 0xfffffffb
1264 .word 0x01dead00, 0xdead0010, 0xffffffff, 0xfffffff7
1265 .word 0x02dead00, 0xdead0020, 0xffffffff, 0xffffffef
1266 .word 0x04dead00, 0xdead0040, 0xffffffff, 0xffffffdf
1267 .word 0x08dead00, 0xdead0080, 0xffffffff, 0xffffffbf
1268 .word 0x001dead0, 0xdead0100, 0xffffffff, 0xffffff7f
1269 .word 0x002dead0, 0xdead0200, 0xffffffff, 0xfffffeff
1270 .word 0x004dead0, 0xdead0400, 0xffffffff, 0xfffffdff
1271 .word 0x008dead0, 0xdead0800, 0xffffffff, 0xfffffbff
1272 .word 0x0001dead, 0xdead1000, 0xffffffff, 0xfffff7ff
1273 .word 0x0002dead, 0xdead2000, 0xffffffff, 0xffffefff
1274 .word 0x0004dead, 0xdead4000, 0xffffffff, 0xffffdfff
1275 .word 0x0008dead, 0xdead8000, 0xffffffff, 0xffffbfff
1276 .word 0xdead1000, 0x0001dead, 0xffffffff, 0xffff7fff
1277 .word 0xdead2000, 0x0002dead, 0xffffffff, 0xfffeffff
1278 .word 0xdead4000, 0x0004dead, 0xffffffff, 0xfffdffff
1279 .word 0xdead8000, 0x0008dead, 0xffffffff, 0xfffbffff
1280 .word 0xdead0100, 0x001dead0, 0xffffffff, 0xfff7ffff
1281
1282reg_port_contention_2: ! boring data
1283 .word 0x10000000, 0x00000001, 0xf0f0f0f0, 0xffffffff
1284 .word 0x20000000, 0x00000002, 0xf0f0f0f0, 0xfffffffe
1285 .word 0x40000000, 0x00000004, 0xf0f0f0f0, 0xfffffffd
1286 .word 0x80000000, 0x00000008, 0xf0f0f0f0, 0xfffffffb
1287 .word 0x01000000, 0x00000010, 0xf0f0f0f0, 0xfffffff7
1288 .word 0x02000000, 0x00000020, 0xf0f0f0f0, 0xffffffef
1289 .word 0x04000000, 0x00000040, 0xf0f0f0f0, 0xffffffdf
1290 .word 0x08000000, 0x00000080, 0xf0f0f0f0, 0xffffffbf
1291 .word 0x00100000, 0x00000100, 0xf0f0f0f0, 0xffffff7f
1292 .word 0x00200000, 0x00000200, 0xf0f0f0f0, 0xfffffeff
1293 .word 0x00400000, 0x00000400, 0xf0f0f0f0, 0xfffffdff
1294 .word 0x00800000, 0x00000800, 0xf0f0f0f0, 0xfffffbff
1295 .word 0x00010000, 0x00001000, 0xf0f0f0f0, 0xfffff7ff
1296 .word 0x00020000, 0x00002000, 0xf0f0f0f0, 0xffffefff
1297 .word 0x00040000, 0x00004000, 0xf0f0f0f0, 0xffffdfff
1298 .word 0x00080000, 0x00008000, 0xf0f0f0f0, 0xffffbfff
1299 .word 0x00001000, 0x00010000, 0xf0f0f0f0, 0xffff7fff
1300 .word 0x00002000, 0x00020000, 0xf0f0f0f0, 0xfffeffff
1301 .word 0x00004000, 0x00040000, 0xf0f0f0f0, 0xfffdffff
1302 .word 0x00008000, 0x00080000, 0xf0f0f0f0, 0xfffbffff
1303 .word 0x00000100, 0x00100000, 0xf0f0f0f0, 0xfff7ffff
1304 .word 0x10000000, 0x00000001, 0xf0f0f0f0, 0xf0f0f0f0
1305 .word 0x20000000, 0x00000002, 0xf0f0f0f0, 0xfffffffe
1306 .word 0x40000000, 0x00000004, 0xf0f0f0f0, 0xfffffffd
1307 .word 0x80000000, 0x00000008, 0xf0f0f0f0, 0xfffffffb
1308 .word 0x01000000, 0x00000010, 0xf0f0f0f0, 0xfffffff7
1309 .word 0x02000000, 0x00000020, 0xf0f0f0f0, 0xffffffef
1310 .word 0x04000000, 0x00000040, 0xf0f0f0f0, 0xffffffdf
1311 .word 0x08000000, 0x00000080, 0xf0f0f0f0, 0xffffffbf
1312 .word 0x00100000, 0x00000100, 0xf0f0f0f0, 0xffffff7f
1313 .word 0x00200000, 0x00000200, 0xf0f0f0f0, 0xfffffeff
1314 .word 0x00400000, 0x00000400, 0xf0f0f0f0, 0xfffffdff
1315 .word 0x00800000, 0x00000800, 0xf0f0f0f0, 0xfffffbff
1316 .word 0x00010000, 0x00001000, 0xf0f0f0f0, 0xfffff7ff
1317 .word 0x00020000, 0x00002000, 0xf0f0f0f0, 0xffffefff
1318 .word 0x00040000, 0x00004000, 0xf0f0f0f0, 0xffffdfff
1319 .word 0x00080000, 0x00008000, 0xf0f0f0f0, 0xffffbfff
1320 .word 0x00001000, 0x00010000, 0xf0f0f0f0, 0xffff7fff
1321 .word 0x00002000, 0x00020000, 0xf0f0f0f0, 0xfffeffff
1322 .word 0x00004000, 0x00040000, 0xf0f0f0f0, 0xfffdffff
1323 .word 0x00008000, 0x00080000, 0xf0f0f0f0, 0xfffbffff
1324 .word 0x00000100, 0x00100000, 0xf0f0f0f0, 0xfff7ffff
1325
1326reg_port_contention_3: ! boring data
1327 .word 0x10000000, 0x00000001, 0xffffffff, 0xffffffff
1328 .word 0x20000000, 0x00000002, 0xefffffff, 0xfffffffe
1329 .word 0x40000000, 0x00000004, 0xdfffffff, 0xfffffffd
1330 .word 0x80000000, 0x00000008, 0xbfffffff, 0xfffffffb
1331 .word 0x01000000, 0x00000010, 0x7fffffff, 0xfffffff7
1332 .word 0x02000000, 0x00000020, 0xfeffffff, 0xffffffef
1333 .word 0x04000000, 0x00000040, 0xfdffffff, 0xffffffdf
1334 .word 0x08000000, 0x00000080, 0xfbffffff, 0xffffffbf
1335 .word 0x00100000, 0x00000100, 0xf7ffffff, 0xffffff7f
1336 .word 0x00200000, 0x00000200, 0xffefffff, 0xfffffeff
1337 .word 0x00400000, 0x00000400, 0xffdfffff, 0xfffffdff
1338 .word 0x00800000, 0x00000800, 0xffbfffff, 0xfffffbff
1339 .word 0x00010000, 0x00001000, 0xff7fffff, 0xfffff7ff
1340 .word 0x00020000, 0x00002000, 0xfffeffff, 0xffffefff
1341 .word 0x00040000, 0x00004000, 0xfffdffff, 0xffffdfff
1342 .word 0x00080000, 0x00008000, 0xfffbffff, 0xffffbfff
1343 .word 0x00001000, 0x00010000, 0xfff7ffff, 0xffff7fff
1344 .word 0x00002000, 0x00020000, 0xffffefff, 0xfffeffff
1345 .word 0x00004000, 0x00040000, 0xffffdfff, 0xfffdffff
1346 .word 0x00008000, 0x00080000, 0xffffbfff, 0xfffbffff
1347 .word 0x00000100, 0x00100000, 0xffff7fff, 0xfff7ffff
1348 .word 0x10000000, 0x00000001, 0xfffffeff, 0xffffffff
1349 .word 0x20000000, 0x00000002, 0xfffffdff, 0xfffffffe
1350 .word 0x40000000, 0x00000004, 0xfffffbff, 0xfffffffd
1351 .word 0x80000000, 0x00000008, 0xfffff7ff, 0xfffffffb
1352 .word 0x01000000, 0x00000010, 0xffffffef, 0xfffffff7
1353 .word 0x02000000, 0x00000020, 0xffffffdf, 0xffffffef
1354 .word 0x04000000, 0x00000040, 0xffffffbf, 0xffffffdf
1355 .word 0x08000000, 0x00000080, 0xffffff7f, 0xffffffbf
1356 .word 0x00100000, 0x00000100, 0xfffffffe, 0xffffff7f
1357 .word 0x00200000, 0x00000200, 0xfffffffd, 0xfffffeff
1358 .word 0x00400000, 0x00000400, 0xfffffffb, 0xfffffdff
1359 .word 0x00800000, 0x00000800, 0xfffffff7, 0xfffffbff
1360 .word 0x00010000, 0x00001000, 0x7fffffff, 0xfffff7ff
1361 .word 0x00020000, 0x00002000, 0x3fffffff, 0xffffefff
1362 .word 0x00040000, 0x00004000, 0x1fffffff, 0xffffdfff
1363 .word 0x00080000, 0x00008000, 0x0fffffff, 0xffffbfff
1364 .word 0x00001000, 0x00010000, 0x07ffffff, 0xffff7fff
1365 .word 0x00002000, 0x00020000, 0x03ffffff, 0xfffeffff
1366 .word 0x00004000, 0x00040000, 0x01ffffff, 0xfffdffff
1367 .word 0x00008000, 0x00080000, 0x007fffff, 0xfffbffff
1368 .word 0x00000100, 0x00100000, 0x003fffff, 0xfff7ffff
1369
1370.end
Full OpenSPARC design & verification tarball including full HDL.