[OpenSPARC-T2-DV] / verif / diag / assembly / exu / ffu_faligndata_n2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: ffu_faligndata_n2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_T0_Fp_disabled_0x20

	#define  MAIN_PAGE_HV_ALSO  
#define  MAIN_PAGE_NUCLEUS_ALSO

#define ENABLE_T0_Clean_Window_0x24
#define ENABLE_T0_Corrected_ECC_error_0x63 
#define ENABLE_T0_Data_Access_Exception_0x30 
#define ENABLE_T0_Data_access_error_0x32 
#define ENABLE_T0_Division_By_Zero_0x28 
#define ENABLE_T0_Fp_disabled_0x20
#define ENABLE_T0_Fp_exception_ieee_754_0x21 
#define ENABLE_T0_Fp_exception_other_0x22 
#define ENABLE_T0_Illegal_instruction_0x10
#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
#define ENABLE_T0_Instruction_access_error_0x0a 
#define ENABLE_T0_Instruction_access_exception_0x08
#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
#define ENABLE_T0_Mem_Address_Not_Aligned_0x34 
#define ENABLE_T0_Privileged_Action_0x37 
#define ENABLE_T0_Privileged_opcode_0x11
#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
#define ENABLE_T0_Tag_Overflow_0x23 
#define ENABLE_T0_Unimplemented_LDD_0x12
#define ENABLE_T0_Unimplemented_STD_0x13
#define ENABLE_T0_data_access_protection_0x6c 
#define ENABLE_T0_fast_data_access_MMU_miss_0x68
#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
	
#include "hboot.s"


#define	check_result(label) \
	ldx	[%l2+%i2], %i1; \
	cmp	%i0, %i1; \
	be      label; \
	add	%i2, 0x8, %i2; \
	ta	BAD_TRAP

.global sam_fast_immu_miss
.global sam_fast_dmmu_miss


/****************START OF TEST*********************************************/


.text
.global main
ALIGN_PAGE_8K

user_text_start:

main:
	
	        wr      %g0, 0x4, %fprs         /* make sure fef is 1 */

		set	data, %g1
		set 	store_result, %l1
		set 	exp_result_start, %l2

		mov	0x0, %l3
		mov	0x0, %i2

		ldd	[%g1], %f0
		ldd	[%g1+8], %f2
		ldd	[%g1+16], %f4
		ldd	[%g1+24], %f6


!write to gsr followed by faligndata
tst_0:
		wr	%l3, %g0, %asr19	!align_offset=0
		faligndata	%f0, %f2, %f32	!since align_offset=0, so, %f32=%f0
		fcmpd	%fcc3, %f0, %f32	
		fbe	%fcc3, tst_1
		add	%l3, 0x1, %l3	!increment l3
		ta	BAD_TRAP


!align offset = 1
tst_1:
		wr	%l3, %g0, %asr19	!align_offset =1
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]	!store freg (dw) into store_result
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l3
		check_result(tst_2)

!align offset = 2
tst_2:
		wr	%l3, %g0, %asr19	!align_offset =2
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l2
		check_result(tst_3)

!align offset = 3
tst_3:
		wr	%l3, %g0, %asr19	!align_offset =3
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l2
		check_result(tst_4)

!align offset = 4
tst_4:
		wr	%l3, %g0, %asr19	!align_offset =4
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l2
		check_result(tst_5)

!align offset = 5
tst_5:
		wr	%l3, %g0, %asr19	!align_offset =5
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l2
		check_result(tst_6)

!align offset = 6
tst_6:
		wr	%l3, %g0, %asr19	!align_offset =6
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l2
		check_result(tst_7)

!align offset = 7
tst_7:
		wr	%l3, %g0, %asr19	!align_offset =7
		faligndata	%f0, %f2, %f32
		std 	%f32, [%l1]
		ldx	[%l1], %i0
		add	%l3, 0x1, %l3	!increment l2
		check_result(tst_8)

!align offset = 0
tst_8:
		wr	%l3, %g0, %asr19	!align_offset =0
		faligndata	%f2, %f0, %f32
		fcmpd	%fcc2, %f2, %f32	
		fbe	%fcc2, end_of_test
		nop	
		ta	BAD_TRAP


end_of_test:	ta	GOOD_TRAP
bad:		ta	BAD_TRAP
user_text_end:


.seg "data"


ALIGN_PAGE_8K

user_data_start:
.align 8
data:
	.word 0x01234567, 0x89abcdef
	.word 0xfedcba98, 0x76543210
	.word 0x11223344, 0x66778899
	.word 0xeeccbbaa, 0x00dd55ff

.align 8
store_result:
		.skip 512

.align 8
short_load: 
		.byte 0x56, 0x0, 0x0,0x0
		.byte 0x0,0x0, 0x0, 0x0
		.byte 0xa9, 0x0, 0x0, 0x0
		.byte 0x0,0x0, 0x0, 0x0
		.half 0xfecd,0x0
		.half 0x0,0x0
		.half 0x5678,0x0
		.half 0x0,0x0

.align 8
exp_result_start:
		.word 0x23456789, 0xabcdeffe
		.word 0x456789ab, 0xcdeffedc
		.word 0x6789abcd, 0xeffedcba
		.word 0x89abcdef, 0xfedcba98
		.word 0xabcdeffe, 0xdcba9876
		.word 0xcdeffedc, 0xba987654
		.word 0xeffedcba, 0x98765432
		.word 0x66778899, 0xeeccbbaa
		.word 0x99eeccbb, 0xaa00dd55
		.word 0x01112233, 0x44667788
		.word 0x76543210, 0x11223344
		.word 0x00dd55ff, 0xfedcba98
		.word 0xaa00dd55, 0xfffedcba
		.word 0x98765432, 0x10eeccbb
		.word 0xfedcba98, 0x76543210
		.word 0x56000000, 0x0
		.word 0x56780000, 0x0
		.word 0xeda8eda8, 0x00007731
		.word 0x33884499, 0x0
		.word 0x44993388, 0x44993388
		.word 0x0, 0x00440000


user_data_end:
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: ffu_faligndata_n2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_T0_Fp_disabled_0x20
	39
	40	#define MAIN_PAGE_HV_ALSO
	41	#define MAIN_PAGE_NUCLEUS_ALSO
	42
	43	#define ENABLE_T0_Clean_Window_0x24
	44	#define ENABLE_T0_Corrected_ECC_error_0x63
	45	#define ENABLE_T0_Data_Access_Exception_0x30
	46	#define ENABLE_T0_Data_access_error_0x32
	47	#define ENABLE_T0_Division_By_Zero_0x28
	48	#define ENABLE_T0_Fp_disabled_0x20
	49	#define ENABLE_T0_Fp_exception_ieee_754_0x21
	50	#define ENABLE_T0_Fp_exception_other_0x22
	51	#define ENABLE_T0_Illegal_instruction_0x10
	52	#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
	53	#define ENABLE_T0_Instruction_access_error_0x0a
	54	#define ENABLE_T0_Instruction_access_exception_0x08
	55	#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
	56	#define ENABLE_T0_Mem_Address_Not_Aligned_0x34
	57	#define ENABLE_T0_Privileged_Action_0x37
	58	#define ENABLE_T0_Privileged_opcode_0x11
	59	#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
	60	#define ENABLE_T0_Tag_Overflow_0x23
	61	#define ENABLE_T0_Unimplemented_LDD_0x12
	62	#define ENABLE_T0_Unimplemented_STD_0x13
	63	#define ENABLE_T0_data_access_protection_0x6c
	64	#define ENABLE_T0_fast_data_access_MMU_miss_0x68
65	#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
66
67	#include "hboot.s"
68
69
70	#define check_result(label) \
71	ldx [%l2+%i2], %i1; \
72	cmp %i0, %i1; \
73	be label; \
74	add %i2, 0x8, %i2; \
75	ta BAD_TRAP
76
77	.global sam_fast_immu_miss
78	.global sam_fast_dmmu_miss
79
80
81	/**************START OF TEST*******************************************/
82
83
84	.text
85	.global main
86	ALIGN_PAGE_8K
87
88	user_text_start:
89
90	main:
91
92	wr %g0, 0x4, %fprs /* make sure fef is 1 */
93
94	set data, %g1
95	set store_result, %l1
96	set exp_result_start, %l2
97
98	mov 0x0, %l3
99	mov 0x0, %i2
100
101	ldd [%g1], %f0
102	ldd [%g1+8], %f2
103	ldd [%g1+16], %f4
104	ldd [%g1+24], %f6
105
106
107	!write to gsr followed by faligndata
108	tst_0:
109	wr %l3, %g0, %asr19 !align_offset=0
110	faligndata %f0, %f2, %f32 !since align_offset=0, so, %f32=%f0
111	fcmpd %fcc3, %f0, %f32
112	fbe %fcc3, tst_1
113	add %l3, 0x1, %l3 !increment l3
114	ta BAD_TRAP
115
116
117	!align offset = 1
118	tst_1:
119	wr %l3, %g0, %asr19 !align_offset =1
120	faligndata %f0, %f2, %f32
121	std %f32, [%l1] !store freg (dw) into store_result
122	ldx [%l1], %i0
123	add %l3, 0x1, %l3 !increment l3
124	check_result(tst_2)
125
126	!align offset = 2
127	tst_2:
128	wr %l3, %g0, %asr19 !align_offset =2
129	faligndata %f0, %f2, %f32
130	std %f32, [%l1]
131	ldx [%l1], %i0
132	add %l3, 0x1, %l3 !increment l2
133	check_result(tst_3)
134
135	!align offset = 3
136	tst_3:
137	wr %l3, %g0, %asr19 !align_offset =3
138	faligndata %f0, %f2, %f32
139	std %f32, [%l1]
140	ldx [%l1], %i0
141	add %l3, 0x1, %l3 !increment l2
142	check_result(tst_4)
143
144	!align offset = 4
145	tst_4:
146	wr %l3, %g0, %asr19 !align_offset =4
147	faligndata %f0, %f2, %f32
148	std %f32, [%l1]
149	ldx [%l1], %i0
150	add %l3, 0x1, %l3 !increment l2
151	check_result(tst_5)
152
153	!align offset = 5
154	tst_5:
155	wr %l3, %g0, %asr19 !align_offset =5
156	faligndata %f0, %f2, %f32
157	std %f32, [%l1]
158	ldx [%l1], %i0
159	add %l3, 0x1, %l3 !increment l2
160	check_result(tst_6)
161
162	!align offset = 6
163	tst_6:
164	wr %l3, %g0, %asr19 !align_offset =6
165	faligndata %f0, %f2, %f32
166	std %f32, [%l1]
167	ldx [%l1], %i0
168	add %l3, 0x1, %l3 !increment l2
169	check_result(tst_7)
170
171	!align offset = 7
172	tst_7:
173	wr %l3, %g0, %asr19 !align_offset =7
174	faligndata %f0, %f2, %f32
175	std %f32, [%l1]
176	ldx [%l1], %i0
177	add %l3, 0x1, %l3 !increment l2
178	check_result(tst_8)
179
180	!align offset = 0
181	tst_8:
182	wr %l3, %g0, %asr19 !align_offset =0
183	faligndata %f2, %f0, %f32
184	fcmpd %fcc2, %f2, %f32
185	fbe %fcc2, end_of_test
186	nop
187	ta BAD_TRAP
188
189
190
191
192
193	end_of_test: ta GOOD_TRAP
194	bad: ta BAD_TRAP
195	user_text_end:
196
197
198	.seg "data"
199
200
201	ALIGN_PAGE_8K
202
203	user_data_start:
204	.align 8
205	data:
206	.word 0x01234567, 0x89abcdef
207	.word 0xfedcba98, 0x76543210
208	.word 0x11223344, 0x66778899
209	.word 0xeeccbbaa, 0x00dd55ff
210
211	.align 8
212	store_result:
213	.skip 512
214
215	.align 8
216	short_load:
217	.byte 0x56, 0x0, 0x0,0x0
218	.byte 0x0,0x0, 0x0, 0x0
219	.byte 0xa9, 0x0, 0x0, 0x0
220	.byte 0x0,0x0, 0x0, 0x0
221	.half 0xfecd,0x0
222	.half 0x0,0x0
223	.half 0x5678,0x0
224	.half 0x0,0x0
225
226	.align 8
227	exp_result_start:
228	.word 0x23456789, 0xabcdeffe
229	.word 0x456789ab, 0xcdeffedc
230	.word 0x6789abcd, 0xeffedcba
231	.word 0x89abcdef, 0xfedcba98
232	.word 0xabcdeffe, 0xdcba9876
233	.word 0xcdeffedc, 0xba987654
234	.word 0xeffedcba, 0x98765432
235	.word 0x66778899, 0xeeccbbaa
236	.word 0x99eeccbb, 0xaa00dd55
237	.word 0x01112233, 0x44667788
238	.word 0x76543210, 0x11223344
239	.word 0x00dd55ff, 0xfedcba98
240	.word 0xaa00dd55, 0xfffedcba
241	.word 0x98765432, 0x10eeccbb
242	.word 0xfedcba98, 0x76543210
243	.word 0x56000000, 0x0
244	.word 0x56780000, 0x0
245	.word 0xeda8eda8, 0x00007731
246	.word 0x33884499, 0x0
247	.word 0x44993388, 0x44993388
248	.word 0x0, 0x00440000
249
250
251	user_data_end: