projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / exu / fp_pstate_fpdis_n2.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: fp_pstate_fpdis_n2.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_T0_Fp_disabled_0x20
39
40#define MAIN_PAGE_HV_ALSO
41#define MAIN_PAGE_NUCLEUS_ALSO
42
43#define ENABLE_T0_Clean_Window_0x24
44#define ENABLE_T0_Corrected_ECC_error_0x63
45#define ENABLE_T0_Data_Access_Exception_0x30
46#define ENABLE_T0_Data_access_error_0x32
47#define ENABLE_T0_Division_By_Zero_0x28
48#define ENABLE_T0_Fp_disabled_0x20
49#define ENABLE_T0_Fp_exception_ieee_754_0x21
50#define ENABLE_T0_Fp_exception_other_0x22
51#define ENABLE_HT0_Illegal_instruction_0x10
52#define ENABLE_T0_Instruction_Access_MMU_Miss_0x09
53#define ENABLE_T0_Instruction_access_error_0x0a
54#define ENABLE_T0_Instruction_access_exception_0x08
55#define ENABLE_T0_Lddf_Mem_Address_Not_Aligned_0x35
56#define ENABLE_T0_Mem_Address_Not_Aligned_0x34
57#define ENABLE_T0_Privileged_Action_0x37
58#define ENABLE_T0_Privileged_opcode_0x11
59#define ENABLE_T0_Stdf_Mem_Address_Not_Aligned_0x36
60#define ENABLE_T0_Tag_Overflow_0x23
61#define ENABLE_T0_Unimplemented_LDD_0x12
62#define ENABLE_T0_Unimplemented_STD_0x13
63#define ENABLE_T0_data_access_protection_0x6c
64#define ENABLE_T0_fast_data_access_MMU_miss_0x68
65#define ENABLE_T0_fast_instr_access_MMU_miss_0x64
66
67
68#include "hboot.s"
69
70.global sam_fast_immu_miss
71.global sam_fast_dmmu_miss
72
73.text
74.global main
75
76main:
77
78/*
79 **********************************************************
80 *
81 * This diag tests all fp instructions with pstate.pef=0
82 *
83 **********************************************************
84*/
85
86/*
87 * Need to be priv mode
88 *
89*/
90
91 ta T_CHANGE_PRIV
92
93/*
94 * Set pstate.pef = 0
95 *
96*/
97 wr %g0, 0x7, %fprs /* make sure fef is 1 */
98 rdpr %pstate, %l0
99 mov 0xfef, %l1 /* set pstate.pef[4] to 0 */
100 and %l0, %l1, %l0
101 wrpr %g0, %l0, %pstate
102
103/*
104 ********************************
105 * All FP instructions
106 ********************************
107*/
108
109/* Expect every fp instruction to be faulted
110 First read PC into %l5
111 Set a count in %l7, this is incremented in the trap handler.
112 Read PC at the end into %l6
113 %l4 is for incrementing illegal instruction trap count
114 %l3 is for incrementing illegal instruction expected trap count
115*/
116
117 wr %g0, 0x0, %asi ! Set it to 0 - this should be irrelevant
118
119 set 0x0, %l3
120 set 0x0, %l4
121 set 0x0, %l7
122 rd %pc, %l5
123
124/* fbfcc */
125
126 fba test_fail
127 fbn test_fail ! This is not causing trap (??)
128 fbu test_fail
129 fbg test_fail
130 fbug test_fail
131 fbl test_fail
132 fbul test_fail
133 fblg test_fail
134 fbne test_fail
135 fbe test_fail
136 fbue test_fail
137 fbge test_fail
138 fbuge test_fail
139 fble test_fail
140 fbule test_fail
141 fbo test_fail
142
143/* fbpfcc */
144
145 fba,pt %fcc0, test_fail
146 fbn,pt %fcc0, test_fail ! This is not cauing trap (??)
147 fbu,pt %fcc0, test_fail
148 fbg,pt %fcc0, test_fail
149 fbug,pt %fcc0, test_fail
150 fbl,pt %fcc0, test_fail
151 fbul,pt %fcc0, test_fail
152 fblg,pt %fcc0, test_fail
153 fbne,pt %fcc0, test_fail
154 fbe,pt %fcc0, test_fail
155 fbue,pt %fcc0, test_fail
156 fbge,pt %fcc0, test_fail
157 fbuge,pt %fcc0, test_fail
158 fble,pt %fcc0, test_fail
159 fbule,pt %fcc0, test_fail
160 fbo,pt %fcc0, test_fail
161
162/* floating point add and subtract */
163
164 fadds %f0, %f1, %f2
165 faddd %f0, %f2, %f4
166 faddq %f0, %f4, %f8
167 fsubs %f0, %f1, %f2
168 fsubd %f0, %f2, %f4
169 fsubq %f0, %f4, %f8
170
171/* floating point add and subtract */
172
173 fcmps %fcc0,%f1, %f2
174 fcmpd %fcc1,%f2, %f4
175 fcmpq %fcc2,%f4, %f8
176 fcmpes %fcc3,%f1, %f2
177 fcmped %fcc0,%f2, %f4
178 fcmpeq %fcc1,%f4, %f8
179
180/* Convert fp to int */
181
182 fstox %f0, %f0
183 fdtox %f0, %f0
184 fqtox %f0, %f0
185 fstoi %f0, %f0
186 fdtoi %f0, %f0
187 fqtoi %f0, %f0
188
189/* Convert fp to fp */
190
191 fstod %f0, %f0
192 fstoq %f0, %f0
193 fdtos %f0, %f0
194 fdtoq %f0, %f0
195 fqtos %f0, %f0
196 fqtod %f0, %f0
197
198/* Convert int to fp */
199
200 fxtos %f0, %f0
201 fxtod %f0, %f0
202 fxtoq %f0, %f0
203 fitos %f0, %f0
204 fitod %f0, %f0
205 fitoq %f0, %f0
206
207/* Floating point mov */
208
209 fmovs %f0, %f0
210 fmovd %f0, %f0
211 fmovq %f0, %f0
212 fnegs %f0, %f0
213 fnegd %f0, %f0
214 fnegq %f0, %f0
215 fabss %f0, %f0
216 fabsd %f0, %f0
217 fabsq %f0, %f0
218
219/* Floating point multiply and divide */
220
221 fmuls %f0, %f0, %f0
222 fmuld %f0, %f0, %f0
223 fmulq %f0, %f0, %f0
224 fsmuld %f0, %f0, %f0
225 fdmulq %f0, %f0, %f0
226 fdivs %f0, %f0, %f0
227 fdivd %f0, %f0, %f0
228 fdivq %f0, %f0, %f0
229
230/* Floating point square root */
231
232! fsqrts %f0, %f0
233! fsqrtd %f0, %f0
234! fsqrtq %f0, %f0
235
236/* Load Floating point */
237
238 ld [%g0], %f0
239 ldd [%g0], %f0
240 add %l3, 0x1, %l3 ! Expect illegal inst. trap
241 ldq [%g0], %f0 ! This is causing 0x10 (??)
242 ld [%g0], %fsr
243 ldx [%g0], %fsr
244 add %l3, 0x1, %l3 ! Expect illegal inst. trap
245 .word 0xc5080000 ! %fsr p. 174 - (op3=0x21, rd = 2..31) - rd = 0x2
246 add %l3, 0x1, %l3 ! Expect illegal inst. trap
247 .word 0xff080000 ! %fsr p. 174 - (op3=0x21, rd = 2..31) - rd = 0x31
248
249/* Load Floating point asi */
250
251 lda [%g0] 0x0, %f0
252 lda [%g0+0x0] %asi, %f0
253 ldda [%g0] 0x0, %f0
254 ldda [%g0+0x0] %asi, %f0
255 add %l3, 0x1, %l3 ! Expect illegal inst. trap
256 ldqa [%g0] 0x0, %f0
257 add %l3, 0x1, %l3 ! Expect illegal inst. trap
258 ldqa [%g0+0x0] %asi, %f0
259
260/* Floating point move on %icc or %xcc */
261
262 fmovsa %xcc, %f4, %f0
263 fmovsn %xcc, %f4, %f0
264 fmovsne %xcc, %f4, %f0
265 fmovse %xcc, %f4, %f0
266 fmovsg %xcc, %f4, %f0
267 fmovsle %xcc, %f4, %f0
268 fmovsge %xcc, %f4, %f0
269 fmovsl %xcc, %f4, %f0
270 fmovsgu %xcc, %f4, %f0
271 fmovsleu %xcc, %f4, %f0
272 fmovscc %xcc, %f4, %f0
273 fmovscs %xcc, %f4, %f0
274 fmovspos %xcc, %f4, %f0
275 fmovsneg %xcc, %f4, %f0
276 fmovsvc %xcc, %f4, %f0
277 fmovsvs %xcc, %f4, %f0
278
279 fmovda %xcc, %f4, %f0
280 fmovdn %xcc, %f4, %f0
281 fmovdne %xcc, %f4, %f0
282 fmovde %xcc, %f4, %f0
283 fmovdg %xcc, %f4, %f0
284 fmovdle %xcc, %f4, %f0
285 fmovdge %xcc, %f4, %f0
286 fmovdl %xcc, %f4, %f0
287 fmovdgu %xcc, %f4, %f0
288 fmovdleu %xcc, %f4, %f0
289 fmovdcc %xcc, %f4, %f0
290 fmovdcs %xcc, %f4, %f0
291 fmovdpos %xcc, %f4, %f0
292 fmovdneg %xcc, %f4, %f0
293 fmovdvc %xcc, %f4, %f0
294 fmovdvs %xcc, %f4, %f0
295
296 fmovqa %xcc, %f4, %f0
297 fmovqn %xcc, %f4, %f0
298 fmovqne %xcc, %f4, %f0
299 fmovqe %xcc, %f4, %f0
300 fmovqg %xcc, %f4, %f0
301 fmovqle %xcc, %f4, %f0
302 fmovqge %xcc, %f4, %f0
303 fmovql %xcc, %f4, %f0
304 fmovqgu %xcc, %f4, %f0
305 fmovqleu %xcc, %f4, %f0
306 fmovqcc %xcc, %f4, %f0
307 fmovqcs %xcc, %f4, %f0
308 fmovqpos %xcc, %f4, %f0
309 fmovqneg %xcc, %f4, %f0
310 fmovqvc %xcc, %f4, %f0
311 fmovqvs %xcc, %f4, %f0
312
313 fmovsa %icc, %f4, %f0
314 fmovsn %icc, %f4, %f0
315 fmovsne %icc, %f4, %f0
316 fmovse %icc, %f4, %f0
317 fmovsg %icc, %f4, %f0
318 fmovsle %icc, %f4, %f0
319 fmovsge %icc, %f4, %f0
320 fmovsl %icc, %f4, %f0
321 fmovsgu %icc, %f4, %f0
322 fmovsleu %icc, %f4, %f0
323 fmovscc %icc, %f4, %f0
324 fmovscs %icc, %f4, %f0
325 fmovspos %icc, %f4, %f0
326 fmovsneg %icc, %f4, %f0
327 fmovsvc %icc, %f4, %f0
328 fmovsvs %icc, %f4, %f0
329
330 fmovda %icc, %f4, %f0
331 fmovdn %icc, %f4, %f0
332 fmovdne %icc, %f4, %f0
333 fmovde %icc, %f4, %f0
334 fmovdg %icc, %f4, %f0
335 fmovdle %icc, %f4, %f0
336 fmovdge %icc, %f4, %f0
337 fmovdl %icc, %f4, %f0
338 fmovdgu %icc, %f4, %f0
339 fmovdleu %icc, %f4, %f0
340 fmovdcc %icc, %f4, %f0
341 fmovdcs %icc, %f4, %f0
342 fmovdpos %icc, %f4, %f0
343 fmovdneg %icc, %f4, %f0
344 fmovdvc %icc, %f4, %f0
345 fmovdvs %icc, %f4, %f0
346
347 fmovqa %icc, %f4, %f0
348 fmovqn %icc, %f4, %f0
349 fmovqne %icc, %f4, %f0
350 fmovqe %icc, %f4, %f0
351 fmovqg %icc, %f4, %f0
352 fmovqle %icc, %f4, %f0
353 fmovqge %icc, %f4, %f0
354 fmovql %icc, %f4, %f0
355 fmovqgu %icc, %f4, %f0
356 fmovqleu %icc, %f4, %f0
357 fmovqcc %icc, %f4, %f0
358 fmovqcs %icc, %f4, %f0
359 fmovqpos %icc, %f4, %f0
360 fmovqneg %icc, %f4, %f0
361 fmovqvc %icc, %f4, %f0
362 fmovqvs %icc, %f4, %f0
363
364 fmovsa %fcc0, %f4, %f0
365 fmovsn %fcc1, %f4, %f0
366 fmovsu %fcc2, %f4, %f0
367 fmovsg %fcc3, %f4, %f0
368 fmovsug %fcc0, %f4, %f0
369 fmovsl %fcc1, %f4, %f0
370 fmovsul %fcc2, %f4, %f0
371 fmovslg %fcc3, %f4, %f0
372 fmovsne %fcc0, %f4, %f0
373 fmovse %fcc1, %f4, %f0
374 fmovsue %fcc2, %f4, %f0
375 fmovsge %fcc3, %f4, %f0
376 fmovsuge %fcc0, %f4, %f0
377 fmovsle %fcc1, %f4, %f0
378 fmovsule %fcc2, %f4, %f0
379 fmovso %fcc3, %f4, %f0
380
381 fmovda %fcc0, %f4, %f0
382 fmovdn %fcc1, %f4, %f0
383 fmovdu %fcc2, %f4, %f0
384 fmovdg %fcc3, %f4, %f0
385 fmovdug %fcc0, %f4, %f0
386 fmovdl %fcc1, %f4, %f0
387 fmovdul %fcc2, %f4, %f0
388 fmovdlg %fcc3, %f4, %f0
389 fmovdne %fcc0, %f4, %f0
390 fmovde %fcc1, %f4, %f0
391 fmovdue %fcc2, %f4, %f0
392 fmovdge %fcc3, %f4, %f0
393 fmovduge %fcc0, %f4, %f0
394 fmovdle %fcc1, %f4, %f0
395 fmovdule %fcc2, %f4, %f0
396 fmovdo %fcc3, %f4, %f0
397
398 fmovqa %fcc0, %f4, %f0
399 fmovqn %fcc1, %f4, %f0
400 fmovqu %fcc2, %f4, %f0
401 fmovqg %fcc3, %f4, %f0
402 fmovqug %fcc0, %f4, %f0
403 fmovql %fcc1, %f4, %f0
404 fmovqul %fcc2, %f4, %f0
405 fmovqlg %fcc3, %f4, %f0
406 fmovqne %fcc0, %f4, %f0
407 fmovqe %fcc1, %f4, %f0
408 fmovque %fcc2, %f4, %f0
409 fmovqge %fcc3, %f4, %f0
410 fmovquge %fcc0, %f4, %f0
411 fmovqle %fcc1, %f4, %f0
412 fmovqule %fcc2, %f4, %f0
413 fmovqo %fcc3, %f4, %f0
414
415/* Floating point move on integer register */
416
417 fmovrse %g1, %f0, %f4
418 fmovrslez %g1, %f0, %f4
419 fmovrslz %g1, %f0, %f4
420 fmovrsne %g1, %f0, %f4
421 fmovrsgz %g1, %f0, %f4
422 fmovrsgez %g1, %f0, %f4
423
424 fmovrde %g0, %f0, %f4
425 fmovrdlez %g0, %f0, %f4
426 fmovrdlz %g0, %f0, %f4
427 fmovrdne %g0, %f0, %f4
428 fmovrdgz %g0, %f0, %f4
429 fmovrdgez %g0, %f0, %f4
430
431 fmovrqe %g1, %f0, %f4
432 fmovrqlez %g1, %f0, %f4
433 fmovrqlz %g1, %f0, %f4
434 fmovrqne %g1, %f0, %f4
435 fmovrqgz %g1, %f0, %f4
436 fmovrqgez %g1, %f0, %f4
437
438 .word 0x8da85ce0 ! Should cause fp exception other for quads but fp disabled is higher prio
439 .word 0x89a840e0 ! Should cause fp exception other (rcond=000) but fp disabled is higher pri (??)
440 .word 0x89a850e0 ! Should cause fp exception other (rcond=100) but fp disabled is higher pri (??)
441
442/* Integer move on floating point CC */
443
444 mova %fcc0, %g0, %g1
445 movn %fcc1, %g0, %g1
446 movu %fcc2, %g0, %g1
447 movg %fcc3, %g0, %g1
448 movug %fcc0, %g0, %g1
449 movl %fcc1, %g0, %g1
450 movul %fcc2, %g0, %g1
451 movlg %fcc3, %g0, %g1
452 movne %fcc0, %g0, %g1
453 move %fcc1, %g0, %g1
454 movue %fcc2, %g0, %g1
455 movge %fcc3, %g0, %g1
456 movuge %fcc0, %g0, %g1
457 movle %fcc1, %g0, %g1
458 movule %fcc2, %g0, %g1
459 movo %fcc3, %g0, %g1
460
461/* rdpr and rd */
462
463 add %l3, 0x1, %l3 ! Expect illegal inst. trap
464 rdpr %fq, %g0 ! illegal instruction (??)
465 rd %fprs, %g0 ! This shouldnt cause a trap
466 add %l7, 0x2, %l7
467
468/* Floating point store */
469
470 st %f0, [%g0]
471 std %f0, [%g0]
472 add %l3, 0x1, %l3 ! Expect illegal inst. trap
473 stq %f0, [%g0]
474 st %fsr, [%g0]
475 stx %fsr, [%g0]
476
477 add %l3, 0x1, %l3 ! Expect illegal inst. trap
478 .word 0xc5280000 ! %fsr p. 226 - (op3=0x25, rd = 2..31) - rd = 0x2
479 add %l3, 0x1, %l3 ! Expect illegal inst. trap
480 .word 0xfd280000 ! %fsr p. 226 - (op3=0x25, rd = 2..31) - rd = 0x31
481
482/* Floating point store asi */
483
484 sta %f0, [%g0] 0x0
485 sta %f0, [%g0+0x0] %asi
486 stda %f0, [%g0] 0x0
487 stda %f0, [%g0+0x0] %asi
488 add %l3, 0x1, %l3 ! Expect illegal inst. trap
489 stqa %f0, [%g0] 0x0
490 add %l3, 0x1, %l3 ! Expect illegal inst. trap
491 stqa %f0, [%g0+0x0] %asi
492
493/* wr */
494
495 wr %g0, 0x0, %fprs ! This shouldnt cause a trap
496 add %l7, 0x2, %l7
497
498/* Branch to test done - self checking - Cant trust SIMICS entirely */
499
500 rd %pc, %l6 ! read pc and save it
501
502 subcc %l3, %l4, %l2 ! Check illegal inst. trap count
503! bne test_fail if illegal inst. trap count doesnt match, test failed
504 nop
505
506 sub %l6, %l5, %l5 ! Subtract both PCs
507 srl %l5, 0x2, %l5 ! Get the count
508 sub %l5, %l3, %l5 ! Account for add instructions
509 sub %l5, 0x1, %l5 ! Account for rd pc operations
510 subcc %l5, %l7, %l5
511
512! bne test_fail ! if the total trap count doesnt match, test failed
513 nop
514
515 ba test_pass
516 nop
517
518test_fail:
519 ta T_BAD_TRAP
520
521
522test_pass:
523 ta T_GOOD_TRAP
524
525/* Own trap handler */
526
Full OpenSPARC design & verification tarball including full HDL.