[OpenSPARC-T2-DV] / verif / diag / assembly / include / apex_tt60_handler.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: apex_tt60_handler.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MONDO_DATA0_OFF 0x00
#define MONDO_DATA1_OFF 0x08
        
#define IMAP_REG_OFF    0x10
#define ICLR_REG_OFF    0x18        

#define INT_THREAD_OFF  0x20        
#define INT_TICK_OFF    0x28        
        
#define INT_COUNT_OFF   0x30        
#define DEV_STATUS_OFF  0x38        
#define INT_ACK_OFF     0x3C        
        
#define INT_DATA_OFF    0x800       
#define INT_DATA_SIZE   0x40        

/* Misc defines ... */        
#define TT60_CNT_OFF    0x00       

#define N2TH_MASK       0x3f       

#define PEP_INO_MASK    0x03     
#define INT_INO_MASK    0x3f     
        
#define PEP_CSR_BASE    0xc800000100        
#define PEP_CSR_SIZE    0x100        
#define PEP_INTx_ACK    0x08                    

#define BOBO_INT_BASE   0x07000                 
#define BOBO_ENG_BASE   0x10000                  
#define BOBO_ENG_SIZE   0x2000                
#define BOBO_INTx_ACK   0x01                    
                        
#define PIU_MEM64_ADR   0x0000008000002010 
#define PIU_MEM64_MSK   0x0000000fff000000

#define PIU_CSR_BASE    0x0000008800000000         
#define PIU_IMU_ELOG    0x0000000000631010         
#define PIU_MMU_ELOG    0x0000000000641010         
#define PIU_ILU_ELOG    0x0000000000651010         
#define PIU_PEU_OLOG    0x0000000000681010         
#define PIU_PEU_ELOG    0x0000000000691010         
#define PIU_INT_STAT    0x000000000060b000         
        
#define PEP_INT_ACK_OFF 0x24             
#define PEP_STAT_OFF    0x14                    

#define BOBO_INT_ACK_OFF 0x00             
#define BOBO_STAT_OFF    0x70                    

        
SECTION .HTRAPS
.text
.global apex_tt60
/*
   g1 = vector 
   g2 = tick     
*/        
apex_tt60:

apex_decode_vector:                     
        cmp     %g1, 21                     ! IO_MONDO
        be      apex_int_vector
        cmp     %g1, 62                     ! ERR_MONDO
        be      apex_err_vector
        nop           
        ba      apex_bad_vector
        nop       
                
apex_int_vector:          
#ifdef NCX_ALIAS_BUG
        ldxa    [%g0] ASI_INTR_ID, %g7          ! Get the thread number in %g7
        sllx    %g7, 3, %g7
        best_set_reg(MONDO_INT_DATA1, %g4, %g3)
        add     %g7, %g3, %g3        
        ldx     [%g3], %g6
        best_set_reg(MONDO_INT_DATA0, %g4, %g3)
        add     %g7, %g3, %g3     
        ldx     [%g3], %g7
#else        
        best_set_reg(MONDO_INT_ADATA1, %g4, %g3)
        ldx     [%g3], %g6
        best_set_reg(MONDO_INT_ADATA0, %g4, %g3)
        ldx     [%g3], %g7
#endif
        and     %g7, INT_INO_MASK, %g4                                           
        cmp     %g4, 24
        bl      apex_tt60_intx                  ! 20, 21, 22, 23 are INTA, B, C, D
        
        sllx    %g4, 3, %g4                     ! s/b int_play2 interrupt, just clear it.
        setx    0x8800601400, %g3, %g2        
        add     %g2, %g4, %g2              
        stx     %g0, [%g2]                      ! clr bridge int state machine
        b       apex_tt60_clr_busy
        nop
        
apex_tt60_intx:                 
        setx    (pep_ctl_base + INT_DATA_OFF), %g4, %g3     
        and     %g7, PEP_INO_MASK, %g4          ! Low order bits of INO are engine #

/* The following code gets the node ID and adds it to the   */
/* index of the interrupt control structure (INO).             */        
/* We assume a max of 4 interrupt control structures per node. */  
#if (NODE_COUNT > 1)
#ifdef  NCX_SYS_MODE_BUG      
        mov     0xa9, %g1
        sllx    %g1, 32, %g1    
        ldx     [%g1], %g1     
        srlx    %g1, 21, %g1         
        and     %g1, 0x0c, %g1                 
        add     %g4, %g1, %g4      
#else        
        mov     0x81, %g1
        sllx    %g1, 32, %g1            
        add     %g1, 8, %g1 
        ldx     [%g1], %g1
        srlx    %g1, 2, %g1     
        and     %g1, 0x0c, %g1           
        add     %g4, %g1, %g4      
#endif        
#endif        
        
        mulx    %g4, INT_DATA_SIZE, %g4        
        add     %g4, %g3, %g3                   ! %g3 is base of interrupt control struct (ic).
        
        stx     %g7, [%g3+MONDO_DATA0_OFF]
        stx     %g6, [%g3+MONDO_DATA1_OFF]
        stx     %g2, [%g3+INT_TICK_OFF]           
         
        ldxa    [%g0] ASI_INTR_ID, %g1          ! Get the thread number in %g1
        stx     %g1, [%g3+INT_THREAD_OFF]        

        best_set_reg(PIU_MEM64_ADR, %g4, %g2)   
        ldx     [%g2], %g2              
        sllx    %g2, 28, %g2
        srlx    %g2, 60, %g2
        or      %g2, 0xc0, %g2
        sllx    %g2, 32, %g2                    ! %g2 has regbase now
        ldx     [%g3+MONDO_DATA0_OFF], %g4
        and     %g4, PEP_INO_MASK, %g4          ! Low order bits of INO are engine #        
        
#if UBOBO
        setx    BOBO_ENG_BASE, %g1, %g6    
        add     %g2, %g6, %g7                   ! %g7 is bobo engine base       
        setx    BOBO_ENG_SIZE, %g1, %g6        
        mulx    %g4, %g6, %g6        
        add     %g7, %g6, %g7                   ! %g7 is bobo csr base for this engine          
        add     %g7, BOBO_STAT_OFF, %g1
#else        
        inc     %g4                             ! Pep 0 csr is at 0x100
        mulx    %g4, PEP_CSR_SIZE, %g6        
        add     %g6, %g2, %g7                   ! %g7 is pep csr base for this engine
        add     %g7, PEP_STAT_OFF, %g1
#endif        

        lduwa   [%g1] 0x0c, %g4                 ! get status (ASI_NL)     
        stw     %g4, [%g3+DEV_STATUS_OFF]                

        ldx     [%g3+MONDO_DATA0_OFF], %g4
        and     %g4, PEP_INO_MASK, %g4          ! Low order bits of INO are engine            

#if UBOBO 
        setx    BOBO_INT_BASE, %g1, %g6    
        add     %g2, %g6, %g7                   ! %g7 is bobo int array base        
        mov     BOBO_INTx_ACK, %g5
        sllx    %g5, %g4, %g5          
        add     %g7, BOBO_INT_ACK_OFF, %g1
        stwa    %g5, [%g1] 0x0c                 ! write pep intx ack (ASI_NL)     
        mov     PEP_INTx_ACK, %g5
        srlx    %g5, %g4, %g5                   ! INTx ack based on INO/Eng              
#else                        
        mov     PEP_INTx_ACK, %g5
        srlx    %g5, %g4, %g5                   ! INTx ack based on INO/Eng        
        add     %g7, PEP_INT_ACK_OFF, %g1
        stwa    %g5, [%g1] 0x0c                 ! write pep intx ack (ASI_NL)     
#endif
        
        setx    (PIU_CSR_BASE + PIU_INT_STAT), %g4, %g6                    
        ldx     [%g6], %g4      
deassert_loop:          
        andcc   %g5, %g4, %g0
        bnz     deassert_loop        
        ldx     [%g6], %g4              
        
        ldx     [%g3+ICLR_REG_OFF], %g2
        stx     %g0, [%g2]                      ! clr bridge int state machine
                        
apex_tt60exit:  
        ldx     [%g3+INT_COUNT_OFF], %g2
        add     %g2, 1, %g2
        stx     %g2, [%g3+INT_COUNT_OFF]        ! This causes pep to be unlocked.

apex_tt60_clr_busy:             
#ifdef NCX_ALIAS_BUG        
        best_set_reg(MONDO_INT_BUSY, %g4, %g3) 
        ldxa    [%g0] ASI_INTR_ID, %g7          ! Get the thread number in %g7
        sllx    %g7, 3, %g7
        add     %g7, %g3, %g3
#else                
        best_set_reg(MONDO_INT_ABUSY, %g4, %g3) 
#endif
        stx     %g0, [%g3]                      ! clr mondo busy
        retry    

#if 0
MMU_ERR_RW1C_ALIAS                                 (8800641018) == 00000000-00000000
IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS     (8800631018) == 00000000-00000000
ILU_CIB_ILU_LOG_ERR_RW1C_ALIAS                     (8800651018) == 00000000-00000000
ILU_CIB_PEC_EN_ERR                                 (8800651808) == 00000000-00000000
TLU_CTB_TLR_OE_ERR_RW1C_ALIAS                      (8800681018) == 00000000-00000000
TLU_CTB_TLR_UE_ERR_RW1C_ALIAS                      (8800691018) == 00000000-00000000
TLU_CTB_TLR_CE_ERR_RW1C_ALIAS                      (88006a1018) == 00000000-00000000
TLU_CTB_TLR_EVENT_ERR_STS_CLR_RW1C_ALIAS           (88006e2120) == 00000000-07014001
#endif
        
apex_err_vector:              
        setx    PIU_CSR_BASE, %g4, %g3         
        
        setx    PIU_IMU_ELOG, %g4, %g2
        ldx     [%g3+%g2], %g4

        setx    PIU_MMU_ELOG, %g4, %g2
        ldx     [%g3+%g2], %g4

        setx    PIU_ILU_ELOG, %g4, %g2
        ldx     [%g3+%g2], %g4

        setx    PIU_PEU_OLOG, %g4, %g2
        ldx     [%g3+%g2], %g4

        setx    PIU_PEU_ELOG, %g4, %g2
        ldx     [%g3+%g2], %g4
                
        ta      T_BAD_TRAP
        nop
                
apex_bad_vector:        
        ta      T_BAD_TRAP
        nop
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: apex_tt60_handler.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MONDO_DATA0_OFF 0x00
	39	#define MONDO_DATA1_OFF 0x08
	40
	41	#define IMAP_REG_OFF 0x10
	42	#define ICLR_REG_OFF 0x18
	43
	44	#define INT_THREAD_OFF 0x20
	45	#define INT_TICK_OFF 0x28
	46
	47	#define INT_COUNT_OFF 0x30
	48	#define DEV_STATUS_OFF 0x38
	49	#define INT_ACK_OFF 0x3C
	50
	51	#define INT_DATA_OFF 0x800
	52	#define INT_DATA_SIZE 0x40
	53
	54	/* Misc defines ... */
	55	#define TT60_CNT_OFF 0x00
	56
	57	#define N2TH_MASK 0x3f
	58
	59	#define PEP_INO_MASK 0x03
	60	#define INT_INO_MASK 0x3f
	61
	62	#define PEP_CSR_BASE 0xc800000100
	63	#define PEP_CSR_SIZE 0x100
	64	#define PEP_INTx_ACK 0x08
65
66	#define BOBO_INT_BASE 0x07000
67	#define BOBO_ENG_BASE 0x10000
68	#define BOBO_ENG_SIZE 0x2000
69	#define BOBO_INTx_ACK 0x01
70
71	#define PIU_MEM64_ADR 0x0000008000002010
72	#define PIU_MEM64_MSK 0x0000000fff000000
73
74	#define PIU_CSR_BASE 0x0000008800000000
75	#define PIU_IMU_ELOG 0x0000000000631010
76	#define PIU_MMU_ELOG 0x0000000000641010
77	#define PIU_ILU_ELOG 0x0000000000651010
78	#define PIU_PEU_OLOG 0x0000000000681010
79	#define PIU_PEU_ELOG 0x0000000000691010
80	#define PIU_INT_STAT 0x000000000060b000
81
82	#define PEP_INT_ACK_OFF 0x24
83	#define PEP_STAT_OFF 0x14
84
85	#define BOBO_INT_ACK_OFF 0x00
86	#define BOBO_STAT_OFF 0x70
87
88
89	SECTION .HTRAPS
90	.text
91	.global apex_tt60
92	/*
93	g1 = vector
94	g2 = tick
95	*/
96	apex_tt60:
97
98	apex_decode_vector:
99	cmp %g1, 21 ! IO_MONDO
100	be apex_int_vector
101	cmp %g1, 62 ! ERR_MONDO
102	be apex_err_vector
103	nop
104	ba apex_bad_vector
105	nop
106
107	apex_int_vector:
108	#ifdef NCX_ALIAS_BUG
109	ldxa [%g0] ASI_INTR_ID, %g7 ! Get the thread number in %g7
110	sllx %g7, 3, %g7
111	best_set_reg(MONDO_INT_DATA1, %g4, %g3)
112	add %g7, %g3, %g3
113	ldx [%g3], %g6
114	best_set_reg(MONDO_INT_DATA0, %g4, %g3)
115	add %g7, %g3, %g3
116	ldx [%g3], %g7
117	#else
118	best_set_reg(MONDO_INT_ADATA1, %g4, %g3)
119	ldx [%g3], %g6
120	best_set_reg(MONDO_INT_ADATA0, %g4, %g3)
121	ldx [%g3], %g7
122	#endif
123	and %g7, INT_INO_MASK, %g4
124	cmp %g4, 24
125	bl apex_tt60_intx ! 20, 21, 22, 23 are INTA, B, C, D
126
127	sllx %g4, 3, %g4 ! s/b int_play2 interrupt, just clear it.
128	setx 0x8800601400, %g3, %g2
129	add %g2, %g4, %g2
130	stx %g0, [%g2] ! clr bridge int state machine
131	b apex_tt60_clr_busy
132	nop
133
134	apex_tt60_intx:
135	setx (pep_ctl_base + INT_DATA_OFF), %g4, %g3
136	and %g7, PEP_INO_MASK, %g4 ! Low order bits of INO are engine #
137
138	/* The following code gets the node ID and adds it to the */
139	/* index of the interrupt control structure (INO). */
140	/* We assume a max of 4 interrupt control structures per node. */
141	#if (NODE_COUNT > 1)
142	#ifdef NCX_SYS_MODE_BUG
143	mov 0xa9, %g1
144	sllx %g1, 32, %g1
145	ldx [%g1], %g1
146	srlx %g1, 21, %g1
147	and %g1, 0x0c, %g1
148	add %g4, %g1, %g4
149	#else
150	mov 0x81, %g1
151	sllx %g1, 32, %g1
152	add %g1, 8, %g1
153	ldx [%g1], %g1
154	srlx %g1, 2, %g1
155	and %g1, 0x0c, %g1
156	add %g4, %g1, %g4
157	#endif
158	#endif
159
160	mulx %g4, INT_DATA_SIZE, %g4
161	add %g4, %g3, %g3 ! %g3 is base of interrupt control struct (ic).
162
163	stx %g7, [%g3+MONDO_DATA0_OFF]
164	stx %g6, [%g3+MONDO_DATA1_OFF]
165	stx %g2, [%g3+INT_TICK_OFF]
166
167	ldxa [%g0] ASI_INTR_ID, %g1 ! Get the thread number in %g1
168	stx %g1, [%g3+INT_THREAD_OFF]
169
170	best_set_reg(PIU_MEM64_ADR, %g4, %g2)
171	ldx [%g2], %g2
172	sllx %g2, 28, %g2
173	srlx %g2, 60, %g2
174	or %g2, 0xc0, %g2
175	sllx %g2, 32, %g2 ! %g2 has regbase now
176	ldx [%g3+MONDO_DATA0_OFF], %g4
177	and %g4, PEP_INO_MASK, %g4 ! Low order bits of INO are engine #
178
179	#if UBOBO
180	setx BOBO_ENG_BASE, %g1, %g6
181	add %g2, %g6, %g7 ! %g7 is bobo engine base
182	setx BOBO_ENG_SIZE, %g1, %g6
183	mulx %g4, %g6, %g6
184	add %g7, %g6, %g7 ! %g7 is bobo csr base for this engine
185	add %g7, BOBO_STAT_OFF, %g1
186	#else
187	inc %g4 ! Pep 0 csr is at 0x100
188	mulx %g4, PEP_CSR_SIZE, %g6
189	add %g6, %g2, %g7 ! %g7 is pep csr base for this engine
190	add %g7, PEP_STAT_OFF, %g1
191	#endif
192
193	lduwa [%g1] 0x0c, %g4 ! get status (ASI_NL)
194	stw %g4, [%g3+DEV_STATUS_OFF]
195
196	ldx [%g3+MONDO_DATA0_OFF], %g4
197	and %g4, PEP_INO_MASK, %g4 ! Low order bits of INO are engine
198
199	#if UBOBO
200	setx BOBO_INT_BASE, %g1, %g6
201	add %g2, %g6, %g7 ! %g7 is bobo int array base
202	mov BOBO_INTx_ACK, %g5
203	sllx %g5, %g4, %g5
204	add %g7, BOBO_INT_ACK_OFF, %g1
205	stwa %g5, [%g1] 0x0c ! write pep intx ack (ASI_NL)
206	mov PEP_INTx_ACK, %g5
207	srlx %g5, %g4, %g5 ! INTx ack based on INO/Eng
208	#else
209	mov PEP_INTx_ACK, %g5
210	srlx %g5, %g4, %g5 ! INTx ack based on INO/Eng
211	add %g7, PEP_INT_ACK_OFF, %g1
212	stwa %g5, [%g1] 0x0c ! write pep intx ack (ASI_NL)
213	#endif
214
215	setx (PIU_CSR_BASE + PIU_INT_STAT), %g4, %g6
216	ldx [%g6], %g4
217	deassert_loop:
218	andcc %g5, %g4, %g0
219	bnz deassert_loop
220	ldx [%g6], %g4
221
222	ldx [%g3+ICLR_REG_OFF], %g2
223	stx %g0, [%g2] ! clr bridge int state machine
224
225	apex_tt60exit:
226	ldx [%g3+INT_COUNT_OFF], %g2
227	add %g2, 1, %g2
228	stx %g2, [%g3+INT_COUNT_OFF] ! This causes pep to be unlocked.
229
230	apex_tt60_clr_busy:
231	#ifdef NCX_ALIAS_BUG
232	best_set_reg(MONDO_INT_BUSY, %g4, %g3)
233	ldxa [%g0] ASI_INTR_ID, %g7 ! Get the thread number in %g7
234	sllx %g7, 3, %g7
235	add %g7, %g3, %g3
236	#else
237	best_set_reg(MONDO_INT_ABUSY, %g4, %g3)
238	#endif
239	stx %g0, [%g3] ! clr mondo busy
240	retry
241
242	#if 0
243	MMU_ERR_RW1C_ALIAS (8800641018) == 00000000-00000000
244	IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS (8800631018) == 00000000-00000000
245	ILU_CIB_ILU_LOG_ERR_RW1C_ALIAS (8800651018) == 00000000-00000000
246	ILU_CIB_PEC_EN_ERR (8800651808) == 00000000-00000000
247	TLU_CTB_TLR_OE_ERR_RW1C_ALIAS (8800681018) == 00000000-00000000
248	TLU_CTB_TLR_UE_ERR_RW1C_ALIAS (8800691018) == 00000000-00000000
249	TLU_CTB_TLR_CE_ERR_RW1C_ALIAS (88006a1018) == 00000000-00000000
250	TLU_CTB_TLR_EVENT_ERR_STS_CLR_RW1C_ALIAS (88006e2120) == 00000000-07014001
251	#endif
252
253	apex_err_vector:
254	setx PIU_CSR_BASE, %g4, %g3
255
256	setx PIU_IMU_ELOG, %g4, %g2
257	ldx [%g3+%g2], %g4
258
259	setx PIU_MMU_ELOG, %g4, %g2
260	ldx [%g3+%g2], %g4
261
262	setx PIU_ILU_ELOG, %g4, %g2
263	ldx [%g3+%g2], %g4
264
265	setx PIU_PEU_OLOG, %g4, %g2
266	ldx [%g3+%g2], %g4
267
268	setx PIU_PEU_ELOG, %g4, %g2
269	ldx [%g3+%g2], %g4
270
271	ta T_BAD_TRAP
272	nop
273
274	apex_bad_vector:
275	ta T_BAD_TRAP
276	nop
277