projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: asi_s.h | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | ! ASI defines for Niagara2 | |
| 39 | ! | |
| 40 | ! In some cases, there is more than one name for the same ASI. | |
| 41 | ! This is so that legacy diags will still run on N2. | |
| 42 | ! | |
| 43 | ||
| 44 | #ifndef __ASI_S_H__ | |
| 45 | #define __ASI_S_H__ | |
| 46 | ||
| 47 | #define ASI_N ASI_NUCLEUS | |
| 48 | #define ASI_NUCLEUS 0x04 | |
| 49 | #define ASI_NL ASI_NUCLEUS_LITTLE | |
| 50 | #define ASI_NUCLEUS_LITTLE 0x0c | |
| 51 | #define ASI_AIUP ASI_AS_IF_USER_PRIMARY | |
| 52 | #define ASI_AS_IF_USER_PRIMARY 0x10 | |
| 53 | #define ASI_AIUS ASI_AS_IF_USER_SECONDARY | |
| 54 | #define ASI_AS_IF_USER_SECONDARY 0x11 | |
| 55 | #define ASI_REAL_MEM 0X14 | |
| 56 | #define ASI_REAL_IO 0x15 | |
| 57 | #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY | |
| 58 | #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x16 | |
| 59 | #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY | |
| 60 | #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY | |
| 61 | #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x17 | |
| 62 | #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE | |
| 63 | #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 | |
| 64 | #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE | |
| 65 | #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 | |
| 66 | #define ASI_REAL_MEM_LITTLE 0x1c | |
| 67 | #define ASI_REAL_IO_LITTLE 0x1d | |
| 68 | #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE | |
| 69 | #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x1e | |
| 70 | #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE | |
| 71 | #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1f | |
| 72 | ||
| 73 | #define ASI_SCRATCHPAD 0x20 | |
| 74 | #define ASI_SCRATCHPAD_0 0x000 | |
| 75 | #define ASI_SCRATCHPAD_1 0x008 | |
| 76 | #define ASI_SCRATCHPAD_2 0x010 | |
| 77 | #define ASI_SCRATCHPAD_3 0x018 | |
| 78 | #define ASI_SCRATCHPAD_4 0x020 | |
| 79 | #define ASI_SCRATCHPAD_5 0x028 | |
| 80 | #define ASI_SCRATCHPAD_6 0x030 | |
| 81 | #define ASI_SCRATCHPAD_7 0x038 | |
| 82 | ||
| 83 | #define ASI_PRIMARY_CONTEXT_REG 0x21 | |
| 84 | #define ASI_PRIMARY_CONTEXT_0_REG_VAL 0x008 | |
| 85 | #define ASI_PRIMARY_CONTEXT_1_REG_VAL 0x108 | |
| 86 | #define ASI_SECONDARY_CONTEXT_REG 0x21 | |
| 87 | #define ASI_SECONDARY_CONTEXT_0_REG_VAL 0x010 | |
| 88 | #define ASI_SECONDARY_CONTEXT_1_REG_VAL 0x110 | |
| 89 | #define ASI_AS_IF_USER_BLK_INIT_PRIMARY 0x22 | |
| 90 | #define ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P ASI_AS_IF_USER_BLK_INIT_PRIMARY | |
| 91 | #define ASI_AS_IF_USER_BLK_INIT_SECONDARY 0x23 | |
| 92 | #define ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S ASI_AS_IF_USER_BLK_INIT_SECONDARY | |
| 93 | #define ASI_NUCLEUS_QUAD_LDD 0x24 | |
| 94 | ||
| 95 | #define ASI_QUEUE 0x25 | |
| 96 | #define ASI_CPU_MONDO_QUEUE_HEAD 0x3c0 | |
| 97 | #define ASI_CPU_MONDO_QUEUE_TAIL 0x3c8 | |
| 98 | #define ASI_DEVICE_QUEUE_HEAD 0x3d0 | |
| 99 | #define ASI_DEVICE_QUEUE_TAIL 0x3d8 | |
| 100 | #define ASI_RES_ERROR_QUEUE_HEAD 0x3e0 | |
| 101 | #define ASI_RES_ERROR_QUEUE_TAIL 0x3e8 | |
| 102 | #define ASI_NONRES_ERROR_QUEUE_HEAD 0x3f0 | |
| 103 | #define ASI_NONRES_ERROR_QUEUE_TAIL 0x3f8 | |
| 104 | ||
| 105 | #define ASI_QUAD_LDD_REAL 0x26 | |
| 106 | #define ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD 0x27 | |
| 107 | #define ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P_LITTLE 0x2a | |
| 108 | #define ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S_LITTLE 0x2b | |
| 109 | #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c | |
| 110 | #define ASI_QUAD_LDD_REAL_LITTLE 0x2e | |
| 111 | #define ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD_LITTLE 0x2f | |
| 112 | #define ASI_QUAD_LDD_PHYS 0x34 | |
| 113 | #define ASI_QUAD_LDD_PHYS_L ASI_QUAD_LDD_PHYS_LITTLE | |
| 114 | #define ASI_QUAD_LDD_PHYS_LITTLE 0x3c | |
| 115 | ||
| 116 | #define ASI_SPU 0x40 | |
| 117 | #define ASI_SPU_CWQ_HEAD 0x000 | |
| 118 | #define ASI_SPU_CWQ_TAIL 0x008 | |
| 119 | #define ASI_SPU_CWQ_FIRST 0x010 | |
| 120 | #define ASI_SPU_CWQ_LAST 0x018 | |
| 121 | #define ASI_SPU_CWQ_CSR 0x020 | |
| 122 | #define ASI_SPU_CWQ_CSR_TE 0x028 | |
| 123 | #define ASI_SPU_CWQ_SYNC 0x030 | |
| 124 | #define ASI_SPU_MA_CTL 0x080 | |
| 125 | #define ASI_SPU_MA_PA 0x088 | |
| 126 | #define ASI_SPU_MA_ADDR 0x090 | |
| 127 | #define ASI_SPU_MA_NP 0x098 | |
| 128 | #define ASI_SPU_MA_SYNC 0x0A0 | |
| 129 | #define ASI_SPU_CR0 0x100 | |
| 130 | #define ASI_SPU_CR1 0x108 | |
| 131 | #define ASI_SPU_SD0 0x110 | |
| 132 | #define ASI_SPU_SD1 0x118 | |
| 133 | #define ASI_SPU_SD2 0x120 | |
| 134 | #define ASI_SPU_SD3 0x128 | |
| 135 | #define ASI_SPU_SD4 0x130 | |
| 136 | #define ASI_SPU_SD5 0x138 | |
| 137 | #define ASI_SPU_SD6 0x140 | |
| 138 | #define ASI_SPU_SD7 0x148 | |
| 139 | #define ASI_SPU_K0 0x150 | |
| 140 | #define ASI_SPU_K1 0x158 | |
| 141 | #define ASI_SPU_K2 0x160 | |
| 142 | #define ASI_SPU_K3 0x168 | |
| 143 | #define ASI_SPU_IV0 0x170 | |
| 144 | #define ASI_SPU_IV1 0x178 | |
| 145 | #define ASI_SPU_AK0 0x180 | |
| 146 | #define ASI_SPU_AK1 0x188 | |
| 147 | #define ASI_SPU_AK2 0x190 | |
| 148 | #define ASI_SPU_AK3 0x198 | |
| 149 | #define ASI_SPU_CD0 0x1a0 | |
| 150 | #define ASI_SPU_CD1 0x1a8 | |
| 151 | #define ASI_SPU_CD2 0x1b0 | |
| 152 | #define ASI_SPU_CD3 0x1b8 | |
| 153 | #define ASI_SPU_CD4 0x1c0 | |
| 154 | #define ASI_SPU_CD5 0x1c8 | |
| 155 | #define ASI_SPU_CD6 0x1d0 | |
| 156 | #define ASI_SPU_CD7 0x1d8 | |
| 157 | #define ASI_SPU_HD0 0x1e0 | |
| 158 | #define ASI_SPU_HD1 0x1e8 | |
| 159 | #define ASI_SPU_HD2 0x1f0 | |
| 160 | #define ASI_SPU_HD3 0x1f8 | |
| 161 | #define ASI_SPU_SYNC 0x208 | |
| 162 | #define ASI_SPU_RC4_0 0x300 | |
| 163 | #define ASI_SPU_RC4_1 0x308 | |
| 164 | #define ASI_SPU_RC4_2 0x310 | |
| 165 | #define ASI_SPU_RC4_3 0x318 | |
| 166 | #define ASI_SPU_RC4_4 0x320 | |
| 167 | #define ASI_SPU_RC4_5 0x328 | |
| 168 | #define ASI_SPU_RC4_6 0x330 | |
| 169 | #define ASI_SPU_RC4_7 0x338 | |
| 170 | #define ASI_SPU_RC4_8 0x340 | |
| 171 | #define ASI_SPU_RC4_9 0x348 | |
| 172 | #define ASI_SPU_RC4_10 0x350 | |
| 173 | #define ASI_SPU_RC4_11 0x358 | |
| 174 | #define ASI_SPU_RC4_12 0x360 | |
| 175 | #define ASI_SPU_RC4_13 0x368 | |
| 176 | #define ASI_SPU_RC4_14 0x370 | |
| 177 | #define ASI_SPU_RC4_15 0x378 | |
| 178 | #define ASI_SPU_RC4_16 0x380 | |
| 179 | #define ASI_SPU_RC4_17 0x388 | |
| 180 | #define ASI_SPU_RC4_18 0x390 | |
| 181 | #define ASI_SPU_RC4_19 0x398 | |
| 182 | #define ASI_SPU_RC4_20 0x3a0 | |
| 183 | #define ASI_SPU_RC4_21 0x3a8 | |
| 184 | #define ASI_SPU_RC4_22 0x3b0 | |
| 185 | #define ASI_SPU_RC4_23 0x3b8 | |
| 186 | #define ASI_SPU_RC4_24 0x3c0 | |
| 187 | #define ASI_SPU_RC4_25 0x3c8 | |
| 188 | #define ASI_SPU_RC4_26 0x3d0 | |
| 189 | #define ASI_SPU_RC4_27 0x3d8 | |
| 190 | #define ASI_SPU_RC4_28 0x3e0 | |
| 191 | #define ASI_SPU_RC4_29 0x3e8 | |
| 192 | #define ASI_SPU_RC4_30 0x3f0 | |
| 193 | #define ASI_SPU_RC4_31 0x3f8 | |
| 194 | #define ASI_SPU_RC4_XY 0x400 | |
| 195 | ||
| 196 | #define ASI_CMP_CORE 0x41 | |
| 197 | #define ASI_CMP_CORE_AVAIL 0x000 | |
| 198 | #define ASI_CMP_CORE_ENABLED 0x010 | |
| 199 | #define ASI_CMP_CORE_ENABLE 0x020 | |
| 200 | #define ASI_CMP_XIR_STEERING 0x030 | |
| 201 | #define ASI_CMP_TICK_ENABLE 0x038 | |
| 202 | #define ASI_CMP_CORE_RUNNING_RW 0x050 | |
| 203 | #define ASI_CMP_CORE_RUNNING_STATUS 0x058 | |
| 204 | #define ASI_CMP_CORE_RUNNING_W1S 0x060 | |
| 205 | #define ASI_CMP_CORE_RUNNING_W1C 0x068 | |
| 206 | ||
| 207 | #define ASI_DIAG 0x42 | |
| 208 | #define ASI_SPARC_BIST_CONTROL 0x000 | |
| 209 | #define ASI_INST_MASK 0x008 | |
| 210 | #define ASI_LSU_DIAG 0x010 | |
| 211 | ||
| 212 | #define ASI_ERROR_INJECT 0x43 | |
| 213 | #define ASI_SELF_TIMED_MARGIN 0x44 | |
| 214 | #define ASI_IFU_CONTROL 0x44 | |
| 215 | #define ASI_IFU_CONTROL_VAL 0x090 | |
| 216 | #define ASI_LSU_CONTROL 0x45 | |
| 217 | #define ASI_DC_DATA ASI_DCACHE_DATA | |
| 218 | #define ASI_DCACHE_DATA 0x46 | |
| 219 | #define ASI_DC_TAG ASI_DCACHE_TAG | |
| 220 | #define ASI_DCACHE_TAG 0x47 | |
| 221 | ||
| 222 | #define ASI_IRF_ECC_REG 0x48 | |
| 223 | #define ASI_FRF_ECC_REG 0x49 | |
| 224 | #define ASI_STB_ACCESS 0x4a | |
| 225 | ||
| 226 | #define ASI_SPARC_ERROR_EN_REG 0x4b | |
| 227 | #define ASI_ESTATE_ERROR_EN_REG ASI_SPARC_ERROR_EN_REG | |
| 228 | #define ASI_SPARC_ERROR_STATUS_REG 0x4c | |
| 229 | #define ASI_AFSR ASI_SPARC_ERROR_STATUS_REG | |
| 230 | #define ASI_ASYNC_FAULT_STATUS ASI_SPARC_ERROR_STATUS_REG | |
| 231 | #define ASI_SPARC_ERROR_ADDRESS_REG 0x4d | |
| 232 | #define ASI_AFAR ASI_SPARC_ERROR_ADDRESS_REG | |
| 233 | #define ASI_ASYNC_FAULT_ADDR ASI_SPARC_ERROR_ADDRESS_REG | |
| 234 | ||
| 235 | #define ASI_SPARC_PWR_MGMT 0x4e | |
| 236 | #define ASI_HYP_SCRATCHPAD 0x4f | |
| 237 | #define ASI_HYP_SCRATCHPAD_0 0x000 | |
| 238 | #define ASI_HYP_SCRATCHPAD_1 0x008 | |
| 239 | #define ASI_HYP_SCRATCHPAD_2 0x010 | |
| 240 | #define ASI_HYP_SCRATCHPAD_3 0x018 | |
| 241 | #define ASI_HYP_SCRATCHPAD_4 0x020 | |
| 242 | #define ASI_HYP_SCRATCHPAD_5 0x028 | |
| 243 | #define ASI_HYP_SCRATCHPAD_6 0x030 | |
| 244 | #define ASI_HYP_SCRATCHPAD_7 0x038 | |
| 245 | ||
| 246 | #define ASI_IMMU 0x50 /* Legacy name */ | |
| 247 | #define ASI_IMMU_TAG_REG 0x50 | |
| 248 | #define ASI_IMMU_TAG_TARGET_VAL 0x000 | |
| 249 | #define ASI_IMMU_SFSR_VAL 0x018 | |
| 250 | #define ASI_IMMU_TAG_ACCESS_VAL 0x030 | |
| 251 | #define ASI_MMU_REAL_RANGE 0x52 | |
| 252 | #define ASI_MMU_REAL_RANGE_0 0x108 | |
| 253 | #define ASI_MMU_REAL_RANGE_1 0x110 | |
| 254 | #define ASI_MMU_REAL_RANGE_2 0x118 | |
| 255 | #define ASI_MMU_REAL_RANGE_3 0x120 | |
| 256 | #define ASI_MMU_PHYSICAL_OFFSET 0x52 | |
| 257 | #define ASI_MMU_PHYSICAL_OFFSET_0 0x208 | |
| 258 | #define ASI_MMU_PHYSICAL_OFFSET_1 0x210 | |
| 259 | #define ASI_MMU_PHYSICAL_OFFSET_2 0x218 | |
| 260 | #define ASI_MMU_PHYSICAL_OFFSET_3 0x220 | |
| 261 | #define ASI_ITLB_PROBE 0x53 | |
| 262 | #define ASI_ITLB_DATA_IN 0x54 | |
| 263 | #define ASI_ITLB_DATA_IN_0 0x000 | |
| 264 | #define ASI_ITLB_DATA_IN_1 0x400 | |
| 265 | #define ASI_ITLB_DATA_IN_2 0x800 | |
| 266 | #define ASI_ITLB_DATA_IN_3 0xc00 | |
| 267 | #define ASI_MMU_ZERO_CONTEXT_TSB_CONFIG 0x54 | |
| 268 | #define ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0 0x010 | |
| 269 | #define ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1 0x018 | |
| 270 | #define ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2 0x020 | |
| 271 | #define ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3 0x028 | |
| 272 | #define ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG 0x54 | |
| 273 | #define ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0 0x030 | |
| 274 | #define ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1 0x038 | |
| 275 | #define ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2 0x040 | |
| 276 | #define ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3 0x048 | |
| 277 | #define ASI_ITSB_PTR 0x54 | |
| 278 | #define ASI_ITSB_PTR_0 0x050 | |
| 279 | #define ASI_ITSB_PTR_1 0x058 | |
| 280 | #define ASI_ITSB_PTR_2 0x060 | |
| 281 | #define ASI_ITSB_PTR_3 0x068 | |
| 282 | #define ASI_DTSB_PTR 0x54 | |
| 283 | #define ASI_DTSB_PTR_0 0x070 | |
| 284 | #define ASI_DTSB_PTR_1 0x078 | |
| 285 | #define ASI_DTSB_PTR_2 0x080 | |
| 286 | #define ASI_DTSB_PTR_3 0x088 | |
| 287 | ||
| 288 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 | |
| 289 | #define ASI_ITLB_TAG_READ_REG 0x56 | |
| 290 | #define ASI_IMMU_DEMAP 0x57 | |
| 291 | #define ASI_IMMU_DEMAP_VAL 0x000 | |
| 292 | ||
| 293 | #define ASI_TSB_SEARCH_MODE_REG 0X58 | |
| 294 | #define ASI_TSB_SEARCH_MODE_ADDR 0X40 | |
| 295 | ||
| 296 | #define ASI_DMMU 0x58 | |
| 297 | #define ASI_DMMU_TAG_TARGET 0x000 | |
| 298 | #define ASI_DMMU_SFSR 0x018 | |
| 299 | #define ASI_DMMU_SFAR 0x020 | |
| 300 | #define ASI_DMMU_TAG_REG 0x58 | |
| 301 | #define ASI_DMMU_TAG_ACCESS_VAL 0x030 | |
| 302 | #define ASI_DMMU_VA_WATCHPOINT 0x58 | |
| 303 | #define ASI_DMMU_VA_WATCHPOINT_VAL 0x038 | |
| 304 | #define ASI_DMMU_PA_WATCHPOINT 0x58 | |
| 305 | #define ASI_DMMU_PA_WATCHPOINT_VAL 0x038 | |
| 306 | #define ASI_PARTITION_ID 0x58 | |
| 307 | #define ASI_PARTITION_ID_VAL 0x080 | |
| 308 | ||
| 309 | #define ASI_DTLB_DATA_IN 0x5c | |
| 310 | #define ASI_DTLB_DATA_IN_0 0x000 | |
| 311 | #define ASI_DTLB_DATA_IN_1 0x400 | |
| 312 | #define ASI_DTLB_DATA_IN_2 0x800 | |
| 313 | #define ASI_DTLB_DATA_IN_3 0xc00 | |
| 314 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d | |
| 315 | #define ASI_DTLB_TAG_READ_REG 0x5e | |
| 316 | #define ASI_DMMU_DEMAP 0x5f | |
| 317 | #define ASI_DMMU_DEMAP_VAL 0x000 | |
| 318 | ||
| 319 | #define ASI_INSTR 0x60 | |
| 320 | #define ASI_INSTRUCTION_BREAKPOINT 0x000 | |
| 321 | #define ASI_INSTRUCTION_BREAKPOINT_CONTROL 0x008 | |
| 322 | #define ASI_INSTR_VA_WATCHPOINT 0x58 | |
| 323 | #define ASI_INSTR_VA_WATCHPOINT_VAL 0x038 | |
| 324 | ||
| 325 | #define ASI_CMP_CORE_ID_BASE 0x63 | |
| 326 | #define ASI_CMP_CORE_INTR_ID 0x000 | |
| 327 | #define ASI_CMP_CORE_ID 0x010 | |
| 328 | #define ASI_CORE_ID 0x63 | |
| 329 | #define ASI_CORE_ID_VA 0x10 | |
| 330 | #define ASI_INTR_ID 0x63 | |
| 331 | #define ASI_INTR_ID_VA 0x00 | |
| 332 | ||
| 333 | ||
| 334 | #define ASI_IC_INSTR ASI_ICACHE_INSTR | |
| 335 | #define ASI_ICACHE_INSTR 0x66 | |
| 336 | #define ASI_IC_TAG ASI_ICACHE_TAG | |
| 337 | #define ASI_ICACHE_TAG 0x67 | |
| 338 | ||
| 339 | #define ASI_INTR_RECEIVE 0x72 | |
| 340 | #define ASI_INTR_W 0x73 | |
| 341 | #define ASI_INTR_R 0x74 | |
| 342 | #define ASI_SWVR_INTR_RECEIVE ASI_INTR_RECEIVE | |
| 343 | #define ASI_SWVR_UDB_INTR_W ASI_INTR_W | |
| 344 | #define ASI_SWVR_UDB_INTR_R ASI_INTR_R | |
| 345 | #define ASI_SWVR_INTR_W ASI_INTR_W | |
| 346 | #define ASI_SWVR_INTR_R ASI_INTR_R | |
| 347 | ||
| 348 | #define ASI_P ASI_PRIMARY | |
| 349 | #define ASI_PRIMARY 0x80 | |
| 350 | #define ASI_S ASI_SECONDARY | |
| 351 | #define ASI_SECONDARY 0x81 | |
| 352 | #define ASI_PNF ASI_PRIMARY_NO_FAULT | |
| 353 | #define ASI_PRIMARY_NO_FAULT 0x82 | |
| 354 | #define ASI_SNF ASI_SECONDARY_NO_FAULT | |
| 355 | #define ASI_SECONDARY_NO_FAULT 0x83 | |
| 356 | #define ASI_PL ASI_PRIMARY_LITTLE | |
| 357 | #define ASI_PRIMARY_LITTLE 0x88 | |
| 358 | #define ASI_SL ASI_SECONDARY_LITTLE | |
| 359 | #define ASI_SECONDARY_LITTLE 0x89 | |
| 360 | #define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE | |
| 361 | #define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a | |
| 362 | #define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE | |
| 363 | #define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b | |
| 364 | ||
| 365 | #define ASI_PST8_P ASI_PST8_PRIMARY | |
| 366 | #define ASI_PST8_PRIMARY 0xc0 | |
| 367 | #define ASI_PST8_S ASI_PST8_SECONDARY | |
| 368 | #define ASI_PST8_SECONDARY 0xc1 | |
| 369 | #define ASI_PST16_P ASI_PST16_PRIMARY | |
| 370 | #define ASI_PST16_PRIMARY 0xc2 | |
| 371 | #define ASI_PST16_S ASI_PST16_SECONDARY | |
| 372 | #define ASI_PST16_SECONDARY 0xc3 | |
| 373 | #define ASI_PST32_P ASI_PST32_PRIMARY | |
| 374 | #define ASI_PST32_PRIMARY 0xc4 | |
| 375 | #define ASI_PST32_S ASI_PST32_SECONDARY | |
| 376 | #define ASI_PST32_SECONDARY 0xc5 | |
| 377 | #define ASI_PST8_PL ASI_PST8_PRIMARY_LITTLE | |
| 378 | #define ASI_PST8_PRIMARY_LITTLE 0xc8 | |
| 379 | #define ASI_PST8_SL ASI_PST8_SECONDARY_LITTLE | |
| 380 | #define ASI_PST8_SECONDARY_LITTLE 0xc9 | |
| 381 | #define ASI_PST16_PL ASI_PST16_PRIMARY_LITTLE | |
| 382 | #define ASI_PST16_PRIMARY_LITTLE 0xca | |
| 383 | #define ASI_PST16_SL ASI_PST16_SECONDARY_LITTLE | |
| 384 | #define ASI_PST16_SECONDARY_LITTLE 0xcb | |
| 385 | #define ASI_PST32_PL ASI_PST32_PRIMARY_LITTLE | |
| 386 | #define ASI_PST32_PRIMARY_LITTLE 0xcc | |
| 387 | #define ASI_PST32_SL ASI_PST32_SECONDARY_LITTLE | |
| 388 | #define ASI_PST32_SECONDARY_LITTLE 0xcd | |
| 389 | #define ASI_FL8_P ASI_FL8_PRIMARY | |
| 390 | #define ASI_FL8_PRIMARY 0xd0 | |
| 391 | #define ASI_FL8_S ASI_FL8_SECONDARY | |
| 392 | #define ASI_FL8_SECONDARY 0xd1 | |
| 393 | #define ASI_FL16_P ASI_FL16_PRIMARY | |
| 394 | #define ASI_FL16_PRIMARY 0xd2 | |
| 395 | #define ASI_FL16_S ASI_FL16_SECONDARY | |
| 396 | #define ASI_FL16_SECONDARY 0xd3 | |
| 397 | #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE | |
| 398 | #define ASI_FL8_PRIMARY_LITTLE 0xd8 | |
| 399 | #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE | |
| 400 | #define ASI_FL8_SECONDARY_LITTLE 0xd9 | |
| 401 | #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE | |
| 402 | #define ASI_FL16_PRIMARY_LITTLE 0xda | |
| 403 | #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE | |
| 404 | #define ASI_FL16_SECONDARY_LITTLE 0xdb | |
| 405 | ||
| 406 | #define ASI_BLK_COMMIT_PRIMARY 0xe0 | |
| 407 | #define ASI_BLK_COMMIT_P ASI_BLK_COMMIT_PRIMARY | |
| 408 | #define ASI_COMMIT_P ASI_BLK_COMMIT_PRIMARY | |
| 409 | #define ASI_COMMIT_PRIMARY ASI_BLK_COMMIT_PRIMARY | |
| 410 | #define ASI_BLK_COMMIT_SECONDARY 0xe1 | |
| 411 | #define ASI_BLK_COMMIT_S ASI_BLK_COMMIT_SECONDARY | |
| 412 | #define ASI_COMMIT_S ASI_BLK_COMMIT_SECONDARY | |
| 413 | #define ASI_COMMIT_SECONDARY ASI_BLK_COMMIT_SECONDARY | |
| 414 | #define ASI_BLK_INIT_ST_QUAD_LDD_P 0xe2 | |
| 415 | #define ASI_BLK_INIT_ST_QUAD_LDD_S 0xe3 | |
| 416 | #define ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE 0xea | |
| 417 | #define ASI_BLK_INIT_ST_QUAD_LDD_S_LITTLE 0xeb | |
| 418 | #define ASI_BLK_P ASI_BLOCK_PRIMARY | |
| 419 | #define ASI_BLOCK_PRIMARY 0xf0 | |
| 420 | #define ASI_BLK_P ASI_BLOCK_PRIMARY | |
| 421 | #define ASI_BLK_S ASI_BLOCK_SECONDARY | |
| 422 | #define ASI_BLOCK_SECONDARY 0xf1 | |
| 423 | #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE | |
| 424 | #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 | |
| 425 | #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE | |
| 426 | #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 | |
| 427 | #define ASI_STB_ACCESS 0x4a | |
| 428 | ||
| 429 | #define ASI_DESR 0x4c | |
| 430 | #define ASI_DFESR 0x4c | |
| 431 | #define ASI_DSFSR 0x58 | |
| 432 | #define ASI_ISFSR 0x50 | |
| 433 | #define ASI_SFAR 0x58 | |
| 434 | #define ASI_CETER 0x4C | |
| 435 | #define ASI_CERER 0x4C | |
| 436 | #define ASI_ERR_INJ 0x43 | |
| 437 | #define ASI_TICK_ACCESS 0x5A | |
| 438 | #define ASI_SCRATCHPAD_ACCESS 0x59 | |
| 439 | #define ASI_TSA_ACCESS 0x5B | |
| 440 | #define ASI_IRF_ECC_REG 0x48 | |
| 441 | #define ASI_FRF_ECC_REG 0x49 | |
| 442 | #define DFESR_VA 0x8 | |
| 443 | #define SFSR_VA 0x18 | |
| 444 | #define SFAR_VA 0x20 | |
| 445 | #define CETER_VA 0x18 | |
| 446 | #define CERER_VA 0x10 | |
| 447 | ||
| 448 | #endif /* __ASI_S_H__ */ |