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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / include / boot_mcuctl_init_b4wmr.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: boot_mcuctl_init_b4wmr.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38mcuctl_init_b4wmr:
39
40#define DRAM_REFRESH_FREQ_DATA 0x0000000000000a28
41#define RAS2RAS_DIF_BANK_DELAY_DATA 0x0000000000000003
42#define RAS2RAS_SAME_BANK_DELAY_DATA 0x0000000000000013
43#define RAS2CAS_DELAY_DATA 0x0000000000000004
44#define INTREAD2PCHG_DELAY_DATA 0x0000000000000003
45#define ACT2PCHG_DELAY_DATA 0x000000000000000f
46#define PCHG_CMD_PERIOD_DATA 0x0000000000000004
47#define WRI_RECOVERY_PERIOD_DATA 0x0000000000000005
48#define ARFSH2ACT_PERIOD_DATA 0x0000000000000019
49#define FOUR_ACTIVE_WINDOW_DATA 0x000000000000000d
50#define INTWRI2READ_DELAY_DATA 0x0000000000000003
51
52! %l6 contains the base address of CSR space in MCU0
53! %g0-%g3 contains the offset for MCU0-MCU3.
54
55 setx 0x8400000000, %l7, %l6
56 sethi %hi(0x00001000), %g1
57 sethi %hi(0x00002000), %g2
58 sethi %hi(0x00003000), %g3
59
60mcuctl_init_b4wmr__DRAM_REFRESH_FREQ:
61! Set DRAM Refresh Freq. Reg.
62 add %l6, 0x020, %l0
63 mov DRAM_REFRESH_FREQ_DATA ,%l3
64
65#ifndef DTM_ENABLED
66 stx %l3, [%l0+%g0]
67 stx %l3, [%l0+%g1]
68 stx %l3, [%l0+%g2]
69 stx %l3, [%l0+%g3]
70#endif
71
72! Set RAS to RAS Diff Bank Delay Reg.
73mcuctl_init_b4wmr__RAS2RAS_DIF_BANK_DELAY:
74 add %l6, 0x080, %l0
75 mov RAS2RAS_DIF_BANK_DELAY_DATA ,%l3
76#ifdef BANK01
77 stx %l3, [%l0+%g0]
78#endif
79
80#ifdef BANK23
81 stx %l3, [%l0+%g1]
82#endif
83
84#ifdef BANK45
85 stx %l3, [%l0+%g2]
86#endif
87
88#ifdef BANK67
89 stx %l3, [%l0+%g3]
90#endif
91
92! Set RAS to RAS Same Bank Delay Reg.
93mcuctl_init_b4wmr__RAS2RAS_SAME_BANK_DELAY:
94 add %l6, 0x088, %l0
95 mov RAS2RAS_SAME_BANK_DELAY_DATA ,%l3
96#ifdef BANK01
97 stx %l3, [%l0+%g0]
98#endif
99#ifdef BANK23
100 stx %l3, [%l0+%g1]
101#endif
102#ifdef BANK45
103 stx %l3, [%l0+%g2]
104#endif
105#ifdef BANK67
106 stx %l3, [%l0+%g3]
107#endif
108
109! Set RAS to CAS Delay Reg.
110mcuctl_init_b4wmr__RAS2CAS_DELAY:
111 add %l6, 0x090, %l0
112 mov RAS2CAS_DELAY_DATA ,%l3
113#ifdef BANK01
114 stx %l3, [%l0+%g0]
115#endif
116#ifdef BANK23
117 stx %l3, [%l0+%g1]
118#endif
119#ifdef BANK45
120 stx %l3, [%l0+%g2]
121#endif
122#ifdef BANK67
123 stx %l3, [%l0+%g3]
124#endif
125
126! Set Int. Read to Precharge Delay Reg.
127mcuctl_init_b4wmr__INTREAD2PCHG_DELAY:
128 add %l6, 0x0a8, %l0
129 mov INTREAD2PCHG_DELAY_DATA ,%l3
130#ifdef BANK01
131 stx %l3, [%l0+%g0]
132#endif
133#ifdef BANK23
134 stx %l3, [%l0+%g1]
135#endif
136#ifdef BANK45
137 stx %l3, [%l0+%g2]
138#endif
139#ifdef BANK67
140 stx %l3, [%l0+%g3]
141#endif
142
143! Set Active to Precharge Delay Reg.
144mcuctl_init_b4wmr__ACT2PCHG_DELAY:
145 add %l6, 0x0b0, %l0
146 mov ACT2PCHG_DELAY_DATA ,%l3
147#ifdef BANK01
148 stx %l3, [%l0+%g0]
149#endif
150#ifdef BANK23
151 stx %l3, [%l0+%g1]
152#endif
153#ifdef BANK45
154 stx %l3, [%l0+%g2]
155#endif
156#ifdef BANK67
157 stx %l3, [%l0+%g3]
158#endif
159
160! Set Precharge Cmd Period Reg.
161mcuctl_init_b4wmr__PCHG_CMD_PERIOD:
162 add %l6, 0x0b8, %l0
163 mov PCHG_CMD_PERIOD_DATA ,%l3
164#ifdef BANK01
165 stx %l3, [%l0+%g0]
166#endif
167#ifdef BANK23
168 stx %l3, [%l0+%g1]
169#endif
170#ifdef BANK45
171 stx %l3, [%l0+%g2]
172#endif
173#ifdef BANK67
174 stx %l3, [%l0+%g3]
175#endif
176
177! Set Write Recovery Period Reg.
178mcuctl_init_b4wmr__WRI_RECOVERY_PERIOD:
179 add %l6, 0x0c0, %l0
180 mov WRI_RECOVERY_PERIOD_DATA ,%l3
181#ifdef BANK01
182 stx %l3, [%l0+%g0]
183#endif
184#ifdef BANK23
185 stx %l3, [%l0+%g1]
186#endif
187#ifdef BANK45
188 stx %l3, [%l0+%g2]
189#endif
190#ifdef BANK67
191 stx %l3, [%l0+%g3]
192#endif
193
194! Set Auto RFSH to Active Period Reg.
195mcuctl_init_b4wmr__ARFSH2ACT_PERIOD:
196 add %l6, 0x0c8, %l0
197 mov ARFSH2ACT_PERIOD_DATA ,%l3
198#ifdef BANK01
199 stx %l3, [%l0+%g0]
200#endif
201#ifdef BANK23
202 stx %l3, [%l0+%g1]
203#endif
204#ifdef BANK45
205 stx %l3, [%l0+%g2]
206#endif
207#ifdef BANK67
208 stx %l3, [%l0+%g3]
209#endif
210
211! Set Four Active Window Reg.
212mcuctl_init_b4wmr__FOUR_ACTIVE_WINDOW:
213 add %l6, 0x0d8, %l0
214 mov FOUR_ACTIVE_WINDOW_DATA ,%l3
215#ifdef BANK01
216 stx %l3, [%l0+%g0]
217#endif
218#ifdef BANK23
219 stx %l3, [%l0+%g1]
220#endif
221#ifdef BANK45
222 stx %l3, [%l0+%g2]
223#endif
224#ifdef BANK67
225 stx %l3, [%l0+%g3]
226#endif
227
228! Set Int. Write to Read Delay Reg.
229mcuctl_init_b4wmr__INTWRI2READ_DELAY:
230 add %l6, 0x0e0, %l0
231 mov INTWRI2READ_DELAY_DATA ,%l3
232#ifdef BANK01
233 stx %l3, [%l0+%g0]
234#endif
235#ifdef BANK23
236 stx %l3, [%l0+%g1]
237#endif
238#ifdef BANK45
239 stx %l3, [%l0+%g2]
240#endif
241#ifdef BANK67
242 stx %l3, [%l0+%g3]
243#endif
244
245!!moved code from hboot_mcu
246
247#ifdef DTM_ENABLED
248 setx 0x8400000000, %l7, %l6
249 sethi %hi(0x00001000), %g1
250 sethi %hi(0x00002000), %g2
251 sethi %hi(0x00003000), %g3
252
253dimm_init_reg_to_3:
254 add %l6, 0x1a0, %l0 ! DRAM_DIMM_INIT_REG
255 mov 3, %l3 ! Set CKE enable to 1 to assert CKE high to the DIMMs
256#ifdef BANK01
257 stx %l3, [%l0+%g0] ! (per conversation with Rashid)
258#endif
259#ifdef BANK23
260 stx %l3, [%l0+%g1]
261#endif
262#ifdef BANK45
263 stx %l3, [%l0+%g2]
264#endif
265#ifdef BANK67
266 stx %l3, [%l0+%g3]
267#endif
268
269! Memory Density Type : 256 Mb, 512 Mb, 1 Gb, 2 Gb
270#if defined(DIMM_SIZE_1G)
271mcuctl_init_b4wmr__DIMM_SIZE_1G:
272 add %l6, 0x008, %l0 ! DRAM_RAS_ADDR_WIDTH_REG
273 mov 0xe, %l3
274#ifdef BANK01
275 stx %l3, [%l0+%g0]
276#endif
277#ifdef BANK23
278 stx %l3, [%l0+%g1]
279#endif
280#ifdef BANK45
281 stx %l3, [%l0+%g2]
282#endif
283#ifdef BANK67
284 stx %l3, [%l0+%g3]
285#endif
286#else
287#if defined(DIMM_SIZE_512)
288mcuctl_init_b4wmr__DIMM_SIZE_512:
289 add %l6, 0x008, %l0
290 mov 0xe, %l3
291#ifdef BANK01
292 stx %l3, [%l0+%g0]
293#endif
294#ifdef BANK23
295 stx %l3, [%l0+%g1]
296#endif
297#ifdef BANK45
298 stx %l3, [%l0+%g2]
299#endif
300#ifdef BANK67
301 stx %l3, [%l0+%g3]
302#endif
303
304 add %l6, 0x128, %l0 ! 8_BANK_REG
305 mov 0x0, %l3
306#ifdef BANK01
307 stx %l3, [%l0+%g0]
308#endif
309#ifdef BANK23
310 stx %l3, [%l0+%g1]
311#endif
312#ifdef BANK45
313 stx %l3, [%l0+%g2]
314#endif
315#ifdef BANK67
316 stx %l3, [%l0+%g3]
317#endif
318#else
319#if defined(DIMM_SIZE_256)
320mcuctl_init_b4wmr__DIMM_SIZE_256:
321 add %l6, 0x008, %l0
322 mov 0xd, %l3
323#ifdef BANK01
324 stx %l3, [%l0+%g0]
325#endif
326#ifdef BANK23
327 stx %l3, [%l0+%g1]
328#endif
329#ifdef BANK45
330 stx %l3, [%l0+%g2]
331#endif
332#ifdef BANK67
333 stx %l3, [%l0+%g3]
334#endif
335
336 add %l6, 0x128, %l0
337 mov 0x0, %l3
338#ifdef BANK01
339 stx %l3, [%l0+%g0]
340#endif
341#ifdef BANK23
342 stx %l3, [%l0+%g1]
343#endif
344#ifdef BANK45
345 stx %l3, [%l0+%g2]
346#endif
347#ifdef BANK67
348 stx %l3, [%l0+%g3]
349#endif
350#else
351!! use default = 2G b
352#endif
353#endif
354#endif
355
356! MEMORY CONFIGURATION SETUP
357
358!! Default !!!
359#define CHNL_TYPE 0
360#define RANK_ADDR 0
361#define RANK 0
362#define NUM_DIMMS 1
363#define AMB_ID 0
364#define CAS_LATENCY 3
365!!
366
367#ifdef SNG_CHANNEL
368#define CHNL_TYPE 1
369#endif
370#ifdef DUAL_CHANNEL
371#define CHNL_TYPE 0
372#endif
373
374#ifdef RANK_LOW
375#define RANK_ADDR 1
376#endif
377
378#ifdef FBDIMMS_1
379#define NUM_DIMMS 1
380#define AMB_ID 0
381#endif
382#ifdef FBDIMMS_2
383#define NUM_DIMMS 2
384#define AMB_ID 8
385#endif
386#ifdef FBDIMMS_4
387#define NUM_DIMMS 4
388#define AMB_ID 24
389#endif
390#ifdef FBDIMMS_6
391#define NUM_DIMMS 6
392#define AMB_ID 40
393#endif
394#ifdef FBDIMMS_8
395#define NUM_DIMMS 0
396#define AMB_ID 56
397#endif
398
399#ifdef STACK_DIMM
400#define RANK 1
401#endif
402
403#ifdef VARY_CAS_LATENCY
404#define CAS_LATENCY VARY_CAS_LATENCY
405#endif
406
407#if defined(SNG_CHANNEL)
408mcuctl_init_b4wmr__SNG_CHANNEL:
409 add %l6, 0x148, %l0 ! SINGLE_CHANNEL_MODE_REG
410 mov CHNL_TYPE, %l3
411#ifdef BANK01
412 stx %l3, [%l0+%g0]
413#endif
414#ifdef BANK23
415 stx %l3, [%l0+%g1]
416#endif
417#ifdef BANK45
418 stx %l3, [%l0+%g2]
419#endif
420#ifdef BANK67
421 stx %l3, [%l0+%g3]
422#endif
423#endif
424
425!! HIGH ADDR / SINGLE RANK
426#if !defined(RANK_LOW) && !defined(STACK_DIMM)
427mcuctl_init_b4wmr__RANK_HIGH__SINGLE_RANK:
428 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
429 mov RANK_ADDR, %l3
430#ifdef BANK01
431 stx %l3, [%l0+%g0]
432#endif
433#ifdef BANK23
434 stx %l3, [%l0+%g1]
435#endif
436#ifdef BANK45
437 stx %l3, [%l0+%g2]
438#endif
439#ifdef BANK67
440 stx %l3, [%l0+%g3]
441#endif
442
443 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
444 mov RANK, %l3
445#ifdef BANK01
446 stx %l3, [%l0+%g0]
447#endif
448#ifdef BANK23
449 stx %l3, [%l0+%g1]
450#endif
451#ifdef BANK45
452 stx %l3, [%l0+%g2]
453#endif
454#ifdef BANK67
455 stx %l3, [%l0+%g3]
456#endif
457
458#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_8)
459 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
460 mov NUM_DIMMS, %l3
461#ifdef BANK01
462 stx %l3, [%l0+%g0]
463#endif
464#ifdef BANK23
465 stx %l3, [%l0+%g1]
466#endif
467#ifdef BANK45
468 stx %l3, [%l0+%g2]
469#endif
470#ifdef BANK67
471 stx %l3, [%l0+%g3]
472#endif
473
474 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
475 mov AMB_ID, %l3
476#ifdef BANK01
477 stx %l3, [%l0+%g0]
478#endif
479#ifdef BANK23
480 stx %l3, [%l0+%g1]
481#endif
482#ifdef BANK45
483 stx %l3, [%l0+%g2]
484#endif
485#ifdef BANK67
486 stx %l3, [%l0+%g3]
487#endif
488#endif
489#endif
490
491!! HIGH ADDR / DUAL RANK
492#if !defined(RANK_LOW) && defined(STACK_DIMM)
493mcuctl_init_b4wmr__RANK_HIGH__STACK_DIMM:
494 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
495 mov RANK_ADDR, %l3
496#ifdef BANK01
497 stx %l3, [%l0+%g0]
498#endif
499#ifdef BANK23
500 stx %l3, [%l0+%g1]
501#endif
502#ifdef BANK45
503 stx %l3, [%l0+%g2]
504#endif
505#ifdef BANK67
506 stx %l3, [%l0+%g3]
507#endif
508
509 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
510 mov RANK, %l3
511#ifdef BANK01
512 stx %l3, [%l0+%g0]
513#endif
514#ifdef BANK23
515 stx %l3, [%l0+%g1]
516#endif
517#ifdef BANK45
518 stx %l3, [%l0+%g2]
519#endif
520#ifdef BANK67
521 stx %l3, [%l0+%g3]
522#endif
523
524#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_8)
525 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
526 mov NUM_DIMMS, %l3
527#ifdef BANK01
528 stx %l3, [%l0+%g0]
529#endif
530#ifdef BANK23
531 stx %l3, [%l0+%g1]
532#endif
533#ifdef BANK45
534 stx %l3, [%l0+%g2]
535#endif
536#ifdef BANK67
537 stx %l3, [%l0+%g3]
538#endif
539
540 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
541 mov AMB_ID, %l3
542#ifdef BANK01
543 stx %l3, [%l0+%g0]
544#endif
545#ifdef BANK23
546 stx %l3, [%l0+%g1]
547#endif
548#ifdef BANK45
549 stx %l3, [%l0+%g2]
550#endif
551#ifdef BANK67
552 stx %l3, [%l0+%g3]
553#endif
554#endif
555#endif
556
557!! LOW ADDR / SINGLE RANK
558#if defined(RANK_LOW) && !defined(STACK_DIMM)
559mcuctl_init_b4wmr__RANK_LOW__SINGLE_RANK:
560 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
561 mov RANK_ADDR, %l3
562#ifdef BANK01
563 stx %l3, [%l0+%g0]
564#endif
565#ifdef BANK23
566 stx %l3, [%l0+%g1]
567#endif
568#ifdef BANK45
569 stx %l3, [%l0+%g2]
570#endif
571#ifdef BANK67
572 stx %l3, [%l0+%g3]
573#endif
574
575 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
576 mov RANK, %l3
577#ifdef BANK01
578 stx %l3, [%l0+%g0]
579#endif
580#ifdef BANK23
581 stx %l3, [%l0+%g1]
582#endif
583#ifdef BANK45
584 stx %l3, [%l0+%g2]
585#endif
586#ifdef BANK67
587 stx %l3, [%l0+%g3]
588#endif
589
590#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_6) || defined(FBDIMMS_8)
591 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
592 mov NUM_DIMMS, %l3
593#ifdef BANK01
594 stx %l3, [%l0+%g0]
595#endif
596#ifdef BANK23
597 stx %l3, [%l0+%g1]
598#endif
599#ifdef BANK45
600 stx %l3, [%l0+%g2]
601#endif
602#ifdef BANK67
603 stx %l3, [%l0+%g3]
604#endif
605
606 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
607 mov AMB_ID, %l3
608#ifdef BANK01
609 stx %l3, [%l0+%g0]
610#endif
611#ifdef BANK23
612 stx %l3, [%l0+%g1]
613#endif
614#ifdef BANK45
615 stx %l3, [%l0+%g2]
616#endif
617#ifdef BANK67
618 stx %l3, [%l0+%g3]
619#endif
620
621#endif
622#endif
623
624!! LOW ADDR / DUAL RANK
625#if defined(RANK_LOW) && defined(STACK_DIMM)
626mcuctl_init_b4wmr__RANK_LOW__STACK_DIMM:
627 add %l6, 0x140, %l0 ! DRAM_SEL_LO_ADDR_BITS_REG
628 mov RANK_ADDR, %l3
629#ifdef BANK01
630 stx %l3, [%l0+%g0]
631#endif
632#ifdef BANK23
633 stx %l3, [%l0+%g1]
634#endif
635#ifdef BANK45
636 stx %l3, [%l0+%g2]
637#endif
638#ifdef BANK67
639 stx %l3, [%l0+%g3]
640#endif
641
642 add %l6, 0x108, %l0 ! DRAM_DIMM_STACK_REG
643 mov RANK, %l3
644#ifdef BANK01
645 stx %l3, [%l0+%g0]
646#endif
647#ifdef BANK23
648 stx %l3, [%l0+%g1]
649#endif
650#ifdef BANK45
651 stx %l3, [%l0+%g2]
652#endif
653#ifdef BANK67
654 stx %l3, [%l0+%g3]
655#endif
656
657#if defined(FBDIMMS_1) || defined(FBDIMMS_2) || defined(FBDIMMS_4) || defined(FBDIMMS_6) || defined(FBDIMMS_8)
658 add %l6, 0x218, %l0 ! DRAM_DIMM_PRESENT_REG
659 mov NUM_DIMMS, %l3
660#ifdef BANK01
661 stx %l3, [%l0+%g0]
662#endif
663#ifdef BANK23
664 stx %l3, [%l0+%g1]
665#endif
666#ifdef BANK45
667 stx %l3, [%l0+%g2]
668#endif
669#ifdef BANK67
670 stx %l3, [%l0+%g3]
671#endif
672
673 add %l6, 0x800, %l0 ! FBD_CHANNEL_STATE_REG
674 mov AMB_ID, %l3
675#ifdef BANK01
676 stx %l3, [%l0+%g0]
677#endif
678#ifdef BANK23
679 stx %l3, [%l0+%g1]
680#endif
681#ifdef BANK45
682 stx %l3, [%l0+%g2]
683#endif
684#ifdef BANK67
685 stx %l3, [%l0+%g3]
686#endif
687
688#endif
689#endif
690
691#ifdef DRAM_SCRUB
692! DRAM_SCRUB_ENABLE
693mcuctl_init_b4wmr__DRAM_SCRUB_ENABLE:
694 add %l6, 0x040, %l0
695 mov 0x1, %l3
696#ifdef BANK01
697 stx %l3, [%l0+%g0]
698#endif
699#ifdef BANK23
700 stx %l3, [%l0+%g1]
701#endif
702#ifdef BANK45
703 stx %l3, [%l0+%g2]
704#endif
705#ifdef BANK67
706 stx %l3, [%l0+%g3]
707#endif
708
709! DRAM_SCRUB_FREQ_REG
710mcuctl_init_b4wmr__DRAM_SCRUB_FREQ:
711 add %l6, 0x018, %l0
712 mov 0x10, %l3
713#ifdef BANK01
714 stx %l3, [%l0+%g0]
715#endif
716#ifdef BANK23
717 stx %l3, [%l0+%g1]
718#endif
719#ifdef BANK45
720 stx %l3, [%l0+%g2]
721#endif
722#ifdef BANK67
723 stx %l3, [%l0+%g3]
724#endif
725#endif
726
727!!! Program same values as in mcu_mem_config.v
728
729#ifdef DDR2_533
730mcuctl_init_b4wmr__ddr2_533_ras_reg_init:
731 add %l6, 0x0b0, %l0 ! DRAM_TRAS_REG
732 mov 0x0c,%l3
733#ifdef BANK01
734 stx %l3, [%l0+%g0]
735#endif
736#ifdef BANK23
737 stx %l3, [%l0+%g1]
738#endif
739#ifdef BANK45
740 stx %l3, [%l0+%g2]
741#endif
742#ifdef BANK67
743 stx %l3, [%l0+%g3]
744#endif
745
746!ddr2_533_rp_reg_init:
747! add %l6, 0x0b8, %l0 ! DRAM_TRP_REG - same as POR value
748! mov 0x03,%l3
749! stx %l3, [%l0+%g0]
750! stx %l3, [%l0+%g1]
751! stx %l3, [%l0+%g2]
752! stx %l3, [%l0+%g3]
753
754!ddr2_533_rtp_reg_init:
755! add %l6, 0x0a8, %l0 ! DRAM_TRTP_REG - same as POR value
756! mov 0x02,%l3
757! stx %l3, [%l0+%g0]
758! stx %l3, [%l0+%g1]
759! stx %l3, [%l0+%g2]
760! stx %l3, [%l0+%g3]
761
762mcuctl_init_b4wmr__ddr2_533_rc_reg_init:
763 add %l6, 0x088, %l0 ! DRAM_TRC_REG
764#if defined(SNG_CHANNEL)
765 mov 0x011,%l3
766#else
767 mov 0x00f,%l3
768#endif
769#ifdef BANK01
770 stx %l3, [%l0+%g0]
771#endif
772#ifdef BANK23
773 stx %l3, [%l0+%g1]
774#endif
775#ifdef BANK45
776 stx %l3, [%l0+%g2]
777#endif
778#ifdef BANK67
779 stx %l3, [%l0+%g3]
780#endif
781
782!ddr2_533_rcd_reg_init:
783! add %l6, 0x090, %l0 ! DRAM_TRCD_REG - same as POR value
784! mov 0x03,%l3
785! stx %l3, [%l0+%g0]
786! stx %l3, [%l0+%g1]
787! stx %l3, [%l0+%g2]
788! stx %l3, [%l0+%g3]
789
790mcuctl_init_b4wmr__ddr2_533_rfc_reg_init:
791 add %l6, 0x0c8, %l0 ! DRAM_TRFC_REG
792 mov 0x014,%l3
793#ifdef BANK01
794 stx %l3, [%l0+%g0]
795#endif
796#ifdef BANK23
797 stx %l3, [%l0+%g1]
798#endif
799#ifdef BANK45
800 stx %l3, [%l0+%g2]
801#endif
802#ifdef BANK67
803 stx %l3, [%l0+%g3]
804#endif
805
806mcuctl_init_b4wmr__ddr2_533_wr_reg_init:
807 add %l6, 0x0c0, %l0 ! DRAM_TWR_REG
808 mov 0x04,%l3
809#ifdef BANK01
810 stx %l3, [%l0+%g0]
811#endif
812#ifdef BANK23
813 stx %l3, [%l0+%g1]
814#endif
815#ifdef BANK45
816 stx %l3, [%l0+%g2]
817#endif
818#ifdef BANK67
819 stx %l3, [%l0+%g3]
820#endif
821
822mcuctl_init_b4wmr__ddr2_533_iwtr_reg_init:
823 add %l6, 0x0e0, %l0 ! DRAM_TIWTR_REG
824 mov 0x03,%l3
825#ifdef BANK01
826 stx %l3, [%l0+%g0]
827#endif
828#ifdef BANK23
829 stx %l3, [%l0+%g1]
830#endif
831#ifdef BANK45
832 stx %l3, [%l0+%g2]
833#endif
834#ifdef BANK67
835 stx %l3, [%l0+%g3]
836#endif
837
838mcuctl_init_b4wmr__ddr2_533_rtw_reg_init:
839 add %l6, 0x0a0, %l0 ! DRAM_TRTW_REG
840#if defined(SNG_CHANNEL)
841 mov 0x0,%l3
842#else
843 mov 0x0,%l3
844#endif
845#ifdef BANK01
846 stx %l3, [%l0+%g0]
847#endif
848#ifdef BANK23
849 stx %l3, [%l0+%g1]
850#endif
851#ifdef BANK45
852 stx %l3, [%l0+%g2]
853#endif
854#ifdef BANK67
855 stx %l3, [%l0+%g3]
856#endif
857
858mcuctl_init_b4wmr__ddr2_533_rrd_reg_init:
859 add %l6, 0x080, %l0 ! DRAM_TRRD_REG
860#if defined(SNG_CHANNEL)
861 mov 5,%l3
862#else
863 mov 3,%l3
864#endif
865#ifdef BANK01
866 stx %l3, [%l0+%g0]
867#endif
868#ifdef BANK23
869 stx %l3, [%l0+%g1]
870#endif
871#ifdef BANK45
872 stx %l3, [%l0+%g2]
873#endif
874#ifdef BANK67
875 stx %l3, [%l0+%g3]
876#endif
877
878mcuctl_init_b4wmr__ddr2_533_faw_reg_init:
879 add %l6, 0x0d8, %l0 ! missing from mcu_defines.h
880 mov 0x0a,%l3
881#ifdef BANK01
882 stx %l3, [%l0+%g0]
883#endif
884#ifdef BANK23
885 stx %l3, [%l0+%g1]
886#endif
887#ifdef BANK45
888 stx %l3, [%l0+%g2]
889#endif
890#ifdef BANK67
891 stx %l3, [%l0+%g3]
892#endif
893
894#else // end of #ifdef DDR2_533
895
896mcuctl_init_b4wmr__ddr2_667_ras_reg_init:
897 add %l6, 0x0b0, %l0 ! DRAM_TRAS_REG
898 mov 0x0f,%l3
899#ifdef BANK01
900 stx %l3, [%l0+%g0]
901#endif
902#ifdef BANK23
903 stx %l3, [%l0+%g1]
904#endif
905#ifdef BANK45
906 stx %l3, [%l0+%g2]
907#endif
908#ifdef BANK67
909 stx %l3, [%l0+%g3]
910#endif
911
912mcuctl_init_b4wmr__ddr2_667_rp_reg_init:
913 add %l6, 0x0b8, %l0 ! DRAM_TRP_REG
914 mov 0x04,%l3
915#ifdef BANK01
916 stx %l3, [%l0+%g0]
917#endif
918#ifdef BANK23
919 stx %l3, [%l0+%g1]
920#endif
921#ifdef BANK45
922 stx %l3, [%l0+%g2]
923#endif
924#ifdef BANK67
925 stx %l3, [%l0+%g3]
926#endif
927
928mcuctl_init_b4wmr__ddr2_667_rtp_reg_init:
929 add %l6, 0x0a8, %l0 ! DRAM_TRTP_REG
930 mov 0x03,%l3
931#ifdef BANK01
932 stx %l3, [%l0+%g0]
933#endif
934#ifdef BANK23
935 stx %l3, [%l0+%g1]
936#endif
937#ifdef BANK45
938 stx %l3, [%l0+%g2]
939#endif
940#ifdef BANK67
941 stx %l3, [%l0+%g3]
942#endif
943
944mcuctl_init_b4wmr__ddr2_667_ref_reg_init:
945 add %l6, 0x020, %l0 ! DRAM_REFRESH_FREQ_REG
946 mov 0xa28,%l3
947
948#ifndef DTM_ENABLED
949 stx %l3, [%l0+%g0]
950 stx %l3, [%l0+%g1]
951 stx %l3, [%l0+%g2]
952 stx %l3, [%l0+%g3]
953#endif
954
955mcuctl_init_b4wmr__ddr2_667_rc_reg_init:
956 add %l6, 0x088, %l0 ! DRAM_TRC_REG
957#if defined(SNG_CHANNEL)
958 mov 0x015,%l3
959#else
960 mov 0x013,%l3
961#endif
962#ifdef BANK01
963 stx %l3, [%l0+%g0]
964#endif
965#ifdef BANK23
966 stx %l3, [%l0+%g1]
967#endif
968#ifdef BANK45
969 stx %l3, [%l0+%g2]
970#endif
971#ifdef BANK67
972 stx %l3, [%l0+%g3]
973#endif
974
975mcuctl_init_b4wmr__ddr2_667_rcd_reg_init:
976 add %l6, 0x090, %l0 ! DRAM_TRCD_REG
977 mov 0x04,%l3
978#ifdef BANK01
979 stx %l3, [%l0+%g0]
980#endif
981#ifdef BANK23
982 stx %l3, [%l0+%g1]
983#endif
984#ifdef BANK45
985 stx %l3, [%l0+%g2]
986#endif
987#ifdef BANK67
988 stx %l3, [%l0+%g3]
989#endif
990
991mcuctl_init_b4wmr__ddr2_667_rfc_reg_init:
992 add %l6, 0x0c8, %l0 ! DRAM_TRFC_REG
993 mov 0x019,%l3
994#ifdef BANK01
995 stx %l3, [%l0+%g0]
996#endif
997#ifdef BANK23
998 stx %l3, [%l0+%g1]
999#endif
1000#ifdef BANK45
1001 stx %l3, [%l0+%g2]
1002#endif
1003#ifdef BANK67
1004 stx %l3, [%l0+%g3]
1005#endif
1006
1007mcuctl_init_b4wmr__ddr2_667_wr_reg_init:
1008 add %l6, 0x0c0, %l0 ! DRAM_TWR_REG
1009 mov 0x05,%l3
1010#ifdef BANK01
1011 stx %l3, [%l0+%g0]
1012#endif
1013#ifdef BANK23
1014 stx %l3, [%l0+%g1]
1015#endif
1016#ifdef BANK45
1017 stx %l3, [%l0+%g2]
1018#endif
1019#ifdef BANK67
1020 stx %l3, [%l0+%g3]
1021#endif
1022
1023mcuctl_init_b4wmr__ddr2_667_iwtr_reg_init:
1024 add %l6, 0x0e0, %l0 ! DRAM_TIWTR_REG
1025 mov 0x03,%l3
1026#ifdef BANK01
1027 stx %l3, [%l0+%g0]
1028#endif
1029#ifdef BANK23
1030 stx %l3, [%l0+%g1]
1031#endif
1032#ifdef BANK45
1033 stx %l3, [%l0+%g2]
1034#endif
1035#ifdef BANK67
1036 stx %l3, [%l0+%g3]
1037#endif
1038
1039mcuctl_init_b4wmr__ddr2_667_rtw_reg_init:
1040 add %l6, 0x0a0, %l0 ! DRAM_TRTW_REG
1041#if defined(SNG_CHANNEL)
1042 mov 0x0,%l3
1043#else
1044 mov 0x0,%l3
1045#endif
1046#ifdef BANK01
1047 stx %l3, [%l0+%g0]
1048#endif
1049#ifdef BANK23
1050 stx %l3, [%l0+%g1]
1051#endif
1052#ifdef BANK45
1053 stx %l3, [%l0+%g2]
1054#endif
1055#ifdef BANK67
1056 stx %l3, [%l0+%g3]
1057#endif
1058
1059mcuctl_init_b4wmr__ddr2_667_rrd_reg_init:
1060 add %l6, 0x080, %l0 ! DRAM_TRRD_REG
1061#if defined(SNG_CHANNEL)
1062 mov 5,%l3
1063#else
1064 mov 3,%l3
1065#endif
1066#ifdef BANK01
1067 stx %l3, [%l0+%g0]
1068#endif
1069#ifdef BANK23
1070 stx %l3, [%l0+%g1]
1071#endif
1072#ifdef BANK45
1073 stx %l3, [%l0+%g2]
1074#endif
1075#ifdef BANK67
1076 stx %l3, [%l0+%g3]
1077#endif
1078
1079mcuctl_init_b4wmr__ddr2_667_faw_reg_init:
1080 add %l6, 0x0d8, %l0 ! missing from mcu_defines.h
1081 mov 0x0d,%l3
1082#ifdef BANK01
1083 stx %l3, [%l0+%g0]
1084#endif
1085#ifdef BANK23
1086 stx %l3, [%l0+%g1]
1087#endif
1088#ifdef BANK45
1089 stx %l3, [%l0+%g2]
1090#endif
1091#ifdef BANK67
1092 stx %l3, [%l0+%g3]
1093#endif
1094
1095#endif // end of !#ifdef DDR2_533
1096
1097! DRAM_CAS_LAT_REG
1098#ifdef VARY_CAS_LATENCY
1099mcuctl_init_b4wmr__DRAM_CAS_LAT_REG:
1100 add %l6, 0x010, %l0
1101 mov CAS_LATENCY,%l3
1102#ifdef BANK01
1103 stx %l3, [%l0+%g0]
1104#endif
1105#ifdef BANK23
1106 stx %l3, [%l0+%g1]
1107#endif
1108#ifdef BANK45
1109 stx %l3, [%l0+%g2]
1110#endif
1111#ifdef BANK67
1112 stx %l3, [%l0+%g3]
1113#endif
1114
1115#endif
1116
1117#endif // DTM_ENABLED
1118
1119done_mcuctl_init_b4wmr:
1120
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